JP2006311210A - Limiter amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a limiter amplifier circuit in which a favorable common mode noise tolerance is attained and a high speed response to an input signal is ensured. <P>SOLUTION: The limiter amplifier circuit comprises a differential amplifier 2 for amplifying a differential input signal composed of a positive-phase input signal VIP and a negative-phase input signal VIN, and an AOC circuit 3 for drawing out a current corresponding to the voltage difference of a maximum value between the positive-phase input signal VIP and the negative-phase input signal VIN from a pair of load resistors 24 and 25 provided on the input stage of the differential amplifier 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a station side device of an optical transmission system, and more particularly to a limiter amplifier circuit that compensates for an offset of a signal received from a home side device.

  2. Description of the Related Art Conventionally, as an optical transmission system that enables high-speed data transmission, a passive optical network (hereinafter referred to as PON) system that time-multiplexes a data signal packet for each subscriber is known. FIG. 8 shows the configuration of this PON system. In the PON system, a plurality of home side devices (ONUs) 102-1 to 102-n are connected to one station side device (OLT) 101 via a passive device such as an optical coupler 103. Reference numeral 104 denotes an optical fiber.

  Upstream packet data from each home-side device 102-1 to 102-n is time-multiplexed and reaches the station-side device 101. At this time, the transmission distance to the station-side device 101 is different for each home-side device. The optical power when reaching the station-side device 101 is different for each home-side device. FIG. 9 shows packet data from each of the home side devices 102-1 to 102-n reaching the station side device 101. In FIG. 9, 105-1 to 105-n are packet data from the home side devices 102-1 to 102-n, and 106-1 to 106-n are added to the head of the packet data 105-1 to 105-n. It is a preamble.

  Thus, in the PON system, since the transmission distance is different for each home-side apparatus, it is necessary for the station-side apparatus 101 to receive optical signals having different reception levels. In other words, the receiving circuit of the station side apparatus 101 needs to compensate for this difference in reception level and generate a signal of a certain level that can be discriminated and reproduced by the discriminator.

  As means for compensating the difference in level of the received signal, there are a method for detecting the level of the received signal and controlling the gain of the amplifier, and a method for detecting the level of the received signal and compensating for the difference in the amplitude center, that is, the offset. is there. In particular, in a PON system with a short interval between packets, since the high-speed compensation of the reception level difference is required, the latter offset compensation method having a high response speed is used. That is, an offset compensation circuit (hereinafter referred to as an AOC circuit) has been conventionally used to cancel this offset.

FIG. 10 shows a configuration of a conventional receiving circuit of the station side device 101. Reference numeral 100 denotes a light receiving element such as a photodiode that converts a received optical signal into a current and outputs it, 200 denotes a preamplifier circuit that converts a current output from the light receiving element 100 into a differential voltage, and 300 denotes an output from the preamplifier circuit 200. It is a limiter amplifier circuit that performs offset compensation of the differential output signal.
Conventionally, as a limiter amplifier circuit, a configuration shown in FIG. 11 (for example, see Patent Document 1) and a configuration shown in FIG. 12 have been proposed (for example, see Patent Document 2).

  The limiter amplifier circuit of FIG. 11 includes differential amplifiers 301 and 302 and an AOC circuit 303. The differential amplifier 302 includes transistors 320 to 323, load resistors 324 and 325, and constant current sources 326 and 327, and the AOC circuit 303 includes peak detectors 330 and 331 and a differential amplifier 332. Has been. In this limiter amplifier circuit, the maximum value of the positive phase output of the differential amplifier 301 is detected and held by the peak detector 330, and the maximum value of the negative phase output of the differential amplifier 301 is detected by the peak detector 331. Hold. By inputting the outputs of the peak detectors 330 and 331 to the differential amplifier 332, the positive phase output of the differential amplifier 332 indicates an intermediate value of the positive phase output of the differential amplifier 301, and the reverse phase of the differential amplifier 332. The output indicates an intermediate value of the negative phase output of the differential amplifier 301.

  The positive phase output of the differential amplifier 332 is input to the gate of the transistor 321 which is the first reference input terminal of the differential amplifier 302, and the negative phase output of the differential amplifier 332 is input to the second amplifier of the differential amplifier 302. The signal is input to the gate of the transistor 322 which is a reference input terminal. Thus, the limiter amplifier circuit of FIG. 11 cancels the offset of the signal input to the differential amplifier 301 from the preamplifier circuit.

  The limiter amplifier circuit of FIG. 12 includes a differential amplifier 304, an output buffer 305, and an AOC circuit 306. The AOC circuit 306 includes a peak detection unit 360 and an offset compensation signal generation unit 361. In this limiter amplifier circuit, the maximum value of the positive phase output and the maximum value of the negative phase output of the differential amplifier 304 are detected and held by the peak detector 360. The offset compensation signal generation unit 361 generates an offset compensation signal based on the difference between the positive phase output and the negative phase output of the peak detection unit 360, and adds this offset compensation signal to the output of the differential amplifier 304. As a result, the limiter amplifier circuit of FIG. 12 cancels the offset of the signal input from the preamplifier circuit to the differential amplifier 304.

The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
Japanese Patent No. 3354892 Japanese Patent Laid-Open No. 08-250955

However, in the limiter amplifier circuit shown in FIG. 11, the offset compensation signal output from the AOC circuit 303 is input to the reference input terminal of the differential amplifier 302 that amplifies the input signal. There was a problem that noise resistance deteriorated.
In the limiter amplifier circuit shown in FIG. 12, an offset compensation signal is generated from the output of the differential amplifier 304 that amplifies the input signal, and this offset compensation signal is added to the output of the differential amplifier 304. There was a problem that the response to the signal was slow.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a limiter amplifier circuit that can obtain good common-mode noise resistance and can perform high-speed response to an input signal.

The present invention provides a limiter amplifier circuit that performs offset compensation of an input signal, a differential amplifier that amplifies the differential input signal composed of a positive phase input signal and a negative phase input signal, and a maximum of the positive phase input signal. And an offset compensation circuit that extracts a current corresponding to a voltage difference between the value and the maximum value of the negative-phase input signal from a pair of loads of the differential circuit provided in the input stage of the differential amplifier. .
Further, in one configuration example of the limiter amplifier circuit of the present invention, the differential circuit of the differential amplifier has the positive phase input signal input to one input terminal of the pair of loads and the pair of input terminals. The negative input signal is input to the other input terminal, and a pair of output terminals are connected to the pair of loads. The first transistor has a differential configuration, and the offset compensation circuit includes: A first level detection unit that detects and holds the maximum value of the positive phase input signal, a second level detection unit that detects and holds the maximum value of the negative phase input signal, and a pair of input terminals The output signal of the first level detection unit is input to one input terminal, the output signal of the second level detection unit is input to the other input terminal, and a pair of output terminals are connected to the pair of loads. Consisting of a second transistor of differential configuration connected A.
In one example of the limiter amplifier circuit according to the present invention, the second transistor is a MOS transistor.
Moreover, in one configuration example of the limiter amplifier circuit of the present invention, the offset compensation circuit further includes a pair of resistors inserted in series with the pair of output terminals of the second transistor.
Further, in one configuration example of the limiter amplifier circuit of the present invention, the gain of the differential amplifier is 1.
In addition, one configuration example of the limiter amplifier circuit of the present invention is a configuration in which the differential amplifier and the offset compensation circuit are used as structural units, and the structural units are connected in series in a plurality of stages.

  According to the present invention, a current corresponding to the voltage difference between the maximum value of the positive phase input signal and the maximum value of the negative phase input signal is obtained from a pair of loads of the differential circuit provided in the input stage of the differential amplifier. By providing the offset compensation circuit that is pulled out, it is possible to obtain a higher common-mode noise resistance than in the prior art, and a high-speed response to an input signal is possible.

  In the present invention, the second transistor of the offset compensation circuit is a MOS transistor, so that the hold performance of the first and second level detectors of the offset compensation circuit can be improved. That is, since the MOS transistor has almost no gate leakage current, it is possible to provide high level hold characteristics.

  Further, in the offset compensation circuit, the gain can be easily adjusted by inserting a pair of resistors in series with the pair of output terminals of the second transistor, so that the accuracy of the offset compensation can be adjusted.

  Further, by setting the gain of the differential amplifier to 1, it is possible to easily adjust the accuracy of offset compensation.

  Further, by using a differential amplifier and an offset compensation circuit as structural units and connecting the structural units in a plurality of stages in series, more accurate offset compensation can be realized.

[First Embodiment]
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a limiter amplifier circuit according to the first embodiment of the present invention. The limiter amplifier circuit according to the present embodiment includes an input buffer 1, a differential amplifier 2, and an AOC circuit 3.

  The differential amplifier 2 includes an NPN transistor 20 whose base is connected to the positive phase output terminal of the input buffer 1, an NPN transistor 21 whose base is connected to the negative phase output terminal of the input buffer 1, and a base whose collector is the collector of the transistor 20. Is connected to the collector of the transistor 21, the base is connected to the collector of the transistor 21, the collector is supplied with the power supply voltage VCC, and one end is supplied with the power supply voltage VCC. A load resistor 24 having the other end connected to the collector of the transistor 20, a power supply voltage VCC applied to one end, a load resistor 25 having the other end connected to the collector of the transistor 21, and an emitter of the transistors 20 and 21 at one end. To the constant current source 26, the other end of which is grounded, and one end of the transistor 2 It is connected to the emitter, and a constant current source 27 whose other end is grounded, one end of which is connected to the emitter of the transistor 23, a constant current source 28 for the other end of which is grounded.

  The AOC circuit 3 includes a level detection unit 30 that detects and holds the maximum value of the normal phase output of the input buffer 1, a level detection unit 31 that detects and holds the maximum value of the negative phase output of the input buffer 1, and a base The level detection signal VholdP of the level detection unit 30 is input to the NPN transistor 32 whose collector is connected to the collector of the transistor 20 of the differential amplifier 2, and the level detection signal VholdN of the level detection unit 31 is input to the base. Is connected to the collector of the transistor 21 of the differential amplifier 2 and a constant current source 34 having one end connected to the emitters of the transistors 32 and 33 and the other end grounded.

  Hereinafter, the operation of the limiter amplifier circuit of the present embodiment will be described. FIG. 2 shows signals of respective parts of the limiter amplifier circuit of FIG. 2A shows a normal phase input signal VIP and a negative phase input signal VIN input to the input buffer 1, a level detection signal VholdP output from the level detection unit 30, and a level detection signal VholdN output from the level detection unit 31. FIG. FIG. 2B is a signal waveform diagram showing a normal phase output signal VOP and a negative phase output signal VON output from the differential amplifier 2. 2A and 2B, V1 is the level of the positive phase input and the negative phase input when no input is applied to the input buffer 1, VIPA is the average level of the positive phase input signal VIP, and VINA is the negative phase input signal. The average level of VIN, ΔV is the offset, and V2 is the level of the positive phase output signal VOP and the negative phase output signal VON when the differential amplifier 2 is not input.

First, the positive phase input signal VIP output from a preamplifier circuit (not shown) is input to the positive phase input terminal of the input buffer 1, and the negative phase input signal VIN output from the preamplifier circuit is input to the negative phase input terminal. Is done.
The differential amplifier 2 amplifies the difference between the positive phase input signal VIP and the negative phase input signal VIN that have passed through the input buffer 1, and outputs the amplification result as a positive phase output signal VOP and a negative phase output signal VON.

  On the other hand, the level detection unit 30 detects and holds the maximum value of the positive phase input signal VIP that has passed through the input buffer 1, and outputs the level detection signal VholdP. Similarly, the level detection unit 31 detects and holds the maximum value of the negative phase input signal VIN that has passed through the input buffer 1, and outputs the level detection signal VholdN.

  FIG. 3 is a circuit diagram illustrating one configuration example of the level detection unit 30. The level detection unit 30 holds the positive value of the positive phase input signal VIP that has passed through the input buffer 1 and the maximum value of the signal output from the output terminal of the buffer amplifier circuit 40. The first hold circuit unit 41 and the second hold circuit unit 42 are configured.

  The first hold circuit unit 41 includes a diode 43 and a hold capacitor 44, and the second hold circuit unit 42 includes a diode 45 and a hold capacitor 46. The output terminal of the buffer amplifier circuit 40 is connected to the input terminal of the first hold circuit unit 41 (the anode of the diode 43) and the input terminal of the second hold circuit unit 42 (the anode of the diode 45). The output terminal of the first hold circuit unit 41, which is a connection point between the cathode of the diode 43 and the first terminal of the hold capacitor 44, is connected to the inverting input terminal (reference voltage input terminal) of the buffer amplifier circuit 40. . On the other hand, the level detection signal VholdP is output from the output terminal of the second hold circuit section 42, which is a connection point between the cathode of the diode 45 and the first terminal of the hold capacitor 46. The second terminals of the hold capacitors 44 and 46 are grounded.

  In the present embodiment, the configuration shown in FIG. 3 makes it possible to realize the level detection unit 30 that can respond to an input signal at high speed and has a small output ripple. Here, the case of the level detection unit 30 has been described as an example, but the level detection unit 31 can also be realized with the same configuration.

  Next, the level detection signals VholdP and VholdN detected as described above are input to the differential transistors 32 and 33. The level detection signal VholdP indicating the maximum value of the normal phase input signal VIP is input to the base of the transistor 32, and the level detection signal VholdN indicating the maximum value of the negative phase input signal VIN is input to the base of the transistor 33, whereby the transistor 32 The voltage difference between the level detection signals VholdN and VholdP (VholdN−VholdP) is output from the collector of the transistor 33, and the voltage difference (VholdP−VholdN) between the level detection signals VholdP and VholdN is output from the collector of the transistor 33.

  The collector of the transistor 32 is connected to the connection point between the collector of the transistor 20 of the differential amplifier 2 and the load resistor 24, and the collector of the transistor 33 is the connection point of the collector of the transistor 21 of the differential amplifier 2 and the load resistor 25. It is connected to the. Therefore, the current corresponding to the voltage difference (VholdN−VholdP) between the level detection signals VholdN and VholdP is extracted from the current flowing through the load resistor 24, and the current corresponding to the voltage difference (VholdP−VholdN) between the level detection signals VholdP and VholdN. The current is extracted from the current flowing through the load resistor 25.

  For example, when the level of the positive-phase input signal VIP increases, the voltage difference (VholdN−VholdP) between the level detection signals VholdN and VholdP increases, so that the base potential of the transistor 32 increases and the collector current of the transistor 32 increases. . Accordingly, since the current flowing through the load resistor 24 increases, the collector potential of the transistor 20 is lowered, thereby canceling the offset.

Thus, in the present embodiment, the normal phase output signal VOP and the negative phase output signal VON in which the offset is canceled as shown in FIG. 2B can be obtained.
In the present embodiment, the output of the AOC circuit is not used as the reference input of the differential amplifier as in the limiter amplifier circuit shown in FIG. 11, but the output of the AOC circuit 3 is used as the load resistors 24 and 25 of the differential amplifier 2. Since the offset compensation is realized by connecting to, high common-mode noise resistance can be obtained as compared with the limiter amplifier circuit shown in FIG. In the present embodiment, since the AOC circuit has a feedforward configuration, a higher speed response to an input signal is possible compared to the limiter amplifier circuit shown in FIG.

[Second Embodiment]
In the first embodiment, bipolar transistors are used for the differential transistors 32 and 33 of the AOC circuit 3, but MOS transistors may be used. When a bipolar transistor is used as in the first embodiment, the charge charged in the hold capacitor 46 of the level detection units 30 and 31 is reduced by the leakage current of the transistor, and the level detection signals VholdP and VholdN are reduced. Gradually decreases.

  On the other hand, when MOS transistors are used as the transistors 32 and 33, the leakage current can be reduced, so that the hold performance of the level detectors 30 and 31 can be improved. That is, the level of the level detection signal VholdP can be maintained at the maximum value of the positive phase input signal VIP, and the level of the level detection signal VholdN can be maintained at the maximum value of the negative phase input signal VIN.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing a configuration of a limiter amplifier circuit according to the third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The limiter amplifier circuit according to the present embodiment includes an input buffer 1, a differential amplifier 2, and an AOC circuit 3a.

The AOC circuit 3a includes a resistor 35 inserted between the emitter of the transistor 32 and one end of the constant current source 34 in the AOC circuit 3 described in the first embodiment, and the emitter of the transistor 33 and the constant current source 34. A resistor 36 is inserted between one end.
By adding the resistors 35 and 36, the amount of current drawn from the load resistors 24 and 25 can be adjusted, and the accuracy of offset compensation can be adjusted.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing a configuration of a limiter amplifier circuit according to the fourth embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The limiter amplifier circuit according to the present embodiment includes an input buffer 1, a differential amplifier 2, and an AOC circuit 3b. The AOC circuit 3b has the same effect as the AOC circuit 3a of the third embodiment, but a resistor 37 is inserted between the collector of the transistor 32 and the collector of the transistor 20 instead of the resistor 35. Instead of the resistor 36, a resistor 38 is inserted between the collector of the transistor 33 and the collector of the transistor 21.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing a configuration of a limiter amplifier circuit according to the fifth embodiment of the present invention. The limiter amplifier circuit according to the present embodiment has a differential amplifier and an AOC circuit as structural units, and the structural units are connected in a plurality of stages in series. In the example of FIG. 6, two structural units are connected. As the differential amplifiers 2-1 and 2-2, the differential amplifier 2 described in the first to fourth embodiments may be used, and the AOC circuits 3-1 and 3-2 may be the first to fourth. Any one of AOC3, 3a, and 3b described in the embodiment may be used. Therefore, description of the circuit configurations of the differential amplifiers 2-1, 2-2 and the AOC circuits 3-1, 3-2 will be omitted.

  FIG. 7 shows signals of respective parts of the limiter amplifier circuit of FIG. 7A shows a normal phase input signal VIP and a negative phase input signal VIN input to the input buffer 1, a level detection signal VholdP output from the level detection unit 30 in the AOC circuit 3-1, and an AOC circuit 3-1. 7B is a signal waveform diagram showing the level detection signal VholdN output from the level detection unit 31 in FIG. 7, and FIG. 7B shows the positive phase input signal VIP2, the negative phase input signal VIN2, and the AOC circuit input to the differential amplifier 2-2. A signal waveform diagram showing the level detection signal VholdP2 output from the level detection unit 30 in 3-2 and the level detection signal VholdN2 output from the level detection unit 31 in the AOC circuit 3-2. FIG. It is a signal waveform diagram which shows the normal phase output signal VOP and the negative phase output signal VON output from the dynamic amplifier 2-2.

The operations of the input buffer 1, the differential amplifier 2-1 and the AOC circuit 3-1 are the same as the operations of the input buffer 1, the differential amplifier 2 and the AOC circuit 3 described in the first embodiment. The amplifier 2-1 outputs a normal phase signal VIP2 and a negative phase signal VIN2.
The operation of the differential amplifier 2-2 is the same as that of the differential amplifier 2-1. That is, the differential amplifier 2-2 amplifies the difference between the positive phase signal VIP2 and the negative phase signal VIN2 output from the differential amplifier 2-1, and the amplification result is converted into the positive phase output signal VOP and the negative phase output signal VON. Output as.

  The operation of the AOC circuit 3-2 is the same as that of the AOC circuit 3-1, but is different from the AOC circuit 3-1, in that the response speed to the input signals VIP2 and VIN2 is slower than that of the AOC circuit 3-1. Therefore, the level detection signal VholdP output from the level detection unit 30 in the AOC circuit 3-1 rises instantaneously according to the positive phase input signal VIP, whereas the level detection unit in the AOC circuit 3-2. As shown in FIG. 7B, the rise of the level detection signal VholdP2 output from 30 is delayed.

  As described above, the reason why the structural units are connected in two stages and the response speed of the AOC circuit 3-2 is made slower than that of the preceding AOC circuit 3-1 is to realize more accurate offset compensation. That is, there is a possibility that the offset cannot be completely canceled in the circuit having one stage of the structural unit described in the first to fourth embodiments. In the example of FIG. 7B, an offset is generated between the positive phase signal VIP2 and the negative phase signal VIN2 output from the differential amplifier 2-1.

  Therefore, the offset is canceled more reliably by connecting the structural units in two stages in series. At this time, it is not preferable for the purpose of canceling the offset that the subsequent structural unit operates before the operation of the structural unit in the previous stage is determined. Therefore, by making the response speed of the AOC circuit 3-2 slower than that of the AOC circuit 3-1, the AOC circuit 3-1 operates, and after the output signals VIP2 and VIN2 of the differential amplifier 2-1 are stabilized, the AOC circuit 3-2 operates. In this way, a normal phase output signal VOP and a negative phase output signal VON with offset canceled as shown in FIG. 7C can be obtained.

  In order to make the response speed of the AOC circuit 3-2 slower than that of the AOC circuit 3-1, the capacitance values of the hold capacitors 44 and 46 of the level detectors 30 and 31 in the AOC circuit 3-2 are set in the AOC circuit 3-1. What is necessary is just to make it larger than the hold capacity | capacitances 44 and 46 of the level detection parts 30 and 31. FIG.

  In the first to fifth embodiments, the gain of the differential amplifier 2 may be 1. In particular, in the multi-stage limiter amplifier circuit shown in FIG. 6, if the gain of each differential amplifier 2 is greater than 1, the offset may increase, so the gain of each differential amplifier 2 is set to 1. Is particularly effective in the fifth embodiment.

  The present invention can be applied to, for example, a station side device of an optical transmission system.

1 is a circuit diagram showing a configuration of a limiter amplifier circuit according to a first embodiment of the present invention. FIG. 2 is a signal waveform diagram showing signals at various parts of the limiter amplifier circuit of FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration example of a level detection unit in the AOC circuit of FIG. 1. It is a circuit diagram which shows the structure of the limiter amplifier circuit used as the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the limiter amplifier circuit used as the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the limiter amplifier circuit used as the 5th Embodiment of this invention. FIG. 7 is a signal waveform diagram showing signals at various parts of the limiter amplifier circuit of FIG. 6. It is a block diagram which shows the structure of a PON system. It is a figure which shows the packet data from each home side apparatus which arrives at a station side apparatus. It is a block diagram which shows the structure of the conventional receiving circuit of the station side apparatus in a PON system. It is a circuit diagram which shows one structural example of the conventional limiter amplifier circuit. It is a circuit diagram which shows the other structural example of the conventional limiter amplifier circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Input buffer, 2, 2-1, 2-2 ... Differential amplifier 3, 3-1, 3-2, 3a, 3b ... AOC circuit, 20-23, 32, 33 ... NPN transistor, 24, 25 ... load resistance, 30, 31 ... level detection part, 35-38 ... resistance.

Claims (6)

In the limiter amplifier circuit that performs offset compensation of the input signal,
A differential amplifier that amplifies the input signal in a differential format composed of a normal phase input signal and a negative phase input signal;
Offset compensation for extracting a current corresponding to a voltage difference between the maximum value of the positive-phase input signal and the maximum value of the negative-phase input signal from a pair of loads of a differential circuit provided in the input stage of the differential amplifier And a limiter amplifier circuit. The limiter amplifier circuit according to claim 1,
The differential circuit of the differential amplifier is:
The pair of loads;
The positive phase input signal is input to one input terminal of the pair of input terminals, the negative phase input signal is input to the other input terminal, and the pair of output terminals are connected to the pair of loads. A first transistor of differential configuration,
The offset compensation circuit is
A first level detector that detects and holds the maximum value of the positive phase input signal;
A second level detection unit for detecting and holding the maximum value of the negative phase input signal;
The output signal of the first level detection unit is input to one input terminal of the pair of input terminals, and the output signal of the second level detection unit is input to the other input terminal. And a second transistor having a differential configuration connected to the pair of loads. The limiter amplifier circuit according to claim 2,
2. The limiter amplifier circuit according to claim 1, wherein the second transistor is a MOS transistor. The limiter amplifier circuit according to claim 2,
The limiter amplifier circuit further comprises a pair of resistors inserted in series with the pair of output terminals of the second transistor. The limiter amplifier circuit according to claim 1,
A limiter amplifier circuit characterized in that a gain of the differential amplifier is unity. The limiter amplifier circuit according to any one of claims 1 to 5,
A limiter amplifier circuit comprising the differential amplifier and the offset compensation circuit as structural units, the structural units being connected in series in a plurality of stages.

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