JP2006311038A - Amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in the conventional amplifier of a configuration for controlling an amplifier output by controlling the power supply voltage of multi-stage amplifiers by a series regulator, operation stability and operation efficiency are low. <P>SOLUTION: The amplifier whose output power is adjusted by an input control signal includes: an error amplifier 121 receiving the input control signal Vin; a first emitter follower transistor 123 for receiving the output of the error amplifier 121; a second emitter follower transistor 122; a feedback circuit 150 for coupling the output of the second emitter follower transistor 122 to an input to the error amplifier 121; a driver stage transistor 111 for receiving a power supply voltage by the output of the first emitter follower transistor 123; and a final stage transistor 112 connected to the output of the driver stage transistor 111 and for receiving the power supply voltage with the output of the second emitter follower transistor 122. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an amplifier and an information communication device using the amplifier. For example, the present invention relates to an amplifier used in a radio transmitter that operates at a high frequency and an information communication device equipped with the amplifier.

  In portable terminals such as mobile phones, the life of batteries has become a major issue as power consumption increases with the recent increase in functionality. In particular, an amplifier in a transmission unit of a radio circuit consumes a large amount of power and greatly affects the life of a battery. Therefore, reducing the power consumption of the amplifier is an important issue.

  FIG. 5 shows a configuration of a conventional amplifier used in a mobile phone (first conventional technology). In general, the power level of the output signal of the mobile phone changes according to the distance to the base station. For example, when the distance to the base station is short, the output level of the mobile phone becomes small. The amplifier is configured to control the power level output from the output terminal 504 of the amplifier by a control signal input from the input terminal 502 (for example, Patent Document 1).

  Here, the high-frequency signal input from the input terminal 501 is set to a power level sufficient to saturate the driver stage amplifier 510 and the final stage amplifier 511 of the multistage amplifier. On the other hand, a control signal input from the input terminal 502 is input to the series regulator 505 and amplified. The series regulator 505 includes an error amplifier 506, resistors 507 and 508, and an emitter follower type transistor 522. After being amplified by the series regulator 505, it is input to the power supply units of the driver stage amplifier 510 and the final stage amplifier 511. Here, since the power supply section of the driver stage amplifier 510 and the final stage amplifier 511 are joined and controlled at the same potential by the output of the series regulator 505, it is possible to output from a lower output power to a higher output power level. It is.

  Here, the solid line in FIG. 3 shows the relationship between the control signal voltage Vin input from the input terminal 502 and the output voltage Vout output from the output terminal 504. In the configuration of FIG. 5, since the driver stage amplifier 510 and the final stage amplifier 511 are saturated and the voltage Vout increases in proportion to the voltage Vin, the voltage Vout can be controlled with high accuracy by the voltage Vin.

  Normally, a relatively large capacitor is connected to the power supply unit of the amplifier so that a high-frequency signal does not leak. However, when the power supply unit of the driver stage amplifier 510 and the final stage amplifier 511 are connected in close proximity, the capacitance is more It is necessary to secure isolation between the driver stage amplifier 510 and the final stage amplifier 511 by connecting a large capacitor to the power supply unit. If sufficient isolation cannot be ensured, the signal leaked from the power supply unit of the final stage amplifier 511 is likely to be in an unstable state such as being fed back to the power supply unit of the driver stage amplifier 510 and oscillating. In the amplifier shown in FIG. 5, when the control signal input from the input terminal 502 is high speed, if a capacitor having a large capacitance value is connected to the power supply units of the driver stage amplifier 510 and the final stage amplifier 511, the driver stage amplifier 510 is provided. There is a problem that the input control signal to the power supply unit of the final stage amplifier 511 is distorted.

FIG. 6 shows another configuration example of the conventional amplifier (second prior art). In this system, individual series regulators 605 and 620 are connected to a driver stage amplifier 610 and a final stage amplifier 611 of the multistage amplifier to control the output power of the multistage amplifier. The series regulator 605 includes resistors 613 and 614, an emitter follower type transistor 612, and an error amplifier 615. The series regulator 620 includes resistors 623 and 624, an emitter follower type transistor 622, and an error amplifier 621. As is apparent from the configuration of FIG. 6, this method is stable because the power supply units of the driver stage amplifier 610 and the final stage amplifier 611 are not connected and isolation is ensured. However, since this method has a series regulator individually, a plurality of error amplifiers are required. As a result, the size and cost increase, and the power consumption of the error amplifier increases. .
US Pat. No. 6,701,138

  As described above, in a conventional amplifier that uses a series regulator to control the power supply voltage of a multistage amplifier and control the output power of the multistage amplifier, the driver stage amplifier and the power supply section of the final stage amplifier are connected and controlled at the same potential. In the configuration (first prior art), when the power supply unit of the multistage amplifier is driven by a high-speed control signal, a capacitor having a large capacitance value is connected to the power supply unit of the multistage amplifier to thereby connect the driver stage amplifier and the final stage amplifier. Therefore, there is a problem that the output power from the final stage amplifier is fed back to the power supply unit of the driver stage amplifier and oscillates.

  In addition, in the method of controlling the output of the multistage amplifier by connecting individual series regulators to the driver stage amplifier and the final stage amplifier of the multistage amplifier (second prior art), a plurality of error amplifiers are required. There is a problem that the size and cost increase and the power consumption of the error amplifier increases.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described conventional problems, and to realize an amplifier that is low in cost, small in size, and stably operates with low power consumption.

  In order to solve the above-described problems, the present invention provides an amplifier in which output power is adjusted by an input control signal, an error amplifier to which the input control signal is input, and a first emitter that inputs an output of the error amplifier. The follower type transistor, the second emitter follower type transistor, the feedback circuit that couples the output of the second emitter follower type transistor and the input of the error amplifier, and the output of the first emitter follower type transistor provide the power supply voltage. A driver stage transistor to be applied; and a final stage transistor connected to an output of the driver stage transistor and to which a power supply voltage is applied by an output of the second emitter follower transistor.

  In addition, a voltage dividing circuit for dividing the output of the error amplifier and inputting the divided voltage to the first emitter follower transistor is provided.

  Further, a DC bias voltage is applied to the voltage dividing circuit.

  The output voltage of the first emitter follower transistor is adjusted by adjusting a voltage dividing ratio of the voltage dividing circuit in accordance with output power of the amplifier.

  A first switching regulator connected to a power supply terminal of the first emitter follower transistor; a second switching regulator connected to a power supply terminal of the second emitter follower transistor; And the second switching regulator outputs a voltage at which the first emitter follower transistor and the second emitter follower transistor are not saturated.

  Further, each of the first switching regulator and the second switching regulator outputs a different voltage, or the output voltage of the first switching regulator is the same level as the output voltage of the second switching regulator or It is characterized by being low.

  The amplifier is a polar modulator.

  Furthermore, an information communication device according to the present invention includes the amplifier according to the present invention.

  According to the amplifier of the present invention, it is possible to realize an amplifier that is low in cost, small in size, and stably operates with low power consumption, and is useful for a transmitter of a communication device.

  FIG. 1 shows a configuration of an amplifier according to an embodiment of the present invention. Hereinafter, the configuration and operation of the amplifier according to the first embodiment will be described with reference to FIG.

  The high-frequency signal input from the input terminal 101 is input to the driver stage amplifier 111 and amplified, then input to the final stage amplifier 112, amplified, and output from the output terminal 105.

  On the other hand, the control signal input from the input terminal 102 is input to the error amplifier 121 of the series regulator 140 and further amplified after being compared with the feedback signal from the feedback network 150. The amplified control signal is branched, one is input to the emitter follower type transistor 122, and the other is input to the emitter follower type transistor 123 via the bias circuit 160. The power supply voltages of the emitter follower type transistors 122 and 123 are supplied from the switching regulators 132 and 131 from the collector terminals 104 and 103, respectively. Each of the switching regulator 131 and the switching regulator 132 outputs a different voltage output. A control signal having substantially the same potential as the input control signal is output from the emitter terminal of the emitter follower type transistor 122 and further branched, and one output is input to the power supply unit of the final stage amplifier 112, and the other is It is fed back to the error amplifier 121 via the feedback network 150.

  On the other hand, the control signal input to the bias circuit 160 is divided by the variable resistor 126 and the resistor 127, and the divided signal is input to the emitter follower transistor 123. A control signal having substantially the same potential as the voltage of the input control signal is output from the emitter terminal and input to the power supply unit of the driver stage amplifier 111.

  Next, the driving method of the driver stage amplifier 111 and the final stage amplifier 112 will be described with reference to FIG. FIG. 2A shows the relationship between the input power Pin and the output power Pout at each power supply voltage of the final stage amplifier 112. A saturation power proportional to the square of the voltage V is output with respect to the power supply voltage V. That is, if the final stage amplifier 112 is saturated, power approximately proportional to the power supply voltage V is output. Therefore, it is possible to control the output power of the final stage amplifier 112 simply by adjusting the voltage V.

  However, since the final stage amplifier 112 generally has a large individual difference in the vicinity of the maximum output, a sufficiently large input power Pin is set so that the maximum output determined by the standard cannot be obtained. It is desirable that the signal is input to the final stage amplifier 112 to be in a supersaturated state. On the other hand, the absolute accuracy of the output when the output power is low is generally not as strict as that at the maximum output. For example, when the output is reduced from 10 dBm to 9 dBm, it is a relatively loose standard in which a relative value of 10 dBm to −1.5 dB to −0.5 dB lower power value may be set. That is, for example, in order to output Pout3 lower than the maximum output, even if the input power Pin3 is not input, if the Pin3 ′ having a power level lower than Pin3 is input, the final amplifier 112 has a power in a range that satisfies the standard. It is possible to output.

  FIG. 2B shows the relationship between the power supply voltage of the driver stage amplifier 111 and the output power. Assuming that the output power of the driver stage amplifier 111 is directly input to the final stage amplifier 112, the final stage amplifier 112 is in an over-input state in order to reliably obtain an output of Pout4 or more. The driver stage amplifier 111 needs to output Pin4. Therefore, the voltage applied to the power source of the driver stage amplifier 111 is 4 × V.

  In order for the final stage amplifier 112 to output Pout3 lower than the maximum output Pout4, it is only necessary to input Pin3 ′ as described above. For the driver stage amplifier 111 to output Pin3 ′, the power source of the driver stage amplifier 111 is required. It is sufficient to apply 3 × V ′ as the voltage. In order to output the voltage 3 × V ′ from the emitter follower transistor 122 at the same time as the voltage 3 × V is output from the emitter follower transistor 122, the gain is reduced by changing the voltage dividing ratio of the bias circuit 160. As one method for realizing this, the resistance value of the variable resistor 126 may be changed. Furthermore, the outputs of the switching regulators 131 and 132 are set to 3 × V + α and 3 × V ′ + α, respectively, by adding a voltage drop α between the collector and the emitter of the emitter follower type transistor to 3 × V and 3 × V ′, respectively. Then, the power consumption in the driver stage amplifier 111 can be reduced as compared with the case where 3 × V is applied. The output voltage of the switching regulator 131 only needs to be the same level as or lower than the output voltage of the switching regulator 132.

  Similarly, when the outputs Pout2 and Pout1 are obtained by the final stage amplifier 112, the bias circuit 160 is adjusted to apply 2 × V ′ and 1 × V ′ as the power supply voltage of the driver stage amplifier 111, and at the same time, the switching regulator 131 If 2 × V ′ + α and 1 × V ′ + α are applied as output voltages, it is possible to reduce power consumption at each output power.

  However, when the power supply voltage of the driver stage amplifier 111 is close to zero, the output power of the driver stage amplifier 111 becomes too low and the final stage amplifier 112 does not saturate. As shown by the dotted lines in FIG. The proportional relationship may not be maintained. As one method for avoiding this, as shown in FIG. 4, a DC voltage Vx that also indicates 128 is applied in the bias circuit. As a result, the final stage amplifier 112 is always saturated and the linear characteristic shown by the solid line in FIG. 3 can be secured.

  The second advantage of this method is that the power consumption of the error amplifier can be reduced. Conventionally, an error amplifier is individually provided for a plurality of emitter follower type transistors. However, in the present invention, a plurality of emitter follower type transistors are driven by one error amplifier, thereby reducing power consumption in the error amplifier. It becomes possible.

  The third advantage of this system is that the amplifier can be stably operated even when the multistage amplifier is driven by one error amplifier. Conventionally, when a multi-stage amplifier is driven by a single error amplifier, it is necessary to connect the power supply section of the driver stage amplifier and the final stage amplifier. However, when driving the power supply unit with a high-speed control signal, it is difficult to connect a capacitor having a large capacitance value to the power supply unit to ensure isolation between the driver stage amplifier and the final stage amplifier. In the present invention, since the power supply sections of the driver stage amplifier and the final stage amplifier are connected via the emitter follower type transistors that apply the respective power supplies, it is possible to ensure a greater isolation than when directly connected. And more stable operation is possible.

  The configuration of the above embodiment can also be applied to an amplifier that performs polar modulation operation.

  In addition, if the amplifier of the above embodiment is mounted on an information communication device such as a mobile phone, a PDA, or a communication card, the amplifier of the present invention with low cost and low power consumption can be provided, so that the information communication device can be used as an information communication device. A low cost and low power consumption device can be realized.

  According to the amplifier of the present invention, it is possible to realize a stable and low power consumption amplifier, which is useful for a transmitter of an information communication device.

Configuration diagram of an amplifier according to an embodiment of the present invention The figure which shows the relationship between the input power and output power of the amplifier which concerns on embodiment of this invention The figure which shows the relationship between the input voltage of the amplifier which concerns on embodiment of this invention, and output power Bias circuit diagram of conventional amplifier Configuration diagram of conventional amplifier Configuration diagram of conventional amplifier

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Input terminal 102 Input terminal 103 Input terminal 104 Input terminal 105 Output terminal 111 Driver stage amplifier 112 Final stage amplifier 121 Error amplifier 122 Emitter follower type transistor 123 Emitter follower type transistor 124 Resistance 125 Resistance 126 Variable resistance 127 Resistance 128 DC voltage 131 Switching Regulator 132 Switching regulator 140 Series regulator 150 Feedback network

Claims (9)

In an amplifier whose output power is adjusted by an input control signal,
An error amplifier to which the input control signal is input;
A first emitter-follower transistor and a second emitter-follower transistor that receive the output of the error amplifier;
A feedback circuit for coupling the output of the second emitter-follower transistor and the input of the error amplifier;
A driver stage transistor to which a power supply voltage is applied by an output of the first emitter follower transistor;
A final stage transistor connected to the output of the driver stage transistor and to which a power supply voltage is applied by the output of the second emitter follower transistor;
An amplifier comprising: 2. The amplifier according to claim 1, further comprising a voltage dividing circuit that divides an output of the error amplifier and inputs the divided output to the first emitter-follower transistor. The amplifier according to claim 2, wherein a DC bias voltage is applied to the voltage dividing circuit. 4. The output voltage of the first emitter-follower transistor is adjusted by adjusting a voltage dividing ratio of the voltage dividing circuit according to output power of the amplifier. 5. amplifier. A first switching regulator is connected to a power supply terminal of the first emitter-follower transistor;
A second switching regulator is connected to a power supply terminal of the second emitter-follower transistor;
2. The first switching regulator and the second switching regulator each output a voltage at which the first emitter-follower transistor and the second emitter-follower transistor are not saturated. 5. The amplifier according to any one of 4. 5. The amplifier according to claim 1, wherein each of the first switching regulator and the second switching regulator outputs a different voltage. 6. The amplifier according to claim 6, wherein an output voltage of the first switching regulator is equal to or lower than an output voltage of the second switching regulator. The amplifier according to claim 1, wherein the amplifier is a polar modulator. An information communication device comprising the amplifier according to claim 1.

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