JP2006310462A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow countermeasure against software error by adding a high resistance to a node, with no large modification in a manufacturing process, with a simple configuration. <P>SOLUTION: The semiconductor device comprises: first and second CMOS inverter circuits constituting an SRAM memory cell; and first and second resistive elements that are provided to connect one input terminal and the other output terminal of the CMOS inverter circuits. Polysilicon patterns 11a and 11b are provided to connect gate electrode patterns 7a and 7b of the two CMOS inverter circuits to nodes Nb and Na of the two CMOS inverter circuits. A high resistance part 11a1 is formed by self-matching on the polysilicon patterns 11a and 11b by utilizing a stepped shape of the base material, and the high resistance part 11a1 constitutes first and second resistance elements. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an SRAM memory cell having two CMOS as an inverter circuit as a memory element among semiconductor devices and a method for manufacturing the same.

  In a semiconductor device called a full-CMOS SRAM (Static Random Access Memory), one memory cell is composed of six MOS transistors. Each memory cell is considered to have a pattern such as a point symmetric type or a line symmetric type in plan view.

  By the way, in such an SRAM, the occurrence of a soft error in which the stored content changes due to a neutron beam or α ray incident from the outside is a problem. It has been found that this soft error can be reduced by inserting a resistor or a capacitor in the node portion of the SRAM memory cell circuit.

As an SRAM with such soft error countermeasures, for example, as shown in Patent Document 1, a configuration in which a resistance is added to a node portion is considered. Here, the configuration in which a high resistance is added to the node portion tends to reduce the operation speed. However, in the low power consumption type SRAM, since the operation speed is not prioritized, sufficient countermeasures are taken. It can be said that.
USP-6529401

  In the above-described Patent Document 1, for example, a tungsten (W) film is formed as a material having a higher resistance value than cobalt silicide (CoSi) in order to add high resistance to the node portion of the memory cell. The resistor is provided as a resistor electrically connected to the node portion by patterning.

  As a result, the resistance can be made higher than that of the silicide formed in the salicide process, which is an excellent countermeasure against soft errors. However, in the conventional structure described above, a tungsten film is used as a manufacturing process. Since one extra layer is formed, there is a problem that practical adoption is difficult in that the number of steps increases and the cost increases.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having a SRAM memory cell having a configuration using a conventional type CMOS inverter with a simple configuration and in a manufacturing process. However, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same which can take a soft error countermeasure by adding a high resistance to a node portion without major changes.

  A semiconductor device according to the present invention includes a semiconductor substrate, first and second CMOS inverter circuits formed on the semiconductor substrate and constituting an SRAM memory cell, and one input of the first and second CMOS inverter circuits. A gate electrode pattern serving as an input terminal of the first and second CMOS inverter circuits, the first and second resistance elements provided so as to connect the terminal and the other output terminal to each other; A high resistance formed by providing a polysilicon pattern for electrically connecting a node serving as an output terminal of the second and first CMOS inverter circuits, and forming the polysilicon pattern in a self-aligned manner using a stepped shape of a base A portion is provided, and the first and second resistance elements are configured by the high resistance portion of the polysilicon pattern.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode pattern on a semiconductor substrate, a step of depositing an interlayer insulating film on the gate electrode pattern, and forming a hole for forming a step in the interlayer insulating film. A step of depositing polysilicon on the interlayer insulating film in which the holes are formed, and processing the polysilicon film to form the gate electrode pattern and an output terminal of an inverter circuit constituting an SRAM memory cell Forming a polysilicon pattern for electrically connecting the nodes constituting the substrate, and implanting impurity ions into the polysilicon pattern, and in the step of implanting impurity ions, the polysilicon pattern Of these, the high resistance portion is formed in a portion along the inner surface of the step forming hole.

  According to the semiconductor device of the present invention, the resistance element provided as a countermeasure against the soft error of the SRAM memory cell is configured by the high resistance portion formed in a self-aligned manner on the polysilicon pattern by using the step shape of the base. So it can be achieved with a simple configuration.

  In addition, according to the method for manufacturing a semiconductor device of the present invention, a resistance element can be formed in the process of forming the SRAM memory cell without significantly changing the layout or adding a large number of processes. Can do it. Further, in the step of implanting impurity ions, a high resistance portion is formed in a self-aligned portion along the inner surface of the step forming hole in the polysilicon pattern, so that it is necessary to add a lithography step. Disappears.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view showing one SRAM memory cell 2 formed on the main surface side of a semiconductor substrate 1, and is a plan view showing a state in which a gate electrode is formed. FIG. 2 shows an electrical configuration for one SRAM memory cell 2.

  First, the electrical configuration will be briefly described. In FIG. 2, the SRAM memory cell 2 is of a general Full-CMOS type and is composed of six MOSFETs. Six MOSFETs (hereinafter simply referred to as transistors) are composed of two p-channel transistors Tp1 and Tp2, and four n-channel transistors Tn1 to Tn4.

  Transistors Tp1 and Tn1 constitute an inverter circuit In1, and transistors Tp2 and Tn2 constitute an inverter circuit In2. These inverter circuits In1 and In2 are connected between power supply terminals Vcc and Vss (GND), respectively.

  The n-channel transistor Tn3 has a source / drain terminal connected between the data line Da and the output terminal Na (node) of the inverter circuit In1, and similarly, the n-channel transistor Tn4 has a source / drain terminal connected to the data terminal. It is connected between the line Db and the output terminal Nb (node) of the inverter circuit In2. The gate terminals of the transistors Tn3 and Tn4 are connected to the word line WL.

  The output terminal Na of the inverter circuit In1 is connected to a common gate terminal of the transistors Tp2 and Tn2 which are input terminals of the inverter circuit In2 via a resistor R1 as a resistance element, and the output terminal of the inverter circuit In2 Nb is connected to a common gate terminal of the transistors Tp1 and Tn1 which are input terminals of the inverter circuit In1 via a resistor R2 as a resistance element. The SRAM memory cell 2 has a configuration that can reduce soft errors by the action of the resistors R1 and R2.

  Next, the overall arrangement configuration of the SRAM memory cell 2 will be described with reference to FIG. Although one SRAM memory cell is shown in FIG. 1 for the sake of simplification, in practice, as a semiconductor memory device, a large number of chips corresponding to the storage capacity are arranged on a chip so as to be symmetrical with each other. Is formed.

  In the SRAM memory cell 2, an element formation region is partitioned in the vertical direction in the figure by STI (Shallow Trench Isolation) 3 embedded and formed as an insulation isolation region in a semiconductor substrate 1 made of silicon single crystal. In the element formation region, N wells (N-well) 4a and 4b are formed corresponding to the transistors Tp1 and Tp2 which are p channel MOSFETs, and P wells (P−) corresponding to the transistors Tn1 to Tn4 which are n channel MOSFETs. well) 5a and 5b are formed.

  Gate oxide films (not shown) as gate insulating films are formed on the upper surfaces of the N wells 4a and 4b and the P wells 5a and 5b, respectively, and gate electrode patterns 7a to 7d made of polycrystalline silicon are formed on the wells. They are arranged and formed so as to be orthogonal to the forming direction. Source / drain regions are formed in regions sandwiching the gate electrode patterns 7a to 7d of the wells 4a, 4b, 5a, and 5b, and the transistors Tp1, Tp2, and Tn1 to Tn4 are formed.

  Specifically, the transistor Tp1 is formed at a portion where the gate electrode pattern 7a intersects with the N well 4a, and the transistor Tn1 is formed at a portion where the gate electrode pattern 7a intersects with the P well 5a. A transistor Tp2 is formed at a portion where the gate electrode pattern 7b intersects with the N well 4b, and a transistor Tn2 is formed at a portion where the gate electrode pattern 7b intersects with the P well 5b. A transistor Tn3 is formed at a portion where the gate electrode pattern 7c intersects the P well 5a, and a transistor Tn4 is formed at a portion where the gate electrode pattern 7d intersects the P well 5b. With the configuration described above, the SRAM memory cell 2 is arranged and formed so as to be symmetric with respect to the point F where the diagonal lines of the memory cells intersect.

  In this embodiment, the metal zeros (M0) 8a and 8b constituting the nodes Na and Nb of the inverter circuits In1 and In2 are formed so as to intersect the N wells 4a and 4b and the P wells 5a and 5b. . Holes 9a and 9b for connecting to the drain terminals of the transistors Tp1 and Tp2 of the inverter circuits In1 and In2 are provided at one end of the metal zeros 8a and 8b, and the inverter circuit In1 is provided at the other end of the metal zeros 8a and 8b. , Holes 10a and 10b are provided for connection to the drain terminals of the In2 transistors Tn1 and Tn2.

  Furthermore, in the present embodiment, a substantially L-shaped polysilicon pattern 11a is formed so as to connect the gate electrode pattern 7a and the metal zero 8b (that is, the node Nb). At the same time, a substantially L-shaped polysilicon pattern 11b is formed so as to connect the gate electrode pattern 7b and the metal zero 8a (that is, the node Na). Since these polysilicon patterns 11a and 11b have substantially the same configuration, the polysilicon pattern 11a will be described with reference to FIG. FIG. 3 is a schematic view schematically showing a cross section of a portion indicated by a cutting line AA in FIG. 1 and three-dimensionally showing a polysilicon pattern 11a.

  As shown in FIG. 3, the polysilicon pattern 11a includes a lower horizontal portion 11a1 formed on the gate electrode pattern 7a, a vertical portion 11a2 extending vertically upward from the right end of the lower horizontal portion 11a1 in the drawing, An upper horizontal portion 11a3 extending in the horizontal direction from the upper end portion of the vertical portion 11a2 and having a substantially L shape is provided. Here, the polysilicon pattern 11a is formed as described later, so that the lower horizontal portion 11a1 and the upper horizontal portion 11a3 are low resistance portions, and the vertical portion 11a2 is a high resistance portion. .

  In the case of this configuration, the high resistance vertical portion 11a2 of the polysilicon pattern 11a corresponds to the resistor R1 shown in FIG. 1, and the high resistance vertical portion (not shown) of the polysilicon pattern 11b is the resistance shown in FIG. It corresponds to the body R2. Thereby, the node Na of the inverter circuit In1 is connected to the common gate terminal of the transistors Tp2 and Tn2 which are the input terminals of the inverter circuit In2 via the resistor R1, and the node Nb of the inverter circuit In2 is connected to the inverter circuit. In this configuration, the transistors Tp1 and Tn1, which are input terminals of In1, are connected to a common gate terminal via a resistor R2. As a result, the SRAM memory cell 2 can reduce soft errors by the action of the resistors R1 and R2.

  In FIG. 3 described above, a spacer 12 formed by a normal spacer processing step is provided on the side of the gate electrode pattern 7a. On the gate electrode pattern 7a, a stopper film (Barrier-SiN) 13 for processing the interlayer insulating film is provided. An interlayer insulating film 14 is formed over the entire surface, and a step forming hole 14a for forming a vertical portion 11a2 of the polysilicon pattern 11a is formed in the interlayer insulating film 14. Yes.

  The polysilicon pattern 11a is formed in the hole 14a as described above. Further, an interlayer insulating film 15 is formed over the entire surface of the above structure, and a metal zero 8b constituting the node Nb is formed. By adopting such a configuration, the gate electrode pattern 7a (that is, the common gate terminal of the transistors Tp1 and Tn1 that are the input terminals of the inverter circuit In1) is connected to the metal zero 8b (that is, the inverter) via the polysilicon pattern 11a. The circuit is electrically connected to the node Nb) of the circuit In2.

Next, a manufacturing process of the SRAM memory cell 2a having the above configuration, particularly a process of manufacturing the polysilicon patterns 11a and 11b will be described with reference to FIGS.
First, the well-known manufacturing process of the SRAM memory cell is executed, and the process is performed until the interlayer insulating film 14 is deposited (deposited) on the entire surface as shown in FIG. The steps executed so far are a step of forming an active area (AA) pattern as an element formation region on the semiconductor substrate 1, and an insulating film is buried in a shallow groove portion formed as an insulating isolation region to form an STI3. A step of forming N wells 4a, 4b, P wells 5a, 5b and channel regions by implanting impurity ions, a step of forming a gate oxide film to a predetermined thickness by thermal oxidation, etc., a gate electrode A step of forming the patterns 7a to 7d, a step of forming the spacer 12, a step of forming a source / drain region by introducing impurities by an ion implantation process, a step of forming a salicide, a step of depositing a stopper film 13, and For example, the interlayer insulating film 14 is deposited by a CVD method or the like.

  Next, as shown in FIG. 5, a step of forming a step forming hole 14a in the interlayer insulating film 14 is performed. In this case, the step forming hole 14a is patterned by a lithography process (PEP (Photo Engraving Process)) (that is, a photoresist is applied to the surface of the interlayer insulating film 14, and the hole 14a is opened). A film is formed), and the interlayer insulating film 14 is etched by RIE (Reactive Ion Etching) using the resist film as a mask material.

  At this time, it is necessary to remove the stopper film 13 at the bottom of the hole 14a. The stopper film 13 may be removed simultaneously with the processing of the interlayer insulating film 14. Further, it may be used as a stopper when the interlayer insulating film 14 is processed, and only the stopper film 13 is separately removed after the processing. In the case of the structure to be removed separately, it is necessary to add an RIE process for removing the stopper film 13.

  Then, when the resist is removed (peeled), the structure shown in FIG. 5 is obtained. Subsequently, a polysilicon (Undoped Poly Si) film 16 is deposited on the above structure as shown in FIG. Thereafter, the wiring (specifically, the polysilicon patterns 11a and 11b) is patterned by a lithography process (PEP) (that is, a photoresist is applied to the surface of the polysilicon film 16 to open the wiring portion). A photoresist film is formed), and the polysilicon film 16 is etched by RIE using the resist film as a mask material, and processing for processing the wiring patterns (polysilicon patterns 11a and 11b) is executed. By this wiring pattern processing, polysilicon patterns 11a and 11b having shapes as shown in FIGS. 3 and 7 are formed. 3 and 7 show only the polysilicon pattern 11a.

  Subsequently, when the resist is removed (peeled), the structure shown in FIG. 7 is obtained. Thereafter, as shown in FIG. 8, impurities are implanted into the surfaces of the polysilicon patterns 11a and 11b. In this case, if necessary, an activation thermal process is performed. By the ion implantation, the lower horizontal portion 11a1 and the upper horizontal portion 11a3 of the polysilicon patterns 11a and 11b become low resistance portions, and the vertical portion 11a2 becomes a high resistance portion. In this case, since the impurity ions are not implanted into the vertical portion 11a2, the high resistance remains.

  Then, as shown in FIG. 9, an interlayer insulating film 15 is deposited on the above structure, and the surface thereof is planarized by a general CMP (Chemical Mechanical Polishing) process. By this flattening process, a configuration as shown in FIG. 9 is obtained.

  Thereafter, the well-known manufacturing process of the SRAM memory cell is executed. That is, patterning of CS (contact hole) is performed by PEP, and a process of etching the interlayer insulating film 15 by RIE using a resist film as a mask material is executed. Thereby, CS processing is executed. After the resist was peeled off, patterning of M0 (metal zero) 8a and 8b was performed by PEP (specifically, metal was deposited, a photoresist was applied to the surface, and the M0 portion was opened. A photoresist film is formed), and the metal film is etched by RIE using this resist film as a mask material. Thereby, the processing of M08a and 8b is executed. Then, after removing the resist, a contact embedding (W-Fill) process is executed.

  According to the present embodiment having such a configuration, the polysilicon patterns 11a and 11b that connect the gate electrode patterns 7a and 7b and the nodes Na and Nb are self-aligned using the base step shape (hole 14a). Since the high resistance portion 11a2 is formed and the high resistance portion 11a2 is used as a resistance element (resistors R1 and R2) to the nodes Na and Nb of the SRAM memory cells 2a and 2b, the high resistance portion is formed. Therefore, it is not necessary to add a lithography process for this purpose, and a configuration for countermeasures against soft errors can be realized easily and at low cost.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows. That is, in the above-described embodiment, the polysilicon wiring patterns 11a and 11b are formed and then the impurity ions are implanted. However, the impurity ions are implanted while the polysilicon is deposited on the entire surface of the wafer. Thereafter, a wiring pattern (polysilicon patterns 11a and 11b) may be formed.

  In the above-described embodiment, an example in which the SRAM memory cell is applied to a point-symmetric type is shown. However, depending on a pattern layout, the SRAM memory cell can be applied to a line-symmetric type or another type, and a capacitor. It is applicable also to the thing of the structure which uses together.

Plane layout diagram of SRAM memory cell showing one embodiment of the present invention Electrical circuit diagram Schematic cross-sectional view of the main part Schematic cross-sectional view of the main part corresponding to each stage of the manufacturing process (Part 1) Schematic sectional view of the main part corresponding to each stage of the manufacturing process (Part 2) Schematic cross-sectional view of the main part corresponding to each stage of the manufacturing process (Part 3) Typical sectional drawing of the principal part corresponding to each stage of a manufacturing process (the 4) Typical sectional drawing of the principal part corresponding to each stage of a manufacturing process (the 5) Typical sectional drawing of the principal part corresponding to each step of a manufacturing process (the 6)

Explanation of symbols

  In the drawings, 1 is a semiconductor substrate, 2 is an SRAM memory cell, 4a and 4b are N wells, 5a and 5b are P wells, 7a to 7d are gate electrode patterns, 8a and 8b are metal zeros, 11a and 11b are polysilicon patterns, 14 is an interlayer insulating film, and 14a is a hole.

Claims (4)

A semiconductor substrate;
First and second CMOS inverter circuits formed on the semiconductor substrate and constituting SRAM memory cells;
First and second resistance elements provided so as to connect between one input terminal and the other output terminal of the first and second CMOS inverter circuits;
Providing a polysilicon pattern for electrically connecting a gate electrode pattern serving as an input terminal of the first and second CMOS inverter circuits and a node serving as an output terminal of the second and first CMOS inverter circuits;
A high resistance portion formed in a self-aligned manner using the step shape of the base is provided in the polysilicon pattern,
2. A semiconductor device according to claim 1, wherein the first and second resistance elements are constituted by a high resistance portion of the polysilicon pattern. The polysilicon pattern includes a horizontal portion connected to the gate electrode pattern, a vertical portion continuing to the horizontal portion, and a horizontal portion continuing to the vertical portion and connected to the node. And
2. The semiconductor device according to claim 1, wherein the vertical portion is the high resistance portion, and the two horizontal portions are low resistance portions. Forming a gate electrode pattern on a semiconductor substrate;
Depositing an interlayer insulating film on the gate electrode pattern;
Forming a step-forming hole in the interlayer insulating film;
Depositing polysilicon on the interlayer insulating film in which the holes are formed;
Processing the polysilicon film to form a polysilicon pattern for electrically connecting the gate electrode pattern and a node constituting an output terminal of an inverter circuit constituting an SRAM memory cell;
Injecting impurity ions into the polysilicon pattern,
In the step of implanting impurity ions, a high resistance portion is formed in a portion along the inner surface of the step forming hole in the polysilicon pattern. Forming a gate electrode pattern on a semiconductor substrate;
Depositing an interlayer insulating film on the gate electrode pattern;
Forming a step-forming hole in the interlayer insulating film;
Depositing polysilicon on the interlayer insulating film in which the holes are formed;
Implanting impurity ions into the deposited polysilicon film;
Processing the polysilicon film to form a polysilicon pattern for electrically connecting the gate electrode pattern and a node constituting an output terminal of an inverter circuit constituting an SRAM memory cell;
A method of manufacturing a semiconductor device, wherein, in the step of implanting impurity ions, a high resistance portion is formed in a portion along an inner surface of the step forming hole in the deposited polysilicon film.

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