JP2006308843A - Display panel drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable fine adjustment of a period for displaying a normal image and a black level image without complicating circuit structure when inserting the black level image in a display panel drive circuit. <P>SOLUTION: The display panel drive circuit is equipped with a first shift register 311 which generates a plurality of signals by shifting a first start pulse by being synchronized with a clock signal, a second shift register 312 which generates a plurality of signals by shifting a second start pulse by being synchronized with the clock signal, a logic circuit 316 which generates a plurality of signals for providing timing for selectively activating transistors of each line on the basis of output signals of the first shift register and output signals of the second shift register, a level shift circuit 320 which shifts output potential of the logic circuit, and an output circuit 330 which inputs output signals of the level shift circuit to output a plurality of drive signals. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generally relates to a display panel driving circuit for driving a display panel, and in particular, drives gates of a plurality of TFTs (Thin Film Transistors) included in an LCD (Liquid Crystal Display) panel. The present invention relates to a display panel drive circuit (gate driver).

  An LCD panel of a type incorporating a plurality of TFTs includes one or more display panel driving circuits (source drivers) for driving the TFT sources and one or more display panel driving circuits (for driving the TFT gates). Gate driver). In one or a plurality of source drivers, the image data for each line is converted into an analog image signal, and the image signal is supplied to the TFT source.

  On the other hand, one or a plurality of gate drivers generate a gate potential for turning on the TFTs of the sequentially selected lines and supply the gate potential to the TFT gates. However, since the characteristics deteriorate when a DC voltage is continuously applied to the LCD panel, it is necessary to periodically reverse the polarity of the voltage applied to the LCD panel. Such a driving method is called an inversion driving method.

  Generally, there are a frame inversion method in which the polarity of the voltage is inverted for each frame, a line inversion method in which the polarity of the voltage is inverted for each line, and a dot inversion method in which the polarity of the voltage is inverted for each pixel. is there. Among these driving methods, a large LCD panel mainly uses a dot inversion method or a line inversion method.

  By the way, in the LCD panel, there is a problem that an image blur or a feeling of afterimage is felt when a high-speed moving image in which a display object moves quickly is displayed. In order to solve this problem, a black level image is inserted between frames or fields.

  FIG. 7 shows signal waveforms in a conventional display panel driving circuit. In this display panel driving circuit, a plurality of gate lines included in the LCD panel are divided into three types, and gate signals are masked using three types of negative logic output enable signals OE1 to OE3. Is called.

  As shown in FIG. 7, when the image display start pulse included in the start pulse signal SP becomes high level, it is synchronized with the pulses 1, 2, 3,... Included in the clock signal CLK. The gate lines G1, G2, G3,... Are sequentially driven to display a normal image. Further, when the black level display start pulse included in the start pulse signal SP becomes high level, for example, in synchronization with the pulses 100, 101, 102,. The gate lines G1, G2, G3, G4,... Are sequentially driven to display a black level image.

  When generating the gate signal for driving the gate lines G1, G4, G7,..., The output enable signal OE1 bar is used to drive the gate lines G2, G5, G8,. When generating the gate signal, the output enable signal OE2 bar is used, and when generating the gate signal for driving the gate lines G3, G6, G9,..., The output enable signal OE3 bar is used. It is done.

Specifically, in the first half period (T ₁ ) of pulse 1 included in the clock signal CLK, a high-level gate signal for image display is supplied to the gate line G1 to turn on the TFT of the first line, Masking of the gate signal is performed using the output enable signal OE1 bar in order to supply a low level gate signal to the gate line G1 in the latter half period (T ₂ ) of the pulse 1 to turn off the TFT of the first line.

Further, a low-level gate signal is supplied to the gate line G1 in the first half cycle (T ₅ ) of the pulse 100 included in the clock signal CLK to turn off the first line TFT, and the second half cycle (T ₆ ) In order to supply a high level gate signal for black level display to the gate line G1 to turn on the TFT of the first line, masking of the gate signal is performed using the output enable signal OE1 bar.

  On the gate line G2, the gate signal is masked using the output enable signal OE2 bar, and on the gate line G3, the gate signal is masked using the output enable signal OE3 bar. In the gate line G4, the gate signal is masked again using the output enable signal OE1 bar.

  In this way, by masking the gate signals using the three systems of output enable signals OE1 to OE3, the three types of gate lines are repeatedly driven, so that the normal image and black level can be controlled within one frame period. An image is displayed. However, in the conventional display panel drive circuit, since three types of output enable signals are used, the circuit configuration becomes complicated, and fine adjustment of a period for displaying a normal image and a period for displaying a black level image is possible. It was difficult.

  As a related technique, Patent Document 1 below discloses a display device capable of suppressing deterioration in image quality caused by moving image blur and the like while suppressing an increase in size and complexity of the structure. According to this display device, image data and blanking data are displayed within one frame period by inserting blanking data into image data for one frame period. Can be suppressed. Furthermore, by selecting a line so that image data and blanking data are displayed on an arbitrary display element within one frame period, an increase in the number of drain drivers is suppressed, thereby increasing the size and complexity of the structure. Can be suppressed. However, in Patent Document 1, when a black level image is inserted, a normal image display period and a black level image display period are finely adjusted without complicating the circuit configuration of the gate driver. There is no disclosure regarding what is possible.

Patent Document 2 below can provide a high-resolution liquid crystal panel by designating a black data section for each frame and controlling the backlight unit by a data signal input to the black data section. A thin film transistor liquid crystal display device and a driving method thereof are disclosed. The liquid crystal display device includes an LCD panel having a plurality of gate lines provided in parallel to one direction and a plurality of data lines provided in parallel to each other at right angles to the direction of the gate lines. A gate driving unit for supplying a gate signal, a data driving unit for supplying a data signal to the LCD panel, a light guide plate, and at least two light sources provided on both sides of the light guide plate in the same plane as the light guide plate, And a backlight unit provided at the lower part of the LCD panel, and image blur can be improved by repeating on / off of at least two light sources at a predetermined time. However, Patent Document 2 does not disclose TFT control because a black level image is inserted by turning on / off the backlight.
JP 2003-36056 A (pages 1, 13 and 74) Japanese Patent Laying-Open No. 2003-228352 (first page, FIG. 5)

  Accordingly, in view of the above points, the present invention complicates the circuit configuration when inserting a black level image in a display panel driving circuit that drives the gates of a plurality of TFTs included in the display panel. It is an object to enable fine adjustment of a period for displaying a normal image and a period for displaying a black level image.

  In order to solve the above problems, a display panel driving circuit according to the present invention is a display panel driving circuit for driving a plurality of transistors arranged in a two-dimensional matrix in a display panel, and starts displaying an image. A first start pulse is applied to give a timing to perform the first shift, and the first start pulse is shifted in synchronization with the clock signal, thereby generating a plurality of signals for sequentially selecting lines to be driven in the display panel. A shift register and a second start pulse that gives the timing to start displaying the black level are applied, and the second start pulse is shifted in synchronization with the clock signal to sequentially select lines to be driven in the display panel. Generated by a second shift register that generates a plurality of signals to be generated and a first shift register. A plurality of signals for generating a timing for selectively activating transistors of each line arranged in the display panel based on the plurality of signals generated and the plurality of signals generated by the second shift register A plurality of level shift circuits for shifting the potentials of signals generated by the plurality of logic circuits, and signals output from the plurality of level shift circuits, and lines arranged on the display panel And a plurality of output circuits for outputting a plurality of drive signals for selectively activating the transistors.

  Here, each of the plurality of logic circuits generates a signal in which a period in which the plurality of output signals of the first shift register are activated is reduced according to the first control signal; In accordance with the control signal, a second logic circuit that generates a signal in which a period during which the plurality of output signals of the second shift register are activated, a signal generated by the first logic circuit, and a second logic A third logic circuit that generates a signal that represents a logical sum with a signal generated by the circuit may be included. Further, a liquid crystal display panel may be used as the display panel, and thin film transistors may be used as the plurality of transistors.

  According to the present invention, a first shift register that generates a plurality of signals for sequentially selecting lines driven in a display panel for displaying an image, and a line driven in the display panel for displaying a black level. By providing a second shift register that generates a plurality of signals for sequentially selecting signals, a normal image display period and a black level image display period can be finely adjusted without complicating the circuit configuration. Is possible.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In the following embodiments, an LCD panel is used as the display panel.
FIG. 1 shows a connection relationship between a display panel driving circuit and an LCD panel according to an embodiment of the present invention. In the LCD panel 100, for example, 3072 × 768 TFTs are arranged in a two-dimensional matrix corresponding to 1024 × 768 dots. Here, three dots for RGB correspond to one dot.

  In order to drive the LCD panel 100, one or more display panel driving circuits (source drivers) 200 for driving the sources of these TFTs are connected to the source lines S1 to S3072, and drive the gates of these TFTs. One or a plurality of display panel driving circuits (gate drivers) 300 are connected to the gate lines G1 to G768. In this embodiment, the source of 3072 TFTs is driven using eight source drivers having 384 outputs, and the gates of 768 TFTs are driven using three gate drivers having 256 outputs. It shall be. Further, a timing controller 400 that controls operation timings of the eight source drivers 200 and the three gate drivers 300 is connected to the source driver 200 and the gate driver 300.

  In the source driver 200, the main components include an image data adding circuit, a control circuit, a power supply circuit, a DAC (Digital to Analog Converter), an operational amplifier, an input terminal, an output terminal, and a gate. An output terminal to the driver is arranged.

  The source driver 200 analogizes the image data addition circuit for adding image data representing a black level image for each frame of image data, and the RGB three types of image data for each line sequentially output from the image data addition circuit. A plurality of DACs for converting the image signals to the image signals, a plurality of operational amplifiers for amplifying the image signals output from the DACs, and an image data adding circuit to control the black level on the LCD panel for each frame period. And a control circuit for displaying an image.

  As shown in FIG. 2, the gate driver 300 includes, as main components, a shift register 311 for displaying an image, a shift register 312 for displaying a black level, a logic circuit 316, a level shift circuit 320, and an output. A circuit 330, an input terminal, and an output terminal are arranged.

  The gate driver 300 sets the line of the LCD panel 100 corresponding to the image signal supplied from the source driver 200 to the LCD panel 100 according to the clock signal and control signal (start pulse signal and output enable signal) supplied from the source driver 200. The gate signals are sequentially selected, and a high level gate signal is supplied to the selected one of the gate lines G1, G2,. Among a plurality of TFTs connected to one source line, a TFT whose gate line is at a high level is turned on, and an image signal is supplied to a liquid crystal electrode connected to the TFT. In this way, an image is displayed on the LCD panel 100 while inserting a black level image for each frame period.

  FIG. 3 shows a configuration example of the two types of shift registers and logic circuits shown in FIG. FIG. 3 shows an image display shift register 311, a black level display shift register 312, and a plurality of logic circuits 316 including AND circuits 313 and 314 and an OR circuit 315.

  The image display shift register 311 is applied with a start pulse signal SP1 including a first start pulse that gives a timing to start displaying an image, and shifts the first start pulse in synchronization with the clock signal CLK. A plurality of signals for sequentially selecting lines to be driven in the LCD panel 100 are generated.

  The black level display shift register 312 is applied with a start pulse signal SP2 including a second start pulse that gives timing for starting display of a black level, and shifts the second start pulse in synchronization with the clock signal CLK. Thus, a plurality of signals for sequentially selecting lines to be driven in the LCD panel 100 are generated.

  The plurality of logic circuits 316 are provided for each line arranged in the LCD panel 100 based on the plurality of signals generated by the image display shift register 311 and the plurality of signals generated by the black level display shift register 312. A plurality of signals that provide timing for selectively activating the transistors are generated.

  Specifically, in each logic circuit 316, the AND circuit 313 reduces the period in which the plurality of output signals of the image display shift register 311 are activated in accordance with the positive logic first output enable signal OE1. The AND circuit 314 generates a signal obtained by reducing the period in which the plurality of output signals of the black level display shift register 312 are activated in accordance with the positive logic second output enable signal OE2.

  Further, the OR circuit 315 generates a signal representing the logical sum of the signal generated by the AND circuit 313 and the signal generated by the AND circuit 314. As the second output enable signal OE2, a signal obtained by inverting the first output enable signal OE1 can be used.

  Conventionally, a display panel driving circuit (gate driver) for driving the gate of a TFT uses a shift register and three output enable signals in order to reduce image blur and afterimage in an LCD panel. In order to display an image and a black level image, a timing for activating the gate signal is generated.

  However, when generating the timing for activating the gate signal based on the three output enable signals, the circuit configuration becomes complicated, and a period for displaying a normal image and a period for displaying a black level image are displayed. Fine adjustment was difficult. According to the present invention, two types of shift registers 311 and 312 and two types of output enable signals are used to generate a timing for activating a gate signal in order to display a normal image and a black level image. The period for displaying a normal image and the period for displaying a black level image can be finely adjusted without complicating the circuit configuration.

FIG. 4 shows a configuration example of the level shift circuit and the output circuit shown in FIG. The logic portion of the display panel driving circuit operates by being supplied with a power supply potential LV _DD of about 3.3 volts and a power supply potential LV _{SS of} 0 volts (ground potential). Meanwhile, TFT incorporated in the LCD panel, for example, 35 since volt power supply potential _{HV DD} and minus 10 volt supply potential _{HV SS} operates is supplied, the power supply logic signals the power potential _LV DD _{~LV SS} It is necessary to convert the drive signal to a potential HV _{DD to} HV _SS . Since the driving voltage of the TFT is different for each LCD panel, it is necessary to set HV _DD and HV _SS according to the specifications of the LCD panel to be used.

  In level shift circuit 320, the first level shift circuit is composed of P channel MOS transistors QP1 and QP2 and N channel MOS transistors QN1 and QN2, and the second level shift circuit is P channel MOS transistor QP3. QP4 and N channel MOS transistors QN3 and QN4.

A signal generated by each logic circuit 316 shown in FIG. 3 is input to the gate of the transistor QP1 and the inverter INV1. The inverter INV1 inverts the input signal and outputs it to the gate of the transistor QP2. In this way, the first level shift circuit receives a signal that transitions between the power supply potential LV _DD and the power supply potential LV _SS, and transitions between the power supply potential LV _DD and the power supply potential HV _SS. Generate a signal. Further, the second-stage level shift circuit receives the signal generated by the first-stage level shift circuit and generates a signal that transitions between the power supply potential HV _DD and the power supply potential HV _SS .

FIG. 5 shows signal potentials in the level shift circuit shown in FIG. The level shift circuit of the first stage is supplied with the power supply potential LV _DD and the power supply potential HV _SS, and changes the low level of the signal (a) that changes between the power supply potential LV _DD and the power supply potential LV _SS to the power supply potential HV. Shift to _SS to generate the signal (b). Further, the second level shift circuit shifts the high level of the signal (b) to the power supply potential HV _DD to generate the signal (c).

Referring to FIG. 4 again, the signals (shown in (c) of FIG. 5) output from the respective level shift circuits 320 are input to the respective output circuits 330. Each output circuit 330 includes a first inverter composed of a P-channel MOS transistor QP5 and an N-channel MOS transistor QN5 connected in series between a power supply potential HV _DD and a power supply potential HV _SS , and a power supply potential HV _DD. And a second inverter constituted by a P-channel MOS transistor QP6 and an N-channel MOS transistor QN6 connected in series between the power supply potential HV _SS and the transistors of each line arranged in the display panel A drive signal for selectively activating is output.

FIG. 6 shows signal waveforms in the display panel drive circuit according to the embodiment of the present invention.
The clock signal CLK and the start pulse signal SP1 illustrated in FIG. 6 are input to the shift register 311 illustrated in FIG. 3, and the clock signal CLK and the start pulse signal SP2 illustrated in FIG. 6 are input to the shift register 312 illustrated in FIG. Is done. When the start pulse included in the start pulse signals SP1 and SP2 is applied, the shift registers 311 and 312 shift the start pulse in synchronization with the clock signal CLK to thereby change the line driven in the LCD panel 100. A plurality of signals to be sequentially selected are generated.

Referring to FIG. 6, a high-level gate signal for image display is supplied to the gate line G1 in the first half period (T ₁ ) of the pulse 1 included in the clock signal CLK to turn on the TFT of the first line. The gate signal is masked using the output enable signal OE1 in order to supply a low level gate signal to the gate line G1 in the _second half period (T ₂ ) of the pulse 1 to turn off the TFT of the first line.

Further, a low-level gate signal is supplied to the gate line G1 in the first half period (T ₅ ) of the pulse 101 included in the clock signal CLK to turn off the first line TFT, and the second half period (T ₆ ) In order to supply a high level gate signal for black level display to the gate line G1 to turn on the TFT of the first line, masking of the gate signal is performed using the output enable signal OE2.

  The same applies to the other gate lines G2, G101, and G102. The period during which the image display gate signal is activated is defined by the output enable signal OE1, and the period during which the black level display gate signal is activated. It is defined by the output enable signal OE2. Such an operation is performed for all gate lines (here, gate lines G1 to G132). The period for displaying a normal image and the period for displaying a black level image can be arbitrarily set based on the display performance of the LCD panel.

The figure which shows the connection relation of the display panel drive circuit which concerns on one Embodiment of this invention. The figure which shows the component of the gate driver shown in FIG. FIG. 3 is a diagram illustrating a configuration example of two types of shift registers and logic circuits illustrated in FIG. 2. FIG. 3 is a diagram illustrating a configuration example of a level shift circuit and an output circuit illustrated in FIG. 2. FIG. 5 shows signal potentials in the level shift circuit shown in FIG. 4. The figure which shows the waveform of the signal in the display panel drive circuit which concerns on one Embodiment of this invention. The figure which shows the waveform of the signal in the conventional display panel drive circuit.

Explanation of symbols

  100 LCD panel, 200 source driver, 300 gate driver, 311, 312 shift register, 313, 314 AND circuit, 315 OR circuit, 320 level shift circuit, 330 output circuit, 400 timing controller, S1 to S3072 source line, G1 to G768 Gate line, QP1 to QP6 P channel transistor, QN1 to QN6 N channel transistor, INV1 inverter

Claims (3)

A display panel driving circuit for driving a plurality of transistors arranged in a two-dimensional matrix in a display panel,
A first start pulse that gives a timing for starting image display is applied, and the first start pulse is shifted in synchronization with the clock signal, whereby a plurality of signals for sequentially selecting lines to be driven in the display panel are displayed. A first shift register to be generated;
A plurality of signals for sequentially selecting lines to be driven in the display panel by applying a second start pulse for giving a timing for starting display of a black level and shifting the second start pulse in synchronization with the clock signal. A second shift register for generating
Based on the plurality of signals generated by the first shift register and the plurality of signals generated by the second shift register, the transistors in each line arranged in the display panel are selectively activated. A plurality of logic circuits for generating a plurality of signals for providing timing;
A plurality of level shift circuits for respectively shifting potentials of signals generated by the plurality of logic circuits;
A plurality of output circuits that input signals output from the plurality of level shift circuits and respectively output a plurality of drive signals for selectively activating transistors of each line arranged in the display panel;
A display panel driving circuit comprising: Each of the plurality of logic circuits is
A first logic circuit for generating a signal in which a period in which the plurality of output signals of the first shift register are activated is reduced according to a first control signal;
A second logic circuit for generating a signal obtained by reducing a period during which a plurality of output signals of the second shift register are activated in accordance with a second control signal;
A third logic circuit for generating a signal representing a logical sum of a signal generated by the first logic circuit and a signal generated by the second logic circuit;
The display panel driving circuit according to claim 1, comprising:   The display panel drive circuit according to claim 1, wherein the display panel is a liquid crystal display panel, and the plurality of transistors are thin film transistors.

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