JP2006303268A5 - - Google Patents
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- Publication number
- JP2006303268A5 JP2006303268A5 JP2005124529A JP2005124529A JP2006303268A5 JP 2006303268 A5 JP2006303268 A5 JP 2006303268A5 JP 2005124529 A JP2005124529 A JP 2005124529A JP 2005124529 A JP2005124529 A JP 2005124529A JP 2006303268 A5 JP2006303268 A5 JP 2006303268A5
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- resist material
- semiconductor chip
- holes
- core material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 17
- 239000000463 material Substances 0.000 claims 10
- 229910000679 solder Inorganic materials 0.000 claims 10
- 239000011162 core material Substances 0.000 claims 7
- 239000000758 substrate Substances 0.000 claims 6
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
Claims (6)
平面形状が四角形から成り、複数の電極が形成された主面を有し、前記コア材の前記表面上に形成された前記ソルダレジスト材上に、ペースト材を介して接着された半導体チップと、
前記半導体チップの前記複数の電極と前記基板の前記複数のボンディング電極とをそれぞれ電気的に接続する複数のボンディングワイヤと、
前記半導体チップ及び前記複数のボンディングワイヤを封止するように、前記基板の前記主面上に形成された封止樹脂と、
前記複数のランドにそれぞれ接続された複数のはんだボールと、
を含み、
前記複数のボンディング電極は、前記半導体チップの各辺に沿うように、前記基板の前記表面に形成されており、
前記複数のスルーホールは、前記半導体チップの各辺に沿うように、前記半導体チップと前記基板の前記複数のボンディング電極との間に形成されており、
前記ソルダレジスト材には、前記コア材の前記表面を露出する凹部が複数形成されており、
前記複数の凹部は、前記半導体チップの各辺に沿うように、前記半導体チップと前記基板の前記複数のボンディング電極との間で、かつ前記複数のスルーホールのうちの隣接するスルーホール間に形成されていることを特徴とする半導体装置。 A core material, a plurality of bonding electrodes formed on the surface of the core material, a solder resist material formed on the surface of the core material so as to expose each of the plurality of bonding electrodes, and the core material A plurality of lands formed on the back surface opposite to the front surface, and a substrate having a plurality of through holes which are wiring paths for electrically connecting the plurality of bonding electrodes and the plurality of lands, respectively.
A semiconductor chip having a main surface on which a planar shape is formed of a quadrangle and on which a plurality of electrodes are formed, and is bonded to the solder resist material formed on the surface of the core material via a paste material;
A plurality of bonding wires electrically connecting the plurality of electrodes of the semiconductor chip and the plurality of bonding electrodes of the substrate;
A sealing resin formed on the main surface of the substrate so as to seal the semiconductor chip and the plurality of bonding wires;
A plurality of solder balls respectively connected to the plurality of lands;
Including
The plurality of bonding electrodes are formed on the surface of the substrate along each side of the semiconductor chip,
The plurality of through holes are formed between the semiconductor chip and the plurality of bonding electrodes of the substrate along each side of the semiconductor chip,
The solder resist material is formed with a plurality of recesses exposing the surface of the core material,
The plurality of recesses are formed between the semiconductor chip and the plurality of bonding electrodes of the substrate and between adjacent through holes among the plurality of through holes so as to be along each side of the semiconductor chip. A semiconductor device which is characterized by being made.
前記複数の凹部は、前記複数のスルーホールのそれぞれと平面的に重ならないように、前記ソルダレジスト材に形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
Wherein the plurality of recesses, so as not to overlap to each in a plane of said plurality of through holes, the semiconductor equipment characterized that you have formed in the solder resist material.
前記複数のスルーホールのそれぞれは、前記ソルダレジスト材で覆われていることを特徴とする半導体装置。 The semiconductor device according to claim 2,
Wherein each of the plurality of through holes, the semiconductor equipment characterized that you have been covered with the solder resist material.
前記複数のスルーホールのそれぞれを覆う前記ソルダレジスト材の一部は、盛り上がっていることを特徴とする半導体装置。 The semiconductor device according to claim 3.
The portion of the respective cover of the plurality of through holes solder resist material, it has raised a semiconductor equipment according to claim Rukoto.
前記凹部の平面形状は矩形状から成り、
前記凹部のうちの前記スルーホール側に位置する端辺は、盛り上がるように形成された前記ソルダレジスト材のすそ野部に接するように、前記ソルダレジスト材に形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 4.
The planar shape of the recess is a rectangular shape,
An end of the recess located on the through-hole side is formed in the solder resist material so as to be in contact with a bottom portion of the solder resist material formed so as to rise. Place.
前記コア材の前記裏面上には、前記複数のランドのそれぞれを露出するように、ソルダレジスト材が形成されていることを特徴とする半導体装置。A solder resist material is formed on the back surface of the core material so as to expose each of the plurality of lands.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005124529A JP4615360B2 (en) | 2005-04-22 | 2005-04-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005124529A JP4615360B2 (en) | 2005-04-22 | 2005-04-22 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010197003A Division JP5271982B2 (en) | 2010-09-02 | 2010-09-02 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006303268A JP2006303268A (en) | 2006-11-02 |
| JP2006303268A5 true JP2006303268A5 (en) | 2008-05-29 |
| JP4615360B2 JP4615360B2 (en) | 2011-01-19 |
Family
ID=37471187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005124529A Expired - Fee Related JP4615360B2 (en) | 2005-04-22 | 2005-04-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4615360B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4362165B2 (en) * | 1999-05-28 | 2009-11-11 | イビデン株式会社 | Electronic component mounting device |
| JP4308608B2 (en) * | 2003-08-28 | 2009-08-05 | 株式会社ルネサステクノロジ | Semiconductor device |
-
2005
- 2005-04-22 JP JP2005124529A patent/JP4615360B2/en not_active Expired - Fee Related
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