JP2006297502A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has good conformity with an LSI process when MEMS devices and CMOS LSIs are mixedly mounted on the same substrate, and which can suppress the effects of moisture, heat, etc. generated from LSI regions on the MEMS devices. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate (500) having a first region and a second region neighboring the first region, an integrated circuit (401) to be formed in the second region, a supporting column structure (414) which is formed on the boundary between the first region and the second region so as to have a wall shape and so as to electrically and spatially separate the first region and the second region, thin film structures (419, 427) which are supported by the supporting column structure and are laminated so as to cover the first region and the second region, and an element (424) which comprises a mechanical movable portion to be arranged in a space to be formed on the lower portion of the thin film structure existing in the first region, and which is electrically connected to the integrated circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element having a hollow structure and an integrated circuit are mixedly mounted on the same semiconductor substrate.

  In recent years, research and development of devices having a hollow structure formed on a semiconductor substrate and having mechanically movable parts, so-called MEMS (Mechanical Electrical Micro System), have been actively conducted. However, in these devices, it is necessary to hold a hollow structure that can be moved mechanically, and packaging technology such as resin molding that has been used in conventional LSI cannot be diverted, and a special package is required. It is said. At the same time, when atmospheric moisture adheres to the surface of the hollow structure, surface tension is generated between the substrate and the hollow structure, and a phenomenon called sticking occurs in which the hollow structure adheres to the substrate. Since this sticking impedes mechanical driving, it is necessary to maintain the inside of the package in a vacuum or an inert gas atmosphere.

  As a specific example of such a hollow structure, an uncooled infrared solid-state imaging device will be described below.

  The uncooled infrared solid-state image sensor converts incident infrared light into heat at the infrared absorption part, and converts the temperature change of the heat sensitive part caused by the weak heat into an electrical signal by the thermoelectric conversion part. The infrared image information is obtained by reading out. That is, in the above infrared solid-state imaging device, the infrared detection unit composed of a thermosensitive unit (infrared absorbing structure) that converts incident infrared rays into heat and a thermoelectric conversion unit that converts the heat into electrical signals is thermally separated from the surroundings. In order to improve the infrared sensitivity, it is essential to improve the thermoelectric conversion efficiency.

  Therefore, the infrared solid-state imaging device is formed into a cavity by etching and removing the silicon substrate and the element isolation oxide film around the infrared detection unit, and is mounted on a vacuum package to make the cavity part in a vacuum state. The method of suppressing the diffusion of heat is taken.

On the other hand, in the prior art described in Patent Document 1, a means for directly bonding an infrared transmitting window to a detection chip and hermetically sealing is proposed. In Patent Document 1, an infrared transmission window made of silicon is disposed on the front surface of an infrared detection array formed on a silicon substrate by polishing both surfaces and applying an antireflection film. The infrared transmission window and the infrared detection array are arranged through a gap, and the transmission window is hermetically bonded and fixed on the silicon substrate so as to surround the infrared detection array, and the inside of the gap is held in a vacuum. ing. The gap between the infrared detection array and the infrared transmission window is formed by using a convex step formed by a metallized layer formed on the bonding surface on the silicon substrate and a solder layer as bonding means. In addition, the vacuum sealing of the gap is realized by soldering the silicon substrate and the infrared transmission window so as to maintain a vacuum state of 1 × 10 ⁻² torr or less. In addition, a microlens array that is paired with each pixel of the infrared detection array is formed in the infrared transmission window, and infrared rays that are incident on the detector are condensed on the corresponding pixel by the microlens array.
JP-A-10-115556

  As described above, when a conventional CMOS integrated circuit and a device having a hollow structure such as the infrared solid-state imaging device are formed on the same substrate, an inexpensive resin mold or the like conventionally used for mounting an integrated circuit is used. Packaging technology cannot be diverted and a special vacuum package is required. Accordingly, there is a problem that the mounting area of the chip is increased and the cost is increased because the chip has a special sealing structure.

  In addition, while it is sufficient that the MEMS device has only 3 to 4 layers, the current CMOS LSI has 6 to 10 wiring layers, and the wiring layer difference between the MEMS device and the CMOS LSI is very large. However, it is an obstacle to be mixed on the same substrate.

  Further, a sacrificial layer process for forming a hollow structure is required for a MEMS device, whereas such a layer structure does not exist in a CMOS LSI.

  Further, in the MEMS device, when moisture in the atmosphere adheres to the surface of the hollow structure, surface tension is generated between the substrate and the hollow structure, and a mechanical phenomenon is caused by a phenomenon called sticking in which the hollow structure adheres to the substrate. In order to hinder driving, the inside of the package must be maintained in a vacuum or an inert gas atmosphere. At this time, in the mixed mounting with the LSI, it is necessary to enclose moisture adsorbed on the film constituting the LSI so as not to reattach to the surface of the MEMS hollow structure.

  Further, in recent LSIs, heat generation due to Joule heat due to current consumption is large, and there is a concern about adverse effects on MEMS devices.

  As described above, the object of the present invention is to have a good consistency with the LSI process in that the MEMS device is mounted on the same substrate as the CMOS LSI, and to suppress the influence on the MEMS device such as moisture and heat generated from the LSI region. It is an object of the present invention to provide a semiconductor device that can be used.

According to this invention,
A semiconductor substrate having a first region and a second region adjacent to the first region;
An integrated circuit formed in the second region;
A pillar structure that is formed in a wall shape at the boundary between the first region and the second region, and that electrically and spatially separates the first and second regions;
A thin film structure that is supported by the support structure and is laminated so as to cover the first and second regions;
An element electrically connected to the integrated circuit, comprising a mechanically movable portion disposed in a space formed in the lower portion of the thin film structure in the first region;
A semiconductor device is provided.

Moreover, according to this invention,
Element wiring for an element having a mechanical movable part to be formed in a space on a semiconductor substrate, an integrated circuit for processing a signal from the element, and a connection wiring for connecting the element and the integrated circuit Form the
A low hygroscopic interlayer film is formed on the element wiring, the integrated circuit, and the connection wiring,
Depositing a sacrificial film on the interlayer film;
An integrated circuit in which a wiring layer and a contact are formed in the sacrificial film so as to be connected to the element wiring and the integrated circuit, and the element is formed, and an element region in which the element is formed and the integrated circuit is formed. Form a wall-shaped support wiring at the boundary with the area,
Deposit a passivation film,
Forming a first opening in the passivation film above the element region;
Removing the sacrificial film from the first opening to form a first space therein, and disposing the movable portion of the element in the space;
A method of manufacturing a semiconductor device is provided, wherein a thin film is deposited and the opening is sealed by lateral film growth.

  In the point that the MEMS device is mixedly mounted on the same substrate as the CMOS LSI, it is compatible with the LSI process, and the influence of moisture, heat, etc. generated from the LSI region on the MEMS device can be suppressed.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.

[First embodiment]
1, 4, 7, 10, 13, 16, 19, and 21 illustrate a manufacturing process of a semiconductor device having an element sealing structure in the MEMS region according to the first embodiment of the present invention. This is schematically shown in cross-sectional view. 2, 5, 8, 11, 14, 17, 20, and 22 are respectively illustrated in FIGS. 1, 4, 7, 10, 13, 16, 19, and 19. FIG. 22 is a plan view of the semiconductor device shown in FIG.

  In this embodiment, an uncooled infrared sensor is cited as an example of a MEMS device. However, the present invention is not limited to this, and can be applied to other MEMS devices that require a similar hollow structure. .

  3, 6, 9, 12, 15, 18, and 23 are shown in FIGS. 1, 4, 7, 10, 13, 16, 19, and 21. The structure of each semiconductor device in an LSI (Large Scale Integrated circuit) region mixedly mounted on the same semiconductor chip is shown. The LSI can be formed on the same chip as long as it is another device having three or more wiring layers, such as a logic circuit for analyzing output data or a memory for holding output data. Of course, a single MEMS device can be formed on the same chip.

  In FIGS. 1 to 23, it should be noted that the same portions or the same elements are denoted by the same reference numerals and description thereof is omitted, and only different configurations or portions are denoted by other reference numerals.

  In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 1, a buried silicon oxide film layer 101 and a single crystal silicon layer 102 are sequentially stacked on a single crystal silicon support substrate 100 as a semiconductor substrate. So-called SOI substrates are used.

  As shown in FIGS. 1 and 2, in the MEMS region 99, an infrared sensor pixel 103 as a semiconductor element is formed in the element region using a normal semiconductor process, and a support wiring 104 serving as an input / output wiring of the infrared sensor pixel 103. , 105, a horizontal wiring 106 for selecting the infrared sensor pixel 103 and supplying a bias voltage, and a vertical wiring 107 for reading out an output signal from the infrared sensor pixel 103 are formed in the wiring region. The infrared sensor pixel 103 includes a plurality of pn junction diodes 108 formed in the single crystal silicon layer 102, an intra-pixel wiring 109 connecting them, a silicon oxide film, and an infrared absorption film 110 made of a silicon nitride film. Here, a groove 111 reaching the surface of the single crystal silicon support substrate 100 is selectively formed in the MEMS region 99 by a dry process.

  In the LSI region 301 shown in FIG. 3, a gate electrode 302, diffusion layers 303 and 304, a first interlayer film 305, a contact 306, a first-layer wiring 106 (formed in common with the horizontal wiring), a second interlayer film 307, a two-layer wiring 107 (formed in common with the vertical wiring), and a third interlayer film 110 (infrared absorbing film) are formed. When the groove 111 shown in FIG. 1 is formed, the LSI region 301 shown in FIG. 3 is protected by a resist mask.

  Next, as shown in FIGS. 4 and 5, the support legs and the wiring area other than the infrared sensor pixel 103 and the LSI area 301 are etched back by a dry process. Thereafter, the first sacrificial film 112 is formed, and then the second sacrificial film 113 is formed. The first and second sacrificial films 112 and 113 are formed, for example, by applying a film obtained by adding several percent of Si to a cycloxan-based organic film using a spin coater and performing a dry baking process. The etching back amount, the thickness of the first and second sacrificial films 112 and 113, and the dry baking conditions define the curvature of the thin film structure 125 (FIG. 21) to be formed later. In the first embodiment, for an infrared sensor pixel of 20 μm, the etch back amount is 2 μm, the thicknesses of the first and second sacrificial films 112 and 113 are 1.5 μm, and the baking temperature is 350 ° C.

  The first and second sacrificial films 112 and 113 may be any material that has etching selectivity in both the device passivation film and the microlens sealing structure. However, the parasitic capacitance between the CMOS LSI wiring layers can be reduced. In view of this, a low-k film having a so-called relative dielectric constant of less than 3.3 is desirable. For example, SiOC, methyl group-containing polysiloxane-based SiO2 (MSQ), polyimide, parylene-based organic film, hydrogen-containing polysiloxane-based SiO2 (HSQ ), And films in which pores are introduced into these films are desirable. Further, the film forming method is not limited to spin coating (coating method), and CVD may be used.

  As shown in FIG. 6, in the LSI region 301, a three-layer wiring 308 is formed on the third interlayer film 110. Here, as a more desirable form, a wiring protective film is formed around the three-layer wiring 308. Specifically, when the three-layer wiring 308 is formed, a barrier metal, for example, Ti, TiN, or a laminated structure thereof is formed as the layer structure on the top and bottom. Thereafter, the three-layer wiring 308 is patterned by photolithography, and a barrier metal is formed again by sputtering or the like. Thereafter, the barrier metal is etched back to form a barrier metal on the side wall of the third layer wiring. Next, a first sacrificial film 112 is formed. Thereafter, a three-layer / four-layer contact 309 is formed, but here again more desirably, barrier metal is formed on the periphery and the bottom in order to prevent oxidation of the contact metal. Thereafter, a four-layer wiring 310 is formed, and a second sacrificial film 113 is formed. For the four-layer wiring 310, a barrier metal is formed in the same manner as the three-layer wiring 309.

  Next, as shown in FIGS. 7 and 8, an etching protective film 114 of the sacrificial film 113, for example, an SiO 2 film is deposited on the sacrificial film 113 to a thickness of 0.1 μm by a CVD method, and a resist 115 is applied. The Thereafter, in the MEMS region 99, first openings 116 are formed on every other (even or odd number) horizontal wiring 106 and vertical wiring 107 by lithography.

  Further, as shown in FIG. 9, in the LSI region 301, the etching protection film 114 is removed by etching in a part of the upper region of the four-layer wiring 310 by fluorine-based dry etching.

  Next, as shown in FIGS. 10 to 12, the first and second sacrificial films 112 and 113 are etched away by O 2 RIE. At this time, since the total of the first and second sacrificial films 112 and 113 is as thick as 3 μm, the resist 115 shown in FIG. 9 is removed at this point.

  Next, as shown in FIGS. 13 to 15, the etching protection film 114 is etched back by fluorine-based dry etching. Thereafter, a first thin SiO 2 film 117 is formed, a first thin film 118 is formed on the SiO 2 film 117, and a second thin SiO 2 film 119 is formed on the first thin film 118. Be filmed. For example, in the present embodiment, the first thin SiO 2 film 117 is deposited with a thickness of 20 nm by a CVD method, and the first thin film 118 is an amorphous silicon film with a thickness of 0.1 μm by a 350 ° CVD method. The second thin SiO2 film 119 is deposited with a thickness of 20 nm by a CVD method. The material of the first thin film 118 is not limited to amorphous silicon in this patent, but is a material that transmits an infrared wavelength region, such as silicon, copper chloride, germanium, lead selenide, zinc sulfide, or cadmium sulfide. What is necessary is just to be comprised from the film | membrane containing this.

  The first thin film 118 needs to be formed with the second openings 121 and 316, and a thick film is not preferable from the viewpoint of the selection ratio with respect to the resist 120 serving as a mask and the etching aspect ratio. More preferably, it is 1 μm or less. Thereafter, after the resist 120 is applied, a second opening pattern 121 is formed in the MEMS region 99 in the region on the horizontal wiring 106 and the vertical wiring 107 where the first opening 116 is not formed by lithography. The

  In the LSI region 301, the second opening pattern 316 is formed in a region other than the first opening pattern 315. Thereafter, the first thin SiO 2 film 117 is removed by fluorine-based dry etching, the first thin film 118 is removed by CF-based dry etching, and the second thin SiO 2 film is removed by fluorine-based dry etching. 119 is removed.

  Next, as shown in FIGS. 16 to 18, the first and second sacrificial films 112 and 113 and the resist 120 are removed by O 2 isotropic dry etching, for example, O 2 plasma asher. After removal, a void 124 is formed. Here, in the present embodiment, a device that places importance on high-speed operability as an LSI is mixedly mounted in the LSI region 301, and the first and second sacrificial films 112 and 113 that become wiring interlayer films are removed to reduce wiring capacitance. The three-layer and four-layer wirings 308 and 310 are formed as aerial wirings extending in the space. However, in a device in which reliability is more important, the first and second sacrificial films 112 and 113 in the LSI region 301 are formed. It is better to leave without removing. In this case, the second opening pattern 316 in the LSI region 301 shown in FIG.

  In addition, the first openings 116 and 315 and the second openings are obtained from the strength required for the thin film structure 125 including the first thin film 118 and the second thin film 123 and the removability of the first and second sacrificial films 112 and 113. The patterns of the openings 121 and 316 are determined, and the optimum pattern varies depending on the cell size of the MEMS device, the wiring pitch of the LSI, and the like, and is not limited to the pattern shown in the drawing according to the present embodiment.

Next, as shown in FIGS. 19 and 20, a hollow structure 122 is formed inside the single crystal silicon support substrate 100 by anisotropic silicon wet etching using TMAH (Tetra-Methyl-Ammonium-Hydroxide). At this time, since the three-layer and four-layer wirings 308 and 310 existing in the LSI region 301 are respectively covered by the three-layer and four-layer passivation films 311 and 314 having a laminated structure, etch pits generated in the wiring step portions. This is effective for suppression and can prevent etching of the wiring by TMAH. Thereafter, the first and second thin SiO ₂ films 117 and 119 are removed by fluorine-based isotropic etching.

  Next, as shown in FIGS. 21 to 23, a thick second thin film 123 is formed. For example, the second thin film 123 is formed by depositing an amorphous silicon film with a thickness of 3 μm by a CVD method of 350 degrees. At this time, by setting the width of the second opening patterns 121 and 316 to be equal to or less than the film thickness of the second thin film 123, the second opening patterns 121 and 316 are formed by the CVD lateral growth of the second thin film 123. Since they are closed, the voids 124 and 317 formed on the hollow structure 122 and the infrared sensor pixel 103 and on the LSI region 301 are maintained at the degree of vacuum during the CVD process, and the thin film structure 125 is formed.

  According to the manufacturing method as described above, infrared sensor pixels 103 as semiconductor elements are two-dimensionally arranged and formed on a semiconductor substrate 100 (single crystal silicon support substrate 100) as shown in FIGS. . Each infrared sensor pixel 103 is formed in an element region on the semiconductor substrate 100, a horizontal wiring 106 for selecting the infrared sensor pixel 103, support wirings 104 and 105 for reading signals from the infrared sensor pixel 103, a vertical wiring 107, These wirings (support wirings 104 and 105, horizontal wiring 106, and vertical wiring 107) are arranged in a wiring region around the element region. The remaining infrared absorption film 110 covers the support wirings 104 and 105, the horizontal wiring 106 and the vertical wiring 107 as a passivation film, and the support wirings 104 and 105 are extended to support the infrared sensor pixel 103, and the infrared rays The sensor pixel 103 is held in the space in a suspended state by the support wirings 104 and 105. The thin film structure 125 covers the gap 124 from at least a part of the wiring region (for example, the upper part of the infrared absorption film 110 of the vertical wiring 107 as shown in FIG. 21), and the infrared sensor pixel 103 is airtight from the outside space. It constitutes the structure to be isolated.

  Further, as shown in FIG. 21, the thin film structure 125 includes a first thin film 118 having an opening 121 that communicates with the gap 124, and a second thin film 123 that closes the opening 121. As described above, the first thin film 118 is thinner than the second thin film 123, and the width of the opening 121 is twice the thickness of the second thin film 123. It is formed as defined below. The gap 124 is filled with a vacuum state or an inert gas.

  In the semiconductor device having such a structure, the thin film structure 125 can focus the detection light on the infrared sensor pixel 103 as a light detection element and improve the sensitivity. The infrared sensor pixel 103 includes an infrared absorption film 110 that absorbs incident infrared rays and converts the infrared rays into heat, and a thermoelectric conversion unit 108 (pn junction diode 108) that converts a temperature change caused by the heat generated in the infrared absorption film 110 into an electric signal. Since it is comprised, it becomes possible to convert infrared rays into an electric signal efficiently.

  In this embodiment, a normal CVD process is used to form the second thin film 123. In this case, since the carrier gas such as N 2 and Ar remains in the gap 124, the heat insulation of the infrared sensor pixel 103 is slightly worse. Thus, the sensitivity of the infrared sensor is reduced. Therefore, the residual gas (inert gas) pressure in the gap 124 is reduced by using ECR sputtering in which the plasma generating part where the CVD process gas exists and the film forming part are separated in forming the second thin film 123. It can suppress that an infrared sensor sensitivity falls.

  In addition, as shown in FIG. 21, the thin film structure 125 defined by the etch back amount of the region other than the infrared sensor pixel 103 and the LSI region 301, the thicknesses of the first and second sacrificial films 112 and 113, and the dry baking conditions is provided. By giving an appropriate curvature, the infrared rays incident on the insensitive area around the infrared sensor pixel 103 can be condensed on the infrared sensor pixel 103 and the sensitivity can be improved. Therefore, the element sealing structure of the semiconductor device has high mass productivity, high reliability, and high yield, and can reduce the cost.

[Second Embodiment]
24 to 33, the MEMS device according to the second embodiment of the present invention and the LSI are formed on the same substrate, and a region isolation structure for separating both the device regions from heat and moisture diffusion is formed. The manufacturing process of the semiconductor device which has an element sealing structure on a device is shown roughly with sectional drawing.

  First, as shown in FIG. 24, a MEMS region 400 (first region) and an LSI region 401 (second region) are defined on a semiconductor substrate 500, and a trench groove is formed in a region corresponding to an isolation portion. The trench groove is filled with an insulating film to form an element isolation part 402 between MEMS devices, an element constituting an LSI, for example, an element isolation part 403 between transistors and an area isolation part 404 between the MEMS region and the LSI region. . Depending on the types of elements and MEMS devices constituting the LSI and the requirements for electrical and thermal isolation between them, the depth of the trench groove may be different. In the present embodiment, the separation portion of the LSI region and the MEMS region is normally formed simultaneously as STI (Shallow Trench Isolation), and only the region separation portion is separately formed as DTI (Deep Trench Isolation).

  Next, as shown in FIG. 25, a transistor 405 is formed in the LSI region 401 by ordinary ion implantation, thermal diffusion, oxidation, CVD, and photolithography. In the MEMS region 400, a silicided polysilicon wiring 406 is formed in the same process. The wiring 406 is connected to the LSI region 401 and may be used as an input / output wiring for the MEMS region 400 and the LSI region 401. However, since the wiring 406 is usually high resistance, it is desirable to use it as an internal wiring in the MEMS region. Further, it is more preferable that the polysilicon electrode 406 be formed in the same process as the gate wiring of the transistor 405 because the number of processes can be reduced. Thereafter, a first interlayer film 407 is formed on the semiconductor substrate 500, and the first interlayer film 407 is planarized by CMP (Chemical Mechanical Polishing). As the material of the first interlayer film 407, it is preferable to use a film that is not particularly highly hygroscopic, such as SiO2, SiN, TEOS. That is, the first interlayer film 407 is formed of an insulating film containing Si as a main component and containing at least one of O, N, C, and H. Thereafter, contact holes are patterned by photolithography, an opening is formed in the first interlayer film 407 by RIE (Reactive Ion Etching), barrier metal TiN is sputtered, and tungsten is buried by CVD. Thereafter, the surface is flattened by CMP to form the first contact wiring 408.

  Next, as shown in FIG. 26, a first layer wiring 409 is formed, and a second interlayer film 410 is formed on the first layer wiring 409 and the first interlayer film 407. This one-layer wiring 409 is connected to the LSI region 401 and serves as an input / output wiring for the MEMS region 400 and the LSI region 401. The material of the second interlayer film 410 is the same as that of the first interlayer film 407.

  In FIGS. 24 to 26, AA ′ is appended, and this AA ′ is a cross section taken along the line AA ′ shown in FIG. 28 referred later. I mean.

  Next, as shown in FIG. 27, a first sacrificial layer film 411 is formed on the second interlayer film 410 by a coating method. The method for forming the sacrificial layer, the material, and the like are the same as in the first embodiment. Thereafter, a groove for forming the second contact wiring 412 and the two-layer wiring 413 is formed by photolithography and RIE, TaN is formed with a film thickness of about 20 nm as a barrier metal as an oxidation barrier, and then plated. As a seed layer, Cu is formed by sputtering with a film thickness of about 80 nm. As the barrier metal, Ti, Ta, Co, nitrides thereof, or a laminated structure thereof may be used. Thereafter, Cu is plated to a thickness of about 0.3 μm, and the polishing is retreated until the surface of the first sacrificial layer film 411 appears by CMP.

  In FIG. 27, B-B ′ is appended, and this B-B ′ means a cross section along the line B-B ′ shown in FIG. 28. FIG. 28 is a plan view seen through a layer along B-B ′ in FIG. 27.

  As shown in FIG. 28, a region separation unit 404 and a region separation structure 414 (post structure) are provided so as to surround the MEMS region 400. The region separation unit 404 is generated in the LSI region 401. Heat and noise are prevented from conducting to the MEMS region 400 through the substrate 500. In the region isolation structure 414, the two-layer wiring 413 and the second contact wiring 412 are continuously formed on the wall, and the Joule heat due to the power consumed in the LSI region 401 and the first sacrificial layer film 411 are formed. The moisture that has been absorbed is prevented from diffusing into the MEMS region 400. However, the single-layer wiring 409 extending between the MEMS region 400 and the LSI region 401 is covered with insulation, but is disposed and formed so as not to intersect the second contact wiring 412. There is no electrical contact.

  Next, as shown in FIG. 29, a second sacrificial layer film 415 is formed by a coating method. The formation method, material, and the like of the sacrificial layer 415 are the same as those in the first embodiment. Next, the three-layer wiring 416 is formed in the same manner as the two-layer wiring 413. At this time, the region isolation structure 414 forms an uninterrupted wall-like structure surrounding the MEMS region 400 by the three-layer wiring 416.

  Next, as shown in FIG. 30, a third sacrificial layer film 417 is formed by a coating method. The formation method, material, and the like of the sacrificial layer 417 are the same as those in the first embodiment. Next, the four-layer wiring 418 is formed in the same manner as the two-layer wiring 413. At this time, the region isolation structure 414 surrounds the periphery of the MEMS region 400 by the four-layer wiring 418 and forms a wall-like structure without interruption.

  Next, as shown in FIG. 31, a first passivation film 419 (thin film structure), for example, a SiN film is deposited on the third sacrificial film 417 to a thickness of 0.1 μm by CVD, and a resist 420 is formed. Applied. Thereafter, a first opening 422 is formed on the high-speed device region 421 in which the internal wiring parasitic capacitance of the MEMS region 400 and the LSI region 401 becomes a problem by lithography technology and fluorine-based RIE. Further, the first opening 422 may not be formed on the device region 423 that places importance on the internal reliability of the LSI region 401.

  Next, as shown in FIG. 32, the first to third sacrificial films 411, 415, and 417 are etched away by O 2 RIE. At this time, since the sacrificial film thickness is large, the resist 420 is removed at this point. At this point, the region where the sacrificial layer was present becomes the cavity 426, and the hollow MEMS structure 424 and the hollow wiring 425 are formed. In this example, an electrostatic switch was prototyped as the MEMS device 424. The high-speed device region 421 in the LSI region 401 may be formed by forming the same region isolation structure 414 as surrounding the high-speed device region 421 in the LSI region. At the same time, these region isolation structures 414 also support the first passivation film 419 on the cavity 426 and also serve to dissipate heat generated in the LSI region. The region separation structure 414 may be appropriately formed in a columnar shape or a wall shape where the strength of the passivation film 419 is insufficient or heat is confined and there is a harmful effect due to temperature rise.

  Next, as shown in FIG. 33, a thick second passivation film 427 (thin film structure) is formed. For example, the second passivation film 427 is formed by depositing a SiO 2 film with a thickness of 0.5 μm by a sputtering method using Ar as a carrier gas. At this time, by setting the width of the first opening pattern 422 to be equal to or less than twice the thickness of the second passivation film 427, the first opening pattern 422 is blocked by the lateral growth of the second passivation film 427. Therefore, the MEMS region 400 and the high-speed device region 421 are maintained in a reduced pressure Ar atmosphere during the process.

It is sectional drawing which shows roughly the element sealing structure in the MEMS area | region in the manufacturing process of the semiconductor device which concerns on 1st embodiment of this invention. FIG. 2 is a plan view schematically showing a semiconductor device having an element sealing structure shown in FIG. 1. FIG. 2 is a cross-sectional view schematically showing a structure in an LSI region of the semiconductor device in which the element sealing structure shown in FIG. 1 is formed. FIG. 2 is a cross-sectional view schematically showing an element sealing structure in a MEMS region in a semiconductor device manufacturing process following the manufacturing process shown in FIG. 1. FIG. 5 is a plan view schematically showing a semiconductor device having an element sealing structure shown in FIG. 4. FIG. 5 is a cross-sectional view schematically showing a structure in an LSI region of a semiconductor device in which the element sealing structure shown in FIG. 4 is formed. FIG. 5 is a cross-sectional view schematically showing an element sealing structure in a MEMS region in a semiconductor device manufacturing process following the manufacturing process shown in FIG. 4. FIG. 8 is a plan view schematically showing a semiconductor device having an element sealing structure shown in FIG. 7. FIG. 8 is a cross-sectional view schematically showing a structure in an LSI region of a semiconductor device in which the element sealing structure shown in FIG. 7 is formed. FIG. 8 is a cross-sectional view schematically showing an element sealing structure in a MEMS region in a semiconductor device manufacturing process following the manufacturing process shown in FIG. 7. It is a top view which shows roughly the semiconductor device of the element sealing structure shown by FIG. It is sectional drawing which shows roughly the structure in the LSI area | region of the semiconductor device in which the element sealing structure shown by FIG. 10 is formed. FIG. 11 is a cross-sectional view schematically showing an element sealing structure in a MEMS region in a semiconductor device manufacturing process following the manufacturing process shown in FIG. 10. It is a top view which shows roughly the semiconductor device of the element sealing structure shown by FIG. FIG. 14 is a cross-sectional view schematically showing a structure in an LSI region of a semiconductor device in which the element sealing structure shown in FIG. 13 is formed. FIG. 14 is a cross-sectional view schematically showing an element sealing structure in a MEMS region in a semiconductor device manufacturing process following the manufacturing process shown in FIG. 13. FIG. 17 is a plan view schematically showing the semiconductor device having the element sealing structure shown in FIG. 16. FIG. 17 is a cross-sectional view schematically showing a structure in an LSI region of a semiconductor device in which the element sealing structure shown in FIG. 16 is formed. FIG. 17 is a cross sectional view schematically showing an element sealing structure in a MEMS region in a semiconductor device manufacturing process following the manufacturing process shown in FIG. 16. FIG. 20 is a cross-sectional view schematically showing a structure in an LSI region of the semiconductor device in which the element sealing structure shown in FIG. 19 is formed. It is a top view which shows roughly the semiconductor device of the element sealing structure in the MEMS area | region which concerns on 1st embodiment of this invention completed through the manufacturing process of FIGS. FIG. 22 is a cross-sectional view schematically showing a structure in an LSI region of the semiconductor device in which the element sealing structure shown in FIG. 21 is formed. FIG. 22 is a cross-sectional view schematically showing a structure in an LSI region of the semiconductor device in which the element sealing structure shown in FIG. 21 is formed. It is sectional drawing which shows roughly the manufacture process of the semiconductor device which mixedly mounts CMOS and LSI which concern on 2nd Embodiment of this invention on the same board | substrate, and has an element sealing structure. It is sectional drawing which shows roughly the manufacturing process of the semiconductor device which mixedly mounts CMOS and LSI on the same board | substrate, and has an element sealing structure. It is sectional drawing which shows roughly the manufacturing process of the semiconductor device which mixedly mounts CMOS and LSI on the same board | substrate, and has an element sealing structure. It is sectional drawing which shows roughly the manufacturing process of the semiconductor device which mixedly mounts CMOS and LSI on the same board | substrate, and has an element sealing structure. It is a top view which shows roughly the semiconductor device which mixedly mounts CMOS and LSI on the same board | substrate, and has an element sealing structure. It is sectional drawing which shows roughly the manufacturing process of the semiconductor device which mixedly mounts CMOS and LSI on the same board | substrate, and has an element sealing structure. It is sectional drawing which shows roughly the manufacturing process of the semiconductor device which mixedly mounts CMOS and LSI on the same board | substrate, and has an element sealing structure. It is sectional drawing which shows roughly the manufacturing process of the semiconductor device which mixedly mounts CMOS and LSI on the same board | substrate, and has an element sealing structure. It is sectional drawing which shows roughly the manufacturing process of the semiconductor device which mixedly mounts CMOS and LSI on the same board | substrate, and has an element sealing structure. 1 is a cross-sectional view schematically showing a semiconductor device in which a CMOS and an LSI are mixedly mounted on the same substrate and have an element sealing structure.

Explanation of symbols

  99, 400 ... MEMS region, 100 ... Single crystal silicon support substrate, 101 ... Embedded silicon oxide film layer, 102 ... Single crystal silicon layer, 103 ... Infrared sensor pixel, 104, 105 ... Support wiring, 106 ... Horizontal wiring, one layer Wiring, 107 ... vertical wiring, two-layer wiring, 108 ... pn junction diode, 109 ... intra-pixel wiring; 110 ... infrared absorption film, third interlayer film, 111 ... groove, 112 ... first sacrificial film; 113 ... second sacrificial film 114, Etching protection film, 115 ... Resist, 116, 315 ... First opening, 117 ... First thin SiO2 film, 118 ... First thin film, 119 ... Second thin SiO2 film, 120 ... Resist, 121, 316, second opening, 122, hollow structure, 123, second thin film, 124, gap, 125, thin film structure 301, 401 ... LSI region, 302 ... Gate electrode, 303, 304 ... Diffusion layer, 305, 407 ... First interlayer film, 306 ... Contact, 307, 410 ... Second interlayer film, 308 ... Three-layer wiring, 309 ... 3 layer-4 layer contact, 310 ... 4 layer wiring, 311 ... 3 layer wiring passivation film, 312 ... silicon oxide film, 313 ... silicon nitride film, 314 ... 4 layer wiring passivation film, 405 ... transistor, 408 ... first contact Wiring, 409... Single layer wiring, 411... First sacrificial film, 412... Second contact wiring, 413... Two layer wiring, 414 ... Area isolation structure, 415. Three-layer wiring, 417 ... third sacrificial layer film, 418 ... four-layer wiring, 419 ... first passivation film, 42 ... resist, 421 ... fast device region, 422 ... first opening, 423 ... device region, 424 ... MEMS device 425 ... hollow wire, 426 ... cavity, 427 ... second passivation film

Claims (14)

A semiconductor substrate having a first region and a second region adjacent to the first region;
An integrated circuit formed in the second region;
A pillar structure that is formed in a wall shape at the boundary between the first region and the second region, and that electrically and spatially separates the first and second regions;
A thin film structure that is supported by the support structure and is laminated so as to cover the first and second regions;
An element electrically connected to the integrated circuit, comprising a mechanically movable portion disposed in a space formed in the lower portion of the thin film structure in the first region;
A semiconductor device comprising:     2. The wiring layer including the wiring that connects the element and the integrated circuit, is electrically insulated from the support structure, and extends through the support structure. The semiconductor device described.     The semiconductor device according to claim 1, wherein an insulating film that separates the first and second regions is formed on the semiconductor substrate.     3. The semiconductor device according to claim 1, wherein the pillar structure is made of Cu having an oxidation barrier layer made of at least Ti, Ta, Co, or a nitride thereof on a surface thereof. An interlayer insulating layer composed of a plurality of layers covering the integrated circuit, and at least one set of two or more consecutive layers of the plurality of layers includes Si as a main component and at least one of O, N, C, and H An interlayer insulating layer formed of an insulating film containing
5. The semiconductor device according to claim 1, further comprising an input / output wiring for the integrated circuit and the element formed separately from the support structure. The thin film structure is composed of a first thin film in which an opening leading to the space is formed at a predetermined position, and a second thin film formed on the first thin film and closing the opening,
6. The semiconductor device according to claim 1, wherein the space is filled with a reduced pressure state or an inert gas.   The semiconductor device according to claim 6, wherein the width of the opening is not more than twice the film thickness of the second thin film. The elements are two-dimensionally arranged in the space,
The input / output wiring is arranged between the elements and selects the element or reads a signal from the element,
The first thin film of the thin film structure includes a support portion that is connected and supported on the input / output wiring, and the opening that leads to the space is provided in a region other than the support portion. The semiconductor device according to any one of 1 to 5, 6, and 7. The element comprises an infrared absorbing layer that absorbs incident infrared radiation and converts it into heat;
A thermoelectric conversion unit that converts a temperature change due to heat generated in the infrared absorption layer into an electrical signal;
9. The device according to claim 1, further comprising a support wiring that supports the infrared absorption layer and the heat transfer conversion portion in the gap portion and is connected to an input / output end of the heat transfer conversion portion. A semiconductor device according to 1.   The semiconductor device according to claim 9, wherein the thin film structure includes at least one of silicon, copper chloride, germanium, lead selenide, zinc sulfide, and cadmium sulfide.   The semiconductor device according to claim 9, wherein the thermoelectric conversion unit includes a silicon pn junction diode. Element wiring for an element having a mechanical movable part to be formed in a space on a semiconductor substrate, an integrated circuit for processing a signal from the element, and a connection wiring for connecting the element and the integrated circuit Form the
A low hygroscopic interlayer film is formed on the element, the integrated circuit, and the connection wiring,
Depositing a sacrificial film on the interlayer film;
An integrated circuit in which a wiring layer and a contact are formed in the sacrificial film so as to be connected to the element wiring and the integrated circuit, and the element is formed, and an element region in which the element is formed and the integrated circuit is formed. Form a wall-shaped support wiring at the boundary with the area,
Deposit a passivation film,
Forming a first opening in the passivation film above the element region;
Removing the sacrificial film from the first opening to form a first space therein, and disposing the movable portion of the element in the space;
A method of manufacturing a semiconductor device, comprising depositing a thin film and sealing the opening by lateral film growth.   13. The semiconductor device according to claim 12, wherein the sacrificial film is an insulating film having carbon as a main skeleton or an insulating film having pores in the film, and has a dielectric constant of less than 3.3. . Forming a second opening in the passivation film above the element region;
The sacrificial film is removed from the second opening to form a second space therein, and wiring connected to the integrated circuit is disposed in the second space. 14. The semiconductor device according to 12 or 13.

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