JP2006295337A - Video recording/reproducing device, video input device, and video output device coping with multi-channel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video recording and reproducing device dealing with multi-channels like an AV server, wherein a flexible system configuration optionally coping with a plurality of resolutions of a video signal is made possible. <P>SOLUTION: The video recording and reproducing device coping with multi-channels including: a plurality of input sections for respectively receiving a video signal; a plurality of output sections for respectively outputting the video signal; and a recording section for recording the video signals, and recording the video signal received by each input section to the recording section, and outputting the video signal reproduced from the recording section from any output section, and at least one of the input sections includes an input timing pulse generation means 32 that generates a timing pulse whose frequency is switched depending on the resolution of the received video signal and supplying the timing pulse to circuits 22, 34 for applying processing to the video signal in the input section. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multichannel video recording / reproducing apparatus, a video input apparatus, and a video output apparatus that are suitable for application to, for example, an AV server.

  AV (Audio / Video) servers are widely used as recording / sending servers for television broadcasting stations. The AV server generally has a plurality of input / output units for inputting / outputting AV signals in a synchronous transmission format such as SDI (Serial Digital Interface).

  AV signals sent to the AV server from outside (VTRs in broadcasting stations, video cameras at the interview site connected to the broadcasting stations over a wide area network, etc.) are input to one of the input units, and compressed at that input unit. Processed. The AV data subjected to this compression processing is recorded in a recording unit such as a hard disk unit.

  Further, the compressed AV data reproduced from the recording unit and sent to any output unit is subjected to decompression processing or the like in the output unit. Then, it is output from the output unit and sent from the AV server to the outside (on-air server, backup server, etc.).

  In today's television broadcasting, SD (Standard Definition) TV broadcasting and HD (High Definition) TV broadcasting are mixed with the start of terrestrial digital broadcasting in Japan and Western countries. For this reason, both the SDTV signal and HDTV signal (in the case of SDI, SD-SDI, which is a transmission format defined as SMPTE 259M, and SMPTE 292M) are specified for AV signals input and output by the AV server. HD-SDI, which is a transmission format that exists). Furthermore, even with SDTV signals, the resolution is different between the NTSC system employed in Japan, the United States, etc., and the PAL system employed in European countries. Therefore, it is necessary for the AV server to input and output video signals with various resolutions.

  In the conventional AV server, an input / output unit having a fixed resolution of a processable video signal, such as an input / output unit dedicated to an SDTV signal and an input / output unit dedicated to an HDTV signal, is provided.

  On the other hand, although not related to the AV server itself, as a device for receiving serial data, both an SDTV signal waveform shaping unit and an HDTV signal waveform shaping unit are provided, and either SD serial data or HD serial data is transmitted. In the past, a data receiving apparatus has been proposed in which reproduced SD serial data and reproduced HD serial data can be taken out (see, for example, Patent Document 1).

JP 2003-115828 A (paragraph numbers 0117 to 0130, FIG. 8)

  In the conventional AV server, since the resolution of the video signal that can be processed for each input unit and output unit is fixed, it is difficult to construct a flexible system that arbitrarily supports a plurality of resolutions. .

  That is, for example, in an AV server having one input section dedicated to HDTV signals, HDTV signals of two or more channels cannot be input simultaneously. If the input unit is detachable, for example, if one SDTV signal dedicated input unit is replaced with an HDTV signal dedicated input unit, two channels of HDTV signals can be input simultaneously. Is complicated.

  There is also a method in which a maximum number of input units and output units corresponding to each resolution are provided, assuming that up to how many channels of the same resolution video signal are input or output at the same time. However, this method increases the size and cost of the system, and in reality, only a part of the input units and output units are used.

  On the other hand, in the data receiving apparatus disclosed in Patent Document 1, it is possible to share one data receiving apparatus for receiving video signals having different resolutions such as SD serial data and HD serial data. However, after receiving video signals of various resolutions, it is necessary to switch settings according to the respective resolutions in order to perform processing on the video signals. The technology is not disclosed at all in Patent Document 1 described above.

  SUMMARY OF THE INVENTION In view of the above, the present invention has been made with an object to enable a flexible system configuration arbitrarily corresponding to a plurality of resolutions of a video signal in a multi-channel video recording / playback apparatus such as an AV server. Is.

  In order to solve this problem, the present invention includes a plurality of input units that respectively input video signals, a plurality of output units that output video signals, and a recording unit that records video signals. In a multi-channel video recording / reproducing apparatus that records a video signal input to a recording unit to a recording unit and outputs a video signal reproduced from the recording unit from any output unit, at least one input unit includes a video signal in the input unit. The circuit for processing the signal includes an input timing pulse generating means for generating and supplying a timing pulse whose frequency is switched according to the resolution of the input video signal.

  In this multi-channel video recording / reproducing apparatus, a timing pulse whose frequency is switched in accordance with the resolution of an input video signal is generated in one input unit, and the timing pulse is supplied to a circuit for processing the video signal. .

  When video signals with various resolutions are input, it is necessary to switch settings according to the resolution in order to perform processing on those video signals. The frequency of the timing pulse supplied to the circuit that processes the signal is switched according to the resolution.

  According to this multi-channel video recording / reproducing apparatus, such timing pulse frequency switching is performed in one input unit. Thus, one input unit can be shared to input video signals having a plurality of resolutions. Therefore, a flexible system configuration that can arbitrarily correspond to a plurality of resolutions of an input video signal is possible.

  In this multi-channel video recording / playback apparatus, as an example, the input unit is provided with a plurality of compression circuits of compression methods respectively corresponding to a plurality of resolutions of the video signal as a compression circuit for compressing the input video signal. Preferably, control means for compressing the video signal is provided by a compression circuit corresponding to the resolution of the input video signal among these compression circuits, and the input timing pulse generation means preferably supplies timing pulses to these compression circuits. It is.

  As a result, it is possible to compress video signals of various resolutions to be input by a compression method corresponding to each resolution within one input unit.

  In addition, in this multi-channel video recording / reproducing apparatus, as an example, a circuit for processing an audio signal multiplexed with the video signal is provided in the input unit, and the input timing pulse generating means responds to the audio signal. Preferably, further frequency timing pulses are generated and supplied to the circuit.

  Thereby, the frequency of the timing pulse that needs to be supplied to the circuit that processes the video signal, and the frequency of the timing pulse that needs to be supplied to the circuit that processes the audio signal multiplexed on the video signal, Are different, the timing pulse having an appropriate frequency can be supplied to the circuit for processing the audio signal.

  Further, in this multi-channel video recording / reproducing apparatus, as an example, the input unit is provided with a clock extracting means for extracting a clock synchronized with the inputted video signal, and the input timing pulse generating means is supplied to the video recording / reproducing apparatus. The frequency of the reference clock is multiplied or divided according to the resolution of the video signal input to the input unit, and the clock extracted by the clock extracting means using the multiplied or divided reference clock It is preferable to use a means for generating timing pulses.

  As a result, even when a clock that serves as a reference for video signal capture timing is not transmitted and this clock is extracted and played back (clock recovery) on the multi-channel video recording / playback apparatus side, Based on the reference clock, it becomes possible to switch the frequency of the timing pulse in accordance with the resolution of the input video signal in one input unit.

  In addition, when the clock extracting means is provided in this way, as an example, at least a part of the constituent elements of the input timing pulse generating means and the clock extracting means is configured by a programmable logic device and is input to the input unit. It is preferable to program the programmable logic device according to the resolution of the signal to switch the connection relationship between the input timing pulse generation means and the clock extraction means.

  In this multi-channel video recording / reproducing apparatus, as an example, the output unit also has a timing pulse in which the frequency is switched according to the resolution of the video signal reproduced from the recording unit to the circuit that processes the video signal in the output unit. It is preferable to include output timing pulse generation means for generating and supplying the output.

  Thereby, not only the input unit side but also the output unit side, one output unit can be shared to output video signals having a plurality of resolutions. Accordingly, a more flexible system configuration that can arbitrarily correspond to a plurality of resolutions of an input video signal and a recorded video signal is possible.

  In addition, when the output unit is provided with output timing pulse generation means in this way, as an example, the output unit has a plurality of resolutions of the video signal as a decompression circuit that decompresses the compressed video data reproduced from the recording unit. A plurality of decompression circuits each corresponding to a compression method are provided, and control means for decompressing the compressed video data is provided by the decompression circuit corresponding to the resolution of the video signal to be output among these decompression circuits. It is preferable to supply timing pulses to these decompression circuits.

  As a result, video signals having a plurality of resolutions recorded by being compressed by a compression method corresponding to each resolution can be expanded in a single output unit by a compression method corresponding to the resolution.

  Further, when the output unit is provided with the output timing pulse generating means as described above, as an example, the output unit is provided with a circuit for processing the audio signal reproduced from the recording unit, and the output timing pulse generating means is It is preferable that a timing pulse having a frequency corresponding to the audio signal is further generated and supplied to the circuit.

  Thus, when the frequency of the timing pulse that needs to be supplied to the circuit that processes the video signal is different from the frequency of the timing pulse that needs to be supplied to the circuit that processes the audio signal, A timing pulse having an appropriate frequency can be supplied to the processing circuit.

  Further, when the output unit is provided with the output timing pulse generation unit as described above, as an example, the output timing pulse generation unit is provided in the video recording / reproducing apparatus according to the resolution of the video signal reproduced from the recording unit. It is preferable to use a means for multiplying or dividing the frequency of the supplied reference clock and a means for generating a timing pulse from the multiplied or divided reference clock.

  Thereby, based on the reference clock of a single frequency, the frequency of the timing pulse can be switched in one output unit according to the resolution of the video signal recorded in the recording unit.

  Further, when the output unit is provided with the output timing pulse generating means in this way, as an example, it is preferable that at least a part of the constituent elements of the output timing pulse generating means is configured by a programmable logic device. .

  Next, the present invention includes a plurality of video input devices that respectively input video signals, a plurality of video output devices that output video signals, and a recording device that records video signals. Input video signal in a video input device for constituting a multi-channel video recording / playback system that records the input video signal in a recording device and outputs the video signal reproduced from the recording device from any video output device As a compression circuit that compresses the video signal, it has a plurality of compression circuits of a compression method respectively corresponding to the plurality of resolutions of the video signal, and the compression circuit corresponding to the resolution of the input video signal among these compression circuits compresses the video signal. Control means for generating the timing pulses to be supplied to these compression circuits by switching the frequency according to the resolution of the input video signal Characterized by comprising a Iminguparusu generation means.

  Further, the present invention provides a video output device for constituting such a multi-channel video recording / playback system, which corresponds to each of a plurality of resolutions of video signals as a decompression circuit for decompressing compressed video data reproduced from the recording device. A plurality of compression-type decompression circuits and a control means for decompressing the compressed video data with the decompression circuit corresponding to the resolution of the video signal to be output among these decompression circuits, and timing pulses supplied to these decompression circuits, And a timing pulse generating means for generating a frequency by switching the frequency according to the resolution of the compressed video data reproduced from the recording apparatus.

  These video input device and video output device respectively correspond to an input unit and an output unit in the multi-channel video recording / reproducing device according to the present invention (Claim 1), and these video input device and video output device. By configuring a multi-channel video recording / reproducing system using the above, a flexible system configuration that arbitrarily supports a plurality of resolutions of the video signal becomes possible.

  According to the present invention, for example, in a multi-channel video recording / reproducing apparatus such as an AV server, it is possible to obtain a flexible system configuration arbitrarily corresponding to a plurality of resolutions of video signals.

  Next, embodiments of the present invention will be specifically described with reference to the drawings. In the following, an example in which the present invention is applied to an AV server that inputs and outputs AV signals in the SDI format will be described.

  FIG. 1 is a block diagram showing the overall configuration of a server system comprising an AV server to which the present invention is applied and a terminal that controls the AV server. This AV server 1 receives a multi-channel AV signal (SDTV signal or HDTV signal) from a VTR in a broadcasting station, a video camera etc. (not shown) at a coverage site connected to the broadcasting station through a wide area network, in an SDI format. (SD-SDI in the case of an SDTV signal, HD-SDI in the case of an HDTV signal).

  The AV server 1 has a plurality of input units and output units (an input board and an output board, which will be described later). The AV signal of each transmitted channel is input from one of the input units, and a recording unit ( Recorded on a hard disk unit (to be described later).

  The AV server 1 outputs AV data reproduced from the recording unit in an SDI format (SD-SDI or HD-SDI) from one of the output units, and an on-air server, a backup server, or the like (not shown). )

  The AV server 1 also transmits and receives AV data via the high-speed network (Gigabit Ethernet) 3 according to the TCP / IP protocol. (ETHERNET \ Ethernet is a registered trademark.)

  The control terminal 2 is a terminal that sends a control signal c to the AV server 1 by serial communication (RS-422A). For example, a workstation or a personal computer is used. From the control terminal 2, as the control signal c, not only a control signal specifying which input unit or output unit is used to input / output the AV signal, but also an SDTV signal or an HDTV signal is input to the input unit. Is sent to the AV server 1 as a control signal for instructing whether to output an SDTV signal recorded on the AV server 1 or an HDTV signal from its output unit.

  FIG. 2 is a block diagram showing the internal configuration of the AV server 1. The AV server 1 is provided with a plurality of input / output units 4, a plurality of hard disk units 5, a network management terminal 6, and a file management terminal 7.

  Each input / output unit 4 has a total of six input units and output units, respectively. From the control terminal 2 in FIG. 1, the control signal c described above is sent to these input / output units 4.

  Each hard disk unit 5 is a disk array device that employs RAID (Redundant Arrays of Inexpensive Disks) technology. Each input / output unit 4 and each hard disk unit 5 are connected to each other via an FC switch 9 by a fiber channel 8 which is a high-speed serial interface.

  The network management terminal 6 is a terminal that manages transmission / reception of AV data via the high-speed network 3 of FIG. 1, and a personal computer is used. The network management terminal 6 is also connected to each hard disk unit 5 via the FC switch 9 via the fiber channel 8.

  The file management terminal 7 is a terminal that manages in which position on the hard disk the AV data recorded as a file in each hard disk unit 5 is actually written, and a personal computer is used. Each input / output unit 4 and the file management terminal 7 are connected to each other by the Ethernet 10.

  The input / output unit 4 is configured by connecting a plurality of substrates. FIG. 3 is a block diagram showing a substrate constituting the input / output unit 4. A total of a maximum of six input boards 11 and output boards 12 (three input boards 11 and three output boards 12 in the illustrated example) are connected to the motherboard 16. Each input board 11 and output board 12 are detachably connected to the mother board 16 by being inserted into a slot (not shown) provided in the housing of the input / output unit 4.

  Each input board 11 has a role as an input unit for inputting an AV signal of one channel, and the input AV signal (SDI format data) is recorded on the hard disk unit 5 in FIG. Convert to data. As will be described later, each input board 11 is shared to input both SDTV signals and HDTV signals (SD-SDI, HD-SDI).

  Each output board 12 has a role as an output unit that outputs an AV signal of one channel, and converts AV data reproduced from the hard disk unit 5 into an SDI format and outputs the data. As will be described later, each output board 12 is also shared to output both SDTV signals and HDTV signals.

  The motherboard 16 further includes a board (hereinafter referred to as a main control board) 13 on which a main CPU (not shown) is mounted and a board (referred to as an FC board) on which a fiber channel interface circuit (not shown) is mounted. 14) and a board (to be referred to as a TG board) 15 for inputting a reference clock supplied to the AV server 1 from the outside.

  The motherboard 16 has a CPU bus 17 that connects the CPUs (not shown) in each of the boards 11 to 15, and an SB (Serial Back-Plane) bus 18 that connects each input board 11, output board 12, and FC board board 14. have.

  From the control terminal 2 in FIG. 1, the control signal c is sent to the main CPU in the main control board 13 via each input board 11, each output board 12, and the mother board 16. The main CPU in the main control board 13 is connected to the Ethernet 10 in FIG.

  As shown in FIG. 2, the FC board 14 is connected to each hard disk unit 5 via the FC switch 9 by the fiber channel 8.

  The TG board 15 supplies a reference clock ref of 27 MHz (the same frequency as the sampling frequency of the SDTV signal) to each input board 11 and output board 12 based on a reference clock from the outside.

  FIG. 4 is a block diagram showing main circuits on the input board 11 and the output board 12 of FIG. On the input board 11, an input signal processing unit 21, a video signal compression processing unit 22, an audio signal compression processing unit 23, a recording signal processing unit 24, and a recording processing control unit 25 are mounted. The recording process control unit 25 is a CPU that controls each of the processing units 21 to 24 under the control of the main CPU on the main control board 13 of FIG.

  The input signal processing unit 21 is a circuit that extracts a video signal and an audio signal from SDI format data input to the input board 11 and generates a timing pulse synchronized with the video signal and the audio signal. The configuration and processing of the input signal processing unit 21 will be described in detail later with reference to FIGS.

  The video signal compression processing unit 22 is a circuit that compresses the video signal extracted by the input signal processing unit 21. The video signal compression processing unit 22 includes MPEG2 MP @ ML standard compression circuit 22a, IMX (MPEG2 422P @ ML) standard compression circuit 22b, and DV standard compression circuits as coding standard compression circuits corresponding to SDTV signals. A compression circuit 22c is provided. Further, the video signal compression processing unit 22 is provided with a compression circuit 22d of the MPEG2 MP @ HL standard as a circuit for compressing the HDTV signal.

  The audio signal compression processing unit 23 is a circuit that compresses the audio signal extracted by the input signal processing unit 21 according to the MPEG1 standard.

  The recording signal processing unit 24 packs the video data compressed by the video signal compression processing unit 22 and the audio data compressed by the audio signal compression processing unit 23 so as to record in the hard disk unit 5 of FIG. This circuit generates AV data.

  The AV data generated by the recording signal processing unit 24 is transferred to the hard disk unit 5 shown in FIG. 2 via the mother board 16 and the FC board 14 shown in FIG.

  On the output board 12, a reproduction signal processing unit 26, a video signal expansion processing unit 27, an audio signal expansion processing unit 28, an output signal processing unit 29, and a reproduction processing control unit 30 are mounted. The reproduction processing control unit 30 is a CPU that controls each of the processing units 26 to 29 under the control of the main CPU on the main control board 13.

  The reproduction signal processing unit 26 is a circuit that separates compressed video data and compressed audio data from AV data reproduced from the hard disk unit 5 and transferred via the FC board 14 and the motherboard 16.

  The video signal decompression processing unit 27 is a circuit that decompresses the compressed video data separated by the reproduction signal processing unit 26. The video signal expansion processing unit 27 includes an MPEG2 MP @ ML standard expansion circuit 27a and an IMX (MPEG2 422P) corresponding to the compression method of the compression circuits 22a to 22d in the video signal compression processing unit 22 on the input board 11. @ML) standard expansion circuit 27b, DV standard expansion circuit 27c, and MPEG2 MP @ HL standard expansion circuit 27d.

  The audio signal expansion processing unit 28 is a circuit that expands the compressed audio data separated by the reproduction signal processing unit 26 in accordance with the MPEG1 standard.

  The output signal processing unit 29 generates timing pulses to be supplied to the video signal expansion processing unit 27, the audio signal expansion processing unit 28, and the like, and the video signal and audio signal expansion processing unit 28 expanded by the video signal expansion processing unit 27. This is a circuit that generates SDI format data from the audio signal decompressed in step S1 and outputs it from the output board 12. The configuration and processing of the output signal processing unit 29 will be described in detail later with reference to FIGS.

  FIG. 5 is a block diagram showing a circuit configuration of a main part of the input signal processing unit 21 of FIG. The input signal processing unit 21 is provided with an SDI receiver 31, a timing generator 32, an error detection circuit 33, and an SDI decoder 34.

  The SDI receiver 31 includes an SDI input circuit that converts SDI format data input to the input signal processing unit 21 into differential data, a clock recovery circuit that extracts and reproduces a clock from the differential data, and the differential data. And a serial / parallel conversion circuit for parallel conversion. The clock regenerated by the clock recovery circuit is sent to the timing generator 32. The data converted in parallel by the serial / parallel conversion circuit is sent to the error correction circuit 33.

  The timing generator 32 generates timing pulses for driving the error correction circuit 33 and the video signal compression processing unit 22 and the audio signal compression processing unit 23 of FIG. 4 from the clock reproduced by the clock recovery circuit in the SDI receiver 31. Circuit. The timing generator 32 is supplied with the aforementioned 27 MHz reference clock ref from the TG board 15 of FIG.

  The error correction circuit 33 is a circuit that performs error correction by calculating a checksum from parallel data in the SDI format sent from the SDI receiver 31.

  The SDI decoder 34 is a circuit that decodes the parallel data of the SDI format that has been error-corrected by the error correction circuit 33 (NRZI → NRZ conversion and descrambling) to restore the video signal and the audio signal. As the SDI decoder 34, a decoder having specifications corresponding to both the SD-SDI format and the HD-SDI format is used.

  The video signal restored by the SDI decoder 34 is sent to the video signal compression processing unit 22. The audio signal restored by the SDI decoder 34 is sent to the audio signal compression processing unit 23.

  FIG. 6 is a block diagram showing in more detail the configuration of the clock system (SDI receiver 31 and timing generator 32) in the configuration of the input signal processing unit 21 shown in FIG. The clock system of the input signal processing unit 21 includes an FPGA (Field Programmable Gate Array) 41 which is a kind of PLD (Programmable Logic Device), a PLL (Phase Comparator, Filter and Voltage Controlled Oscillator) 42, an amplifier 43, A differential driver 44, a PLL 45, and amplifiers 46 and 47 are provided.

  The FPGA 41 includes a frequency divider 50, a frequency divider 51, a PLL 52, a PLL 53, a clock recovery circuit 54, a PLL 55, and a PLL 56 as expansion circuits. The frequency divider 50, the frequency divider 51, the PLL 52, and the PLL 53 constitute the timing generator 32 of FIG. The clock recovery circuit 54 is a component of the SDI receiver 31 in FIG. Specifically, a circuit having a specification capable of handling input data with a bit rate of 400 Mbps or more is used as the clock recovery circuit 54.

  The FPGA 41 is configured by loading a program from the interface circuit 48 for FPGA. The interface circuit 48 is connected to a flash memory 49 storing a program for SDTV signals and a program for HDTV signals. Under the control of the recording processing control unit 25 in FIG. The program for the SDTV signal is read from the flash memory 49 and loaded into the FPGA 41. When the HDTV signal is input, the program for the HDTV signal is read from the flash memory 49 and loaded into the FPGA 41.

  FIG. 6 shows a clock system setting when an SDTV signal is input. Of the connection relationship of the circuits in the FPGA 41 at this time, the same part as that when the HDTV signal is input (FIG. 7 described later) is drawn with a thin line, and the different part is drawn with a thick line.

  Differential data is supplied to the clock recovery circuit 54 from an SDI input circuit 57 which is a component of the SDI receiver 31 of FIG.

  The above-described 27 MHz reference clock ref from the TG board 15 of FIG. 3 is supplied to the frequency divider 50 after being converted into a differential clock by the differential driver 58. The frequency divider 50 sends information on the frequency division ratio to the PLL 42. The frequency divider 51 sends the frequency division ratio information to the PLL 45.

  A timing pulse is supplied from the PLL 52 to the audio signal compression processing unit 23 of FIG. Timing pulses are supplied from the PLL 53 to the SDI decoder 34 in FIG. 5 and the video signal compression processing unit 22 (compression circuits 22a to 22d) in FIG.

  The operation of this clock system when an SDTV signal is input is as follows. Since the SD-SDI bit rate (here, level C bit rate) is 270 Mbps, differential data is supplied from the SDI input circuit 57 to the clock recovery circuit 54 at 270 Mbps when an SDTV signal is input.

  At this time, the frequency divider 50 and the PLL 42 generate a 27 MHz clock synchronized with the reference clock ref, and this clock is supplied from the amplifier 43 to the PLL 55. The PLL 55 generates a 130 MHz clock obtained by multiplying the clock by 5 and supplies it to the clock recovery circuit 54.

  The clock recovery circuit 54 treats the differential data of 270 Mbps from the SDI input circuit 57 as the differential data of 1.35 Gbps based on the reference-synchronized 130 MHz clock from the PLL 55, and 135 MHz synchronized with the differential data. Generate a clock. Then, this 135 MHz clock is supplied to the PLL 56.

  The PLL 56 generates 27 MHz, 135 MHz, and 270 MHz clocks synchronized with the input data from this clock and supplies them to the clock recovery circuit 54, respectively. The clock recovery circuit 54 supplies the 27 MHz clock among them to the frequency divider 51.

  The frequency divider 51 and the PLL 45 remove (reclock) jitter from the 27 MHz clock. The 27 MHz clock output from the PLL 45 is supplied from the amplifier 46 to the PLL 52 and also supplied from the amplifier 47 to the PLL 53. In this way, when an SDTV signal is input, a 27 MHz clock synchronized with the input SDTV signal is supplied to the PLL 52 and the PLL 53.

  The PLL 52 generates a 27 MHz timing pulse from this input-synchronized 27 MHz clock, and supplies the timing pulse to the audio signal compression processing unit 23. The PLL 53 generates a 27 MHz timing pulse from the input synchronous 27 MHz clock and supplies the timing pulse to the SDI decoder 34 and the video signal compression processing unit 22.

  The amplifier 47 is also supplied with an input-synchronized 27 MHz clock from the clock recovery circuit 54, and the PLL 53 generates a 135 MHz clock from the input-synchronized 27 MHz clock and supplies it to the clock recovery circuit 54. This is a clock used when the input data is output to the outside of the input board 11 for debugging as a result of the processing in the error correction circuit 33 of FIG.

  FIG. 7 shows the setting of this clock system when an HDTV signal is input. Of the connection relationship of the circuits in the FPGA 41, the same part as that at the time of SDTV signal input (FIG. 6) is drawn with a thin line, and the different part is drawn with a thick line.

  Further, at this time, the PLLs 55 and 56 in FIG. 6 are not connected to the clock recovery circuit 54 (not used as a clock system), and therefore are not shown.

  The operation of this clock system when an HDTV signal is input is as follows. Since the HD-SDI bit rate is 1.5 Gbps, differential data is supplied from the SDI input circuit 57 to the clock recovery circuit 54 at 1.5 Gbps when an HDTV signal is input.

  At this time, the frequency divider 50 and the PLL 42 generate a clock of 74 MHz (the same frequency as the sampling frequency of the HDTV signal) synchronized with the reference clock ref, and this clock is converted into a differential clock by the differential driver 44 and recovered. This is supplied to the circuit 54.

  The clock recovery circuit 54 generates a 74 MHz clock synchronized with the 1.5 Gbps differential data from the SDI input circuit 57 based on the reference synchronized 74 MHz clock from the PLL 55. Then, the 74 MHz clock is supplied to the frequency divider 51 and the PLL 53.

  The frequency divider 51 and the PLL 45 generate a 27 MHz clock from the 74 MHz clock. The 74 MHz clock output from the PLL 45 is supplied from the amplifier 46 to the PLL 52. In this way, when an HDTV signal is input, a 27 MHz clock synchronized with the input HDTV signal is supplied to the PLL 52, and a 74 MHz clock synchronized with the input HDTV signal is supplied to the PLL 53.

  The PLL 52 generates a 27 MHz timing pulse from this input-synchronized 27 MHz clock, and supplies the timing pulse to the audio signal compression processing unit 23. The PLL 53 generates a 74 MHz timing pulse from the input synchronous 74 MHz clock, and supplies the timing pulse to the error correction circuit 33 and the video signal compression processing unit 22.

  Next, FIG. 8 is a block diagram showing a circuit configuration of a main part of the output signal processing unit 29 shown in FIG. The output signal processing unit 29 is provided with a timing generator 61, an SDI encoder 62, and an SDI driver 63.

  The aforementioned 27 MHz reference clock ref is supplied to the timing generator 61 from the TG board 15 of FIG. The timing generator 61 is a circuit that generates timing pulses for driving the SDI encoder 62, the video signal expansion processing unit 27, and the audio signal expansion processing unit 28 of FIG. 4 from the reference clock ref.

  The SDI encoder 62 encodes (scrambles and NRZ → NRZI conversion) the video signal expanded by the video signal expansion processing unit 27 and the audio signal expanded by the audio signal expansion processing unit 28 in accordance with the SDI format. It is. As the DI encoder 62, an encoder having specifications compatible with both the SD-SDI format and the HD-SDI format is used.

  The SDI driver 63 includes a parallel / serial conversion circuit that serially converts the data encoded by the SDI encoder 62.

  FIG. 9 is a block diagram showing in more detail the configuration of the timing generator 61 that is the clock system in the configuration of the output signal processing unit 29 shown in FIG. The timing generator 61 is provided with an FPGA 71, a PLL 72, amplifiers 73 and 74, a PLL 75, and an amplifier 76.

  The FPGA 71 includes a frequency divider 79, a frequency divider 80, a PLL 81, and a PLL 82 as expansion circuits.

  The FPGA 71 is configured by loading a program from the interface circuit 77 for FPGA. The interface circuit 77 is connected to a flash memory 78 storing a program for SDTV signals and a program for HDTV signals. Under the control of the reproduction processing control unit 30 in FIG. A program for SDTV signals is read from the flash memory 78 and loaded into the FPGA 71. When an HDTV signal is input, a program for HDTV signals is read from the flash memory 78 and loaded into the FPGA 71.

  FIG. 9 shows the setting of the timing generator 61 when the SDTV signal is output. The 27 MHz reference clock ref from the TG board 15 of FIG. 3 is converted into a differential clock by the differential driver 83 and supplied to the frequency divider 79 and the frequency divider 80, respectively. The frequency divider 79 sends frequency division ratio information to the PLL 72. The frequency divider 80 sends frequency division ratio information to the PLL 75.

  Timing pulses are supplied from the PLL 81 to the video signal expansion processing unit 27 (expansion circuits 27a to 27d) in FIG. 4 and the SDI encoder 62 in FIG. A timing pulse is supplied from the PLL 82 to the audio signal expansion processing unit 28 of FIG.

  The operation of the timing generator 61 when the SDTV signal is output is as follows. When outputting the SDTV signal, the frequency divider 79 and the PLL 72 generate a 27 MHz clock synchronized with the reference clock ref. This clock is supplied from the amplifier 73 to the PLL 82.

  The 27 MHz clock generated by the frequency divider 79 and the PLL 72 is supplied to the amplifier 74, the output of the amplifier 74 is supplied to the PLL 81, and the clock generated by the frequency divider 80 and the PLL 75 is supplied to the amplifier 76. Then, the output of the amplifier 76 is supplied to the PLL 81.

  When the SDTV signal is output, the frequency divider 80 does not operate (the amplifier 76 is also turned off), and the 27 MHz clock from the PLL 72 is supplied to the PLL 81.

  In this way, when outputting the SDTV signal, a 27 MHz clock synchronized with the reference clock ref is supplied to the PLL 81 and the PLL 82. The PLL 81 generates a 27 MHz timing pulse from the reference-synchronized 27 MHz clock, and supplies the timing pulse to the SDI encoder 62 and the video signal expansion processing unit 27. The PLL 82 generates a 27 MHz timing pulse from the reference-synchronized 27 MHz clock and supplies the timing pulse to the audio signal expansion processing unit 28.

  FIG. 10 shows the setting of the timing generator 61 when the HDTV signal is output. The connection relationship of the circuits in the FPGA 71 is the same as when the SDTV signal is output (FIG. 9).

  The operation of the timing generator 61 when outputting an HDTV signal is as follows. Even when the HDTV signal is output, the frequency divider 79 and the PLL 72 generate a 27 MHz clock synchronized with the reference clock ref. This clock is supplied from the amplifier 73 to the PLL 82.

  The 27 MHz clock generated by the frequency divider 79 and the PLL 72 is supplied to the amplifier 74, the output of the amplifier 74 is supplied to the PLL 81, and the clock generated by the frequency divider 80 and the PLL 75 is supplied to the amplifier 76. Then, the output of the amplifier 76 is supplied to the PLL 81.

  When the HDTV signal is output, the frequency divider 80 and the PLL 75 generate a 74 MHz clock synchronized with the reference clock ref, the amplifier 74 is turned off, and the 74 MHz clock from the PLL 75 is supplied to the PLL 81.

  In this way, when outputting an HDTV signal, a 74 MHz clock synchronized with the reference clock ref is supplied to the PLL 81, and a 27 MHz clock synchronized with the reference clock ref is supplied to the PLL 82. The PLL 81 generates a 74 MHz timing pulse from the reference-synchronized 74 MHz clock, and supplies the timing pulse to the SDI encoder 62 and the video signal expansion processing unit 27. The PLL 82 generates a 27 MHz timing pulse from the reference-synchronized 27 MHz clock and supplies the timing pulse to the audio signal expansion processing unit 28.

  Next, when the control terminal 2 of FIG. 1 designates that an AV signal is input to any input board 11 of the AV server 1, or the AV signal recorded in the AV server 1 is output from any output board 12. A process of the input board 11 and the output board 12 when the output is designated will be described.

  FIG. 11 is a flowchart showing processing of the main control board 13 and the input board 11 when the control terminal 2 designates that any one of the input boards 11 inputs an AV signal. As described above, in addition to the control signal designating which input board 11 the AV signal is input from the control terminal 2, which of the SDTV signal and the HDTV signal is input to the input board 11 is input. A designated control signal is sent to the AV server 1. This control signal is sent to the main CPU on the main control board 13 (FIG. 3) in the input / output unit 4 (FIG. 4) of the AV server 1.

  Based on the control signal from the control terminal 2, the main CPU on the main control board 13 receives the AV signal to be input to the recording processing control unit 25 on the designated input board 11 as shown in FIG. , Resolution information indicating which of the HDTV signals is transmitted (step S1).

  In the designated input board 11, the recording processing control unit 25 performs settings for the input signal processing unit 21 and the video signal compression processing unit 22 (FIG. 4) based on the resolution information (step S11).

  In step S11, when an SDTV signal is input, the program for the SDTV signal is loaded into the FPGA 41 in the input signal processing unit 21, and the clock system in the input signal processing unit 21 is described with reference to FIG. Set as you did. Of the compression circuits 22a to 22d of the video signal compression processing unit 22, only one compression circuit for SDTV signals (any one of the compression circuits 22a to 22c) operates, and the remaining compression circuits. Set to not work.

  On the other hand, when an HDTV signal is input, in step S11, the FPGA 41 in the input signal processing unit 21 is loaded with a program for the HDTV signal, and the clock system in the input signal processing unit 21 is used with reference to FIG. Set as described. In addition, among the compression circuits 22a to 22d of the video signal compression processing unit 22, only the HDTV signal compression circuit 22d operates, and the remaining compression circuits are set not to operate.

  Subsequently, the recording process control unit 25 notifies the main CPU on the main control board 13 that this setting has been completed (step S12).

  In response to this, the main CPU on the main control board 13 transmits a recording operation start instruction for the input AV signal to the recording processing control unit 25 on the input board 11 (step S2).

  When this recording operation start instruction is transmitted, the recording processing control unit 25 controls the processing units 21 to 24 (FIG. 4) of the input board 11 based on the setting result in step S11, and inputs the AV signal to be input. Process (step S13).

  As a result, when an SDTV signal is input, a timing pulse of 27 MHz (sampling frequency of the SDTV signal) is supplied to the SDI decoder 34 and the video signal compression processing unit 22 as described with reference to FIG. The SDI decoder 34 is driven by the 27 MHz timing pulse, and decodes the parallel data in the SD-SDI format to restore the SDTV signal and the audio signal. In addition, any one of the compression circuits for the SDTV signal in the video signal compression processing unit 22 is driven by the 27 MHz timing pulse and compresses the SDTV signal restored by the SDI decoder 34.

  On the other hand, when an HDTV signal is input, a timing pulse of 74 MHz (a sampling frequency of the HDTV signal) is supplied to the SDI decoder 34 and the video signal compression processing unit 22 as described with reference to FIG. The SDI decoder 34 is driven by this 74 MHz timing pulse, decodes the parallel data of the HD-SDI format, and restores the HDTV signal and the audio signal. In addition, the HDTV signal compression circuit 22 d in the video signal compression processing unit 22 is driven by the timing pulse of 74 MHz and compresses the HDTV signal restored by the SDI decoder 34.

  Further, at the time of input of either an SDTV signal or an HDTV signal, the same 27 MHz timing pulse is supplied to the audio signal compression processing unit 23 as described with reference to FIGS. The audio signal compression processing unit 23 compresses the audio signal driven by the 27 MHz timing pulse and restored by the SDI decoder 34.

  Subsequently, when the first AV data for recording on the hard disk unit 5 (FIG. 2) is generated, the recording processing control unit 25 notifies the main CPU on the main control board 13 (step S14).

  In response, the main CPU on the main control board 13 transmits an AV data recording operation start instruction to the FC board 14 (FIG. 3) and the hard disk unit 5 (step S3). As a result, the AV data generated by the input board 11 is transferred to the hard disk unit 5 via the mother board 12 (FIG. 3) and the FC board 14 and recorded on the hard disk unit 5.

  Thereafter, when a control signal for instructing the end of AV signal input is sent from the control terminal 2, the main CPU on the main control board 13 transmits a recording operation end instruction to the recording processing control unit 25 on the input board 11 (steps). S4).

  Based on this recording operation end instruction, the recording processing control unit 25 ends the processing of the processing units 21 to 24 of the input board 11 for the AV signal input thereafter (step S15). When the last AV data for recording is generated from the AV signals input so far, this is transmitted to the main CPU on the main control board 13 (step S16).

  In response, the main CPU on the main control board 13 transmits a recording operation end instruction to the FC board 14 and the hard disk unit 5 (step S17). As a result, after the AV data generated last by the input board 11 is recorded in the hard disk unit 5, the recording operation to the hard disk unit 5 is completed.

  FIG. 12 is a flowchart showing processing of the main control board 13 and the output board 12 when the control terminal 2 designates output of an AV signal from any of the output boards 12. As described above, the control terminal 2 includes the SDTV signal and the HDTV signal recorded in the AV server 1 in addition to the control signal for designating which output board 12 the AV signal recorded in the AV server 1 is output from. A control signal is sent to the AV server 1 for designating which one of these is to be output from the output board 12. This control signal is sent to the main CPU on the main control board 13 (FIG. 3) in the input / output unit 4 (FIG. 4) of the AV server 1.

  Based on the control signal from the control terminal 2, the main CPU on the main control board 13 outputs the AV signal to be output to the reproduction processing control unit 30 on the designated output board 12 as shown in FIG. , Resolution information indicating which of the HDTV signals is transmitted (step S21).

  In the designated output board 12, the reproduction processing control unit 30 makes settings for the output signal processing unit 29 and the video signal expansion processing unit 27 (FIG. 4) based on the resolution information (step S31).

  In this step S31, when the SDTV signal is output, the program for the SDTV signal is loaded into the FPGA 71 in the output signal processing unit 29, and the timing generator 61 in the output signal processing unit 29 is used with reference to FIG. Set as described. Of the decompression circuits 27a to 27d of the video signal decompression processing unit 27, only the decompression circuit (any one of the decompression circuits 27a to 27c) corresponding to the compression method that compresses the SDTV signal to be output operates. The remaining decompression circuits are set not to operate.

  On the other hand, when outputting the HDTV signal, in step S31, the FPGA 71 in the output signal processing unit 29 is loaded with the program for the HDTV signal, and the timing generator 61 in the output signal processing unit 29 is used with reference to FIG. Set as described above. Also, among the expansion circuits 27a to 27d of the video signal expansion processing unit 27, only the expansion circuit 27d is set to operate and the remaining expansion circuits are set not to operate.

  Subsequently, the reproduction processing control unit 30 notifies the main CPU on the main control board 13 that this setting has been completed (step S32).

  In response to this, the main CPU on the main control board 13 transmits an AV signal reproduction operation start instruction to the FC board 14 (FIG. 3) and the hard disk unit 5 (FIG. 2) (step S22). A reproduction operation start instruction is transmitted to the reproduction processing control unit 30 on the output board 12 (step S23).

  When this reproduction operation start instruction is transmitted, the reproduction processing control unit 30 controls each of the processing units 26 to 29 (FIG. 4) of the output board 12 based on the setting result in step S31 to reproduce from the hard disk unit 5. Then, the transferred AV data is processed (step S33).

  As a result, as described with reference to FIG. 9, the timing pulse of 27 MHz (the sampling frequency of the SDTV signal) is supplied to the video signal expansion processing unit 27 and the SDI encoder 62 when the SDTV signal is output. One of the video signal expansion processing units 27 corresponding to a compression method in which the SDTV signal to be output is compressed is driven by the timing pulse of 27 MHz, transferred from the hard disk unit 5, and reproduced signal processing unit 26. The video data (compressed SDTV signal) separated in step 1 is expanded. The SDI encoder 62 is driven by the 27 MHz timing pulse, and the SDTV signal expanded by the video signal expansion processing unit 27 and the audio signal expanded by the audio signal expansion processing unit 28 are converted into an SD-SDI format. Encode as usual.

  On the other hand, at the time of outputting an HDTV signal, a timing pulse of 74 MHz (HDTV signal sampling frequency) is supplied to the video signal expansion processing unit 27 and the SDI encoder 62 as described with reference to FIG. The decompression circuit 27d of the video signal decompression processing unit 27 is driven by the timing pulse of 74 MHz, and decompresses the video data (compressed HDTV signal) transferred from the hard disk unit 5 and separated by the reproduction signal processing unit 26. To do. The SDI encoder 62 is driven by the timing pulse of 74 MHz, and the HDTV signal expanded by the video signal expansion processing unit 27 and the audio signal expanded by the audio signal expansion processing unit 28 are converted into an HD-SDI format. Encode as usual.

  Further, at the time of output of either the SDTV signal or the HDTV signal, the same 27 MHz timing pulse is supplied to the audio signal expansion processing unit 28 as described with reference to FIGS. The audio signal expansion processing unit 28 expands the audio data driven by the 27 MHz timing pulse, transferred from the hard disk unit 5 and separated by the reproduction signal processing unit 26.

  As a result, both the SDTV signal and the HDTV signal recorded in the AV server 1 are output from the output board 12 in the SDI format (SD-SDI, HD-SDI format).

  Thereafter, when a control signal instructing the end of output of the AV signal is sent from the control terminal 2, the main CPU on the main control board 13 transmits a reproduction operation end instruction to the FC board 14 and the hard disk unit 5 (step S24). Thereafter, a reproduction operation end instruction is transmitted to the reproduction processing control unit 30 on the output board 12 (step S25).

  Based on this reproduction operation end instruction, the reproduction processing control unit 30 ends the processing of each of the processing units 26 to 29 of the output board 12 (step S34).

  As described above, this AV server 1 generates a timing pulse in which the frequency is switched in one input board 11 in accordance with the resolution (SDTV signal or HDTV signal) of the input video signal. The timing pulse is supplied to the SDI decoder 34 and the video signal compression processing unit 22. Similarly, in one output board 12, a timing pulse whose frequency is switched according to the resolution (SDTV signal or HDTV signal) of the output video signal is generated, and the timing pulse is expanded to the video signal. The data is supplied to the processing unit 27 and the SDI encoder 62.

  When video signals with various resolutions are input, it is necessary to switch settings according to the resolution in order to perform processing on those video signals. The frequency of the timing pulse supplied to the circuit that processes the signal is switched according to the resolution.

  According to the AV server 1, the frequency of the timing pulse is switched in one input board 11 and one output board 12 based on a single frequency reference clock. As a result, one input board 11 and one output board 12 can be shared to input and output video signals (SDTV signals and HDTV signals) having a plurality of resolutions.

  Therefore, when three input boards 11 and three output boards 12 are connected to the mother board 16 as shown in FIG. 3, three channels of SDTV signals can be simultaneously transmitted without replacing the input board 11 and the output board 12. Input and record, simultaneous input and recording of 3 channel HDTV signals, simultaneous output of recorded 3 channel SDTV signals, and simultaneous output of recorded 3 channel HDTV signals it can.

  In this way, the system can be flexibly configured to arbitrarily support multiple resolutions of video signals to be input and output, making it possible to reduce the size and cost of the system compared to conventional systems. Become.

  The video signal compression processing unit 22 of the input board 11 and the video signal expansion processing unit 27 of the output board 12 are respectively provided with compression circuits 22a to 22d and expansion circuits corresponding to a plurality of resolutions (SDTV signal and HDTV signal) of the video signal. 27a to 27d are provided, and among these compression circuits 22a to 22d and expansion circuits 27a to 27, the compression circuit and expansion circuit corresponding to the resolution of the input / output video signal operate, so one input board 11. In the output board 12, video signals of various resolutions to be input / output can be compressed and expanded by compression methods corresponding to the respective resolutions.

  In addition, the audio signal compression processing unit 23 of the input board 11 and the audio signal expansion processing unit 28 of the output board 12 operate with timing pulses of the same frequency when processing either an SDTV signal or an HDTV signal to process the audio signal. Although necessary, the same 27 MHz timing pulse can be supplied to the audio signal compression processing unit 23 and the audio signal expansion processing unit 28 when any of the SDTV signal and HDTV signal is input.

  In the above example, the MPEG2 MP @ ML standard compression / decompression circuits 22a and 27a and the IMX (MPEG2 422P) are used as the compression / decompression circuit of the encoding standard corresponding to the SDTV signal. @ML) standard compression / decompression circuits 22b, 27b and DV standard compression / decompression circuits 22c22b, 27b are provided, and MPEG2 MP @ HL standard expansion is used as a compression / decompression circuit for encoding standards corresponding to HDTV signals. Circuits 22d and 27d are provided. However, as shown in FIG. 13, there are various other encoding standards corresponding to the SDTV signal and HDTV signals. Therefore, the compression / decompression circuit of these standards is connected to the input board 11. The output board 12 may be provided.

  In the above example, the present invention is applied to an AV server that inputs and outputs AV signals in the SDI format. However, the present invention is not limited to this, and the present invention may be applied to an AV server that inputs and outputs AV signals in an SDTI (Serial Data Transport Interface) format, and an AV server that inputs and outputs analog component signals or analog composite signals. When an analog component signal or an analog composite signal is input to an AV server and recorded, for example, a clock having a frequency corresponding to the resolution of the video signal is generated from the synchronization signal added to those signals, and the clock is used as the clock. However, according to the present invention, a clock having a frequency corresponding to a plurality of resolutions of the video signal can be generated from such a synchronization signal within one input board. it can.

  In the above example, the present invention is applied to input / output SDTV signals and HDTV signals with one input board and output board. However, as another example, the present invention may be applied to input / output an NTSC system signal and a PAL system signal with one input board and output board.

  In the above example, the present invention is applied to an AV server used in a broadcasting station or the like. However, the present invention may also be applied to a video recording / reproducing apparatus other than an AV server that has a plurality of input / output units.

It is a block diagram which shows the whole structure of the system which consists of AV server and control terminal to which this invention is applied. It is a block diagram which shows the internal structure of the AV server to which this invention is applied. It is a block diagram which shows the board | substrate which comprises the input / output unit of FIG. It is a block diagram which shows the main circuits on the input board of FIG. 3, and an output board. FIG. 5 is a block diagram illustrating a circuit configuration of an input signal processing unit in FIG. 4. FIG. 5 is a block diagram illustrating a clock system (when an STDV signal is input) of the input signal processing unit of FIG. 4. FIG. 5 is a block diagram showing a configuration of a clock system of the input signal processing unit of FIG. 4 (when an HTDV signal is input). FIG. 5 is a block diagram illustrating a circuit configuration of an output signal processing unit in FIG. 4. FIG. 5 is a block diagram illustrating a clock system (when an STDV signal is output) of the output signal processing unit of FIG. 4. FIG. 5 is a block diagram illustrating a clock system (when outputting an HTDV signal) of the output signal processing unit of FIG. 4. It is a flowchart which shows the process of the main control board at the time of AV signal input, and an input board. It is a flowchart which shows the process of the main control board at the time of AV signal output, and an output board. It is a figure which shows the encoding standard corresponding to an SDTV signal and an HDTV signal.

Explanation of symbols

  1 AV server, 2 control terminal, 4 input / output unit, 5 hard disk unit, 11 input board, 12 output board, 13 main control board, 14 FC board, 15 TG board, 21 input signal processing unit, 22 video signal compression processing unit , 22a to 22d compression circuit, 23 audio signal compression processing unit, 24 recording signal processing unit, 25 recording processing control unit, 26 reproduction signal processing unit, 27 video signal expansion processing unit, 27a to 27d expansion circuit, 28 audio signal expansion processing Unit, 29 output signal processing unit, 30 reproduction processing control unit, 31 SDI receiver, 32 timing generator, 34 SDI decoder, 41 FPGA, 42 PLL, 45 PLL, 48 FPGA interface circuit, 49 flash memory, 5 Frequency divider, 51 frequency divider, 52 PLL, 53 PLL, 54 clock recovery circuit, 55 PLL, 56 PLL, 61 timing generator, 62 SDI encoder, 63 SDI driver, 71 FPGA, 72 PLL, 75 PLL, 77 FPGA Interface circuit, 78 flash memory, 79 frequency divider, 80 frequency divider, 81 PLL, 82 PLL

Claims (18)

A plurality of input units for inputting video signals,
A plurality of output units each outputting a video signal;
A video recording unit that records video signals input to each of the input units, and outputs video signals reproduced from the recording unit from any one of the output units. In the channel compatible video recording and playback device,
The input unit is
A multi-channel characterized in that a circuit for processing a video signal in the input unit includes an input timing pulse generating means for generating and supplying a timing pulse whose frequency is switched according to the resolution of the input video signal. Compatible video recording and playback device. The multi-channel video recording / reproducing apparatus according to claim 1,
The input unit has a plurality of compression circuits of a compression method respectively corresponding to a plurality of resolutions of the video signal as a compression circuit that compresses the input video signal, and the resolution of the input video signal among the plurality of compression circuits Control means for compressing the video signal with a compression circuit corresponding to
The multi-channel video recording / reproducing apparatus, wherein the input timing pulse generating means supplies a timing pulse to the compression circuit. The multi-channel video recording / reproducing apparatus according to claim 1,
The input unit has a circuit for processing an audio signal multiplexed with a video signal,
The multi-channel video recording / reproducing apparatus, wherein the input timing pulse generation means further generates a timing pulse having a frequency corresponding to the audio signal and supplies the timing pulse to the circuit. The multi-channel video recording / reproducing apparatus according to claim 1,
The input unit has a clock extraction means for extracting a clock synchronized with the input video signal,
The input timing pulse generation means includes:
Means for multiplying or dividing the frequency of the reference clock supplied to the video recording / reproducing apparatus according to the resolution of the video signal input to the input unit;
And a means for generating the timing pulse from the clock extracted by the clock extraction means using the multiplied or divided reference clock. The multi-channel video recording / reproducing apparatus according to claim 4,
At least some of the components of the input timing pulse generation means and the clock extraction means are configured by a programmable logic device,
Multi-channel compatible video, wherein the programmable logic device is programmed according to the resolution of the video signal input to the input unit, and the connection relationship between the input timing pulse generating means and the clock extracting means is switched. Recording / playback device. The multi-channel video recording / reproducing apparatus according to claim 1,
The output unit is
A circuit for processing the video signal in the output unit includes an output timing pulse generation unit that generates and supplies a timing pulse whose frequency is switched according to the resolution of the video signal reproduced from the recording unit. Multi-channel compatible video recording / playback device. The multi-channel video recording / reproducing apparatus according to claim 6,
The output unit has a plurality of decompression circuits of a compression method respectively corresponding to a plurality of resolutions of a video signal as a decompression circuit that decompresses the compressed video data reproduced from the recording unit, and among the plurality of decompression circuits It has a control means for decompressing the compressed video data by the decompression circuit corresponding to the resolution of the video signal to be output,
The multi-channel video recording / reproducing apparatus, wherein the output timing pulse generating means supplies a timing pulse to the expansion circuit. The multi-channel video recording / reproducing apparatus according to claim 6,
The output unit has a circuit for processing an audio signal reproduced from the recording unit,
The multi-channel video recording / reproducing apparatus, wherein the output timing pulse generating means further generates a timing pulse having a frequency corresponding to the audio signal and supplies the timing pulse to the circuit. The multi-channel video recording / reproducing apparatus according to claim 6,
The output timing pulse generation means includes:
Means for multiplying or dividing the frequency of a reference clock supplied to the video recording / reproducing apparatus according to the resolution of the video signal reproduced from the recording unit;
And a means for generating the timing pulse from the multiplied or frequency-divided reference clock. The multi-channel video recording / reproducing apparatus according to claim 9,
A multi-channel video recording / reproducing apparatus, wherein at least a part of the constituent elements of the output timing pulse generating means is a programmable logic device. A plurality of video input devices for inputting video signals,
A plurality of video output devices each outputting a video signal;
A recording device for recording a video signal, recording the video signal input to each of the video input devices to the recording device, and outputting the video signal reproduced from the recording device from any of the video output devices In the video input device for configuring the multi-channel compatible video recording / playback system,
As a compression circuit for compressing the input video signal, it has a plurality of compression circuits of a compression method respectively corresponding to a plurality of resolutions of the video signal,
Control means for compressing the video signal with a compression circuit corresponding to the resolution of the input video signal among the plurality of compression circuits;
A video input device comprising: timing pulse generation means for generating a timing pulse to be supplied to the compression circuit by switching a frequency according to the resolution of an input video signal. The video input device according to claim 11,
A circuit for processing an audio signal multiplexed with the video signal;
The video input device, wherein the timing pulse generation means further generates a timing pulse having a frequency corresponding to the audio signal and supplies the timing pulse to the circuit. The video input device according to claim 11,
A clock extracting means for extracting a clock synchronized with the input video signal;
The timing pulse generating means includes
Means for multiplying or dividing the frequency of a reference clock supplied to the video recording / reproducing apparatus in accordance with the resolution of an input video signal;
And a means for generating the timing pulse from the clock extracted by the clock extraction means using the multiplied or divided reference clock. The video input device according to claim 13.
At least some of the components of the input timing pulse generation means and the clock extraction means are configured by a programmable logic device,
A video input device, wherein the programmable logic device is programmed in accordance with the resolution of a video signal input to the input unit, and the connection relationship between the input timing pulse generation means and the clock extraction means is switched. A plurality of video input devices for inputting video signals,
A plurality of video output devices each outputting a video signal;
A recording device for recording a video signal, recording the video signal input to each of the video input devices to the recording device, and outputting the video signal reproduced from the recording device from any of the video output devices In the video output device for configuring the multi-channel video recording / playback system,
As a decompression circuit for decompressing the compressed video data reproduced from the recording device, a plurality of decompression circuits of a compression method respectively corresponding to a plurality of resolutions of the video signal are provided.
Control means for decompressing the compressed video data with a decompression circuit corresponding to the resolution of the video signal to be output among the plurality of decompression circuits;
A video output device comprising: timing pulse generation means for generating a timing pulse to be supplied to the decompression circuit by switching a frequency in accordance with a resolution of compressed video data reproduced from the recording device. The video output device according to claim 15, wherein
A circuit for processing an audio signal reproduced from the recording device;
The video output device, wherein the timing pulse generation means further generates a timing pulse having a frequency corresponding to the audio signal and supplies the timing pulse to the circuit. The video output device according to claim 15, wherein
The timing pulse generating means includes
Means for multiplying or dividing the frequency of a reference clock supplied to the video recording / reproducing device in accordance with the resolution of the video signal reproduced from the recording device;
And a means for generating the timing pulse from the multiplied or divided reference clock. The video output device according to claim 17.
An image output apparatus characterized in that at least a part of the components of the timing pulse generating means is configured by a programmable logic device.

Images