JP2006294992A - Capacitor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems: in the crown-like capacitance used for the DRAM, the solution etching the insulating film of the outside wall periphery of a lower electrode after forming the lower electrode on an inner wall of a deep hole formed in a thick insulating film leaves the lower electrode in destruction with the surface tension of the solution or an unexpected etching caused by the solution penetration to cause a pair-bit-defect. <P>SOLUTION: A silicon nitride film having a thickness of at least not less than three times of that of the lower electrode is provided on the interlayer insulating film with a plug formed, after patterning the silicon nitride film in a line shape in some cases, the deep hole is formed by depositing the thick insulating film. After that, by laterally retreating the side wall of the insulating film in the hole, the lower electrode is formed with a part of the surface of the silicon nitride film exposed and a stand formed. The lower electrode formed jutting out the surface of the silicon nitride film improves a mechanical strength to prevent the destruction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a capacitor constituting a DRAM and a method for manufacturing the same, and more particularly to a capacitor structure suitable for avoiding a problem that the lower electrode collapses when a crown-shaped lower electrode is formed and a method for manufacturing the same.

  In recent years, the capacity of semiconductor devices has been increased, and in particular, DRAM (Dynamic Random Access Memory) has been commercialized as a gigabit class memory having a minimum processing dimension of 100 nm, and a DRAM corresponding to a minimum processing dimension of 90 nm or more. Development is underway. Along with such miniaturization of elements, the plane area allowed for the capacitor, which is a main component of the DRAM, is inevitably reduced, and it has become difficult to secure a desired capacity. Under such circumstances, the structure generally used in the conventional deep hole stacked capacitor is that a lower electrode made of silicon having an uneven surface (HSG: Hemispherical Silicon Grain) has a depth of about 2000 nm. A dielectric and an upper electrode are formed on the inner surface of the deep hole. The HSG is formed for the purpose of increasing the surface area of the electrode in order to secure the capacitance of the capacitor. This HSG has a height of about 80 nm from the bottom of the silicon electrode, that is, from the side wall of the deep hole to the top of the HSG. In the case where the short side of the deep hole has a relatively wide short side of, for example, 250 nm, even if the HSG is formed, it is 80 nm from both sides and only 160 nm is occupied in total, so the remaining central space short side is 90 nm. If 90 nm can be secured, it is sufficiently possible to form a dielectric and an upper electrode thereon.

  However, when the miniaturization of the DRAM further progresses and the short side becomes about 200 nm, the short side of the central space remaining after the formation of HSG becomes 40 nm, and the coverage to the bottom is secured in the deep hole. Therefore, it becomes difficult to form a dielectric and an upper electrode. In particular, securing the dielectric coverage is an essential requirement for maintaining the charge retention function of the DRAM. If the coverage is poor, that is, if there is a portion where the film thickness is thin, there is a problem that the leakage current increases in that portion and charge cannot be accumulated. For this reason, even if the holes are miniaturized, a space for securing the dielectric coverage is required, and it becomes extremely difficult to apply HSG that narrows the space.

 In order to overcome the above-described difficulties, a capacitor having a crown structure in which inner and outer walls of a lower electrode formed in a deep hole are exposed and both side surfaces are used as a capacitor has been studied. In the crown type structure, the capacitor area can be secured approximately twice that when only the inner wall is used, so that the same capacity as when HSG is used can be ensured without using HSG. Since HSG is not used, a space margin can be secured, the dielectric and the upper electrode can be easily formed, and the capacitor can be improved in reliability.

However, the above-mentioned crown type structure has the following problems. The problem will be described with reference to FIGS. 2 (a), 2 (b), and 2 (c) schematically showing the manufacturing process of the crown structure.
First, as shown in FIG. 2A, after a silicon plug 203 is formed in a predetermined region of the first interlayer insulating film 201 and the silicon nitride film 202, a second interlayer insulating film made of a thick silicon oxide film is formed. accumulate. Next, as shown in FIG. 2B, a deep hole 205 is formed by lithography and dry etching to expose the silicon plug, and then a lower electrode 206 is formed on the inner wall of the deep hole. Thereafter, as shown in FIG. 2C, the second interlayer insulating film 204 that has been supported around the outer wall of the lower electrode 206 is removed with a hydrofluoric acid solution. When the thick silicon oxide is removed by this hydrofluoric acid solution, the lower electrode loses its support and the mechanical strength is remarkably reduced. Therefore, the lower electrode collapses due to the surface tension of the solution, and the adjacent lower electrode comes into contact with each other to cause a bad pair bit. Bring. It is effective if the silicon oxide can be removed by dry etching that does not cause surface tension, but at present, it is difficult and practical to remove only the silicon oxide without impairing the shape of the lower electrode.

  In order to avoid the above-mentioned pair bit failure, Japanese Patent Application Laid-Open No. 2003-224210 discloses a structure in which etching of the interlayer insulating film is stopped halfway so that the entire outer wall is not exposed, leaving the lower half interlayer insulating film. A capacitor is disclosed. The capacitor structure disclosed herein is effective in preventing the lower electrode from collapsing. However, there is a problem that the area of the capacitor is reduced by the amount of the region remaining as a support for the originally intended increase in capacitance.

  In Japanese Patent Laid-Open Nos. 2003-142605 and 2003-297952, the mechanical strength is increased by connecting and supporting each other with an insulator beam at an arbitrary height above the capacitor lower electrode. A structure for preventing collapse is disclosed. However, since the insulator used for semiconductor manufacture has its own stress, there is a problem that the insulator itself is deformed as soon as the contacting object disappears. Since the stress changes depending on the length of the beam, the positional relationship between the capacitors is restricted. Further, since there is no adjacent capacitor in the capacitor located on the outermost periphery of the memory cell region, it cannot be connected and supported, and there is still a fear of collapse.

JP 2003-224210 A JP 2003-142605 A JP 2003-297852 A

  As described above, when the lower electrode of the crown type structure is formed, the insulating film around the outer wall that has supported the lower electrode must be removed by wet etching using a solution. Unexpected etching due to soaking occurs and the lower electrode collapses. The collapse of the lower electrode causes a contact short circuit between adjacent capacitors, resulting in a defective pair bit, and independent control in units of bits becomes impossible, thus hindering DRAM operation.

If removal by a solution is not used, the above problem can be avoided, but it is practically difficult to remove a thick oxide film by a dry etching method without causing problems such as damage to the shape of the lower electrode. Therefore, there is a demand for a structure and manufacturing method for a lower electrode that does not collapse even when solution etching is used to form a lower electrode having a crown structure.
In view of the above problems, an object of the present invention is to provide a DRAM having a highly reliable capacitor by avoiding a pair bit failure without causing a lower electrode to collapse even if a crown structure is formed by using solution etching. There is.

  In order to achieve the above object, a capacitor according to the present invention includes a conductive plug provided in an interlayer insulating film on a semiconductor substrate, and a crown-type lower electrode in contact with the conductive plug, and the conductive plug is provided in the capacitor. A silicon nitride film having a thickness of at least three times the thickness of the lower electrode on at least a part of a region of the interlayer insulating film surface where the bottom of the lower electrode is not in contact with the conductive plug; The bottom surface of the lower electrode is formed so as to protrude from the first bottom surface that is in contact with the conductive plug and at least partially surrounded by the silicon nitride film, and on the surface of the silicon nitride film that surrounds at least part of the first bottom surface. It is characterized by comprising a second bottom surface.

  The capacitor manufacturing method according to the present invention is a method for manufacturing a capacitor having a conductive plug formed in a first interlayer insulating film on a semiconductor substrate and a crown-shaped lower electrode connected to the conductive plug, Depositing a silicon nitride film having a thickness of at least three times the thickness of the lower electrode on the first interlayer insulating film on which the conductive plug is formed; and a second interlayer insulating film on the silicon nitride film. Depositing a film; forming a deep hole through the second interlayer insulating film and the silicon nitride film to expose the surface of the conductive plug; and a second interlayer insulating film constituting a sidewall of the deep hole And a step of retreating a side wall of the second interlayer insulating film of the silicon nitride film to expose a part of the surface of the silicon nitride film, and a step of retreating the second interlayer insulating film and the part of the surface of the silicon nitride film that are retreated. Exposed Forming a lower electrode on the inner wall of the deep hole made of a silicon nitride film; removing the second interlayer insulating film; exposing an outer wall of the lower electrode; forming a crown-shaped lower electrode; and the crown-shaped lower electrode The method includes a step of forming a dielectric on the top and a step of forming an upper electrode on the dielectric.

  The capacitor manufacturing method according to the present invention is a method for manufacturing a capacitor having a conductive plug formed in a first interlayer insulating film on a semiconductor substrate and a crown-shaped lower electrode connected to the conductive plug, Depositing a silicon nitride film having a thickness of at least three times the thickness of the lower electrode on the first interlayer insulating film on which the conductive plug is formed; and a second interlayer on the silicon nitride film. Depositing an insulating film; depositing a third interlayer insulating film having a wet etching rate slower than the second interlayer insulating film on the second interlayer insulating film; and Forming a deep hole through the interlayer insulating film and the silicon nitride film and exposing the surface of the conductive plug; and a third interlayer insulating film, a second interlayer insulating film and a silicon nitride film constituting the sidewall of the deep hole Of which, the second layer Retreating the sidewall of the insulating film to expose a part of the surface of the silicon nitride film; and nitriding the third interlayer insulating film, the second interlayer insulating film with the sidewall retreated and the part of the surface exposed Forming a lower electrode on a deep hole inner wall made of a silicon film, removing the third interlayer insulating film and the second interlayer insulating film, exposing an outer wall of the lower electrode, and forming a crown-shaped lower electrode; The method includes a step of forming a dielectric on the crown-shaped lower electrode and a step of forming an upper electrode on the dielectric.

  Furthermore, the method for manufacturing a capacitor according to the present invention is a method for manufacturing a capacitor having a conductive plug formed in a first interlayer insulating film on a semiconductor substrate, and a crown-shaped lower electrode connected to the conductive plug, Depositing a first silicon nitride film having a thickness of at least three times the thickness of the lower electrode on the second interlayer insulating film on which the conductive plug is formed; and covering the conductive plug so as to cover the conductive plug A step of patterning the first silicon nitride film into a desired shape; a step of depositing a second silicon nitride film over the entire surface; and depositing a second interlayer insulating film on the second silicon nitride film to flatten the surface. A step of depositing a third interlayer insulating film having a wet etching rate slower than that of the second interlayer insulating film on the second interlayer insulating film having a planarized surface, and the third interlayer insulating film. , Second interlayer insulating film, second Forming a deep hole through the silicon nitride film and the patterned first silicon nitride film, exposing the surface of the conductive plug, and a second interlayer insulating film forming a part of a side wall of the deep hole Retreating the side wall of the second silicon nitride film to expose a partial surface of the second silicon nitride film, the third interlayer insulating film, the second interlayer insulating film having the side wall retreated, and the second nitride having the partially exposed surface Forming a lower electrode on the inner wall of the deep hole comprising the silicon film and the patterned first silicon nitride film; removing the third interlayer insulating film and the second interlayer insulating film; and exposing the outer wall of the lower electrode And a step of forming a crown-type lower electrode, a step of forming a dielectric on the crown-type lower electrode, and a step of forming an upper electrode on the dielectric.

  In the capacitor of the present invention, a silicon nitride film at least three times the thickness of the lower electrode is provided at the bottom of the deep hole, and a pedestal composed of a side wall of the silicon nitride film and a partial upper surface of the silicon nitride film is formed in advance. The lower electrode is formed in the state. As a result, the bottom surface of the lower electrode protrudes over the surface of the first bottom surface that is in contact with the conductive plug and at least partially surrounded by the silicon nitride film, and the surface of the silicon nitride film that surrounds at least part of the first bottom surface. And a second bottom surface formed. Therefore, since the lower electrode itself is in contact with the upper surface of the silicon nitride film in addition to the side wall of the silicon nitride film, the mechanical strength can be improved against the force applied in the lateral direction and the collapse can be prevented. Can do. In addition, since silicon nitride is formed with a thickness of three times or more the thickness of the lower electrode, the contact length between the silicon nitride and the lower electrode can be increased, and the solution penetrates from the interface so that the lower layer silicon oxide Problems caused by unexpected etching can be avoided. Further, the silicon nitride film may be patterned. In this case, the patterned silicon nitride is formed so as to bite into the deep hole, so that not only the upper surface of the bitten silicon nitride but also the side surface of the pattern is formed by the lower electrode. It can be set as the structure enclosed, and mechanical strength can be improved more.

Further, in the capacitor according to the present invention, it is possible to prevent the collapse by using the silicon nitride film alone, so that it is not necessary to form another film thickly to support it, and the outer wall of the lower electrode can be used effectively as a capacitor, which is effective in increasing the capacity. is there.
Furthermore, in the capacitor of the present invention, since the structure for preventing the collapse is applied to each lower electrode itself, there is no need for the connection support as in the above-mentioned patent document, and the problem newly generated in the connection support structure is avoided. In addition, the capacitor located on the outermost periphery of the memory cell region can be effectively prevented from collapsing.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

First, the structure of a DRAM using the capacitor of the present invention will be described with reference to the schematic cross-sectional view of FIG.
The p-type silicon substrate 101 is provided with an n-well 102 and a first p-well 103 therein. A second p well 104 is provided in a region other than the n well 102, and an element isolation region 105 is provided for element isolation. For convenience, the first p-well 103 shows a memory array region in which a plurality of memory cells are arranged, and the second p-well 104 shows a peripheral circuit region.
The first p-well 103 is provided with switching transistors 106 and 107 serving as word lines as constituent elements of individual memory cells. The transistor 106 includes a gate electrode 111 through a drain 108, a source 109, and a gate insulating film 110. The transistor 107 has a common source 109 and a gate electrode 111 through a drain 112 and a gate insulating film 110. An interlayer insulating film 113 is provided so as to cover the transistor.

A contact hole 114 is provided in a predetermined region of the interlayer insulating film 113 to constitute a bit line contact made of polycrystalline silicon 115, titanium silicide 116, titanium nitride 117 and tungsten 118. A bit line made of tungsten nitride 119 and tungsten 120 is provided so as to be connected to the bit line contact. A first interlayer insulating film 121 is provided so as to cover the bit line.
Contact holes are formed in predetermined regions of the interlayer insulating film 113 and the first interlayer insulating film 121 so as to be connected to the drains 108 and 112 of the transistor, and then filled with silicon, and a silicon plug 122 is provided.

A capacitor is provided so as to be connected to the silicon plug 122. The bottom of the capacitor lower electrode 126 is located on a first bottom surface in contact with the silicon plug 122 and a 300 nm thick silicon nitride film 123 provided on the surface of the first interlayer insulating film 121 in a region other than the first bottom surface. A second bottom surface. The first bottom surface and the side wall adjacent to the first bottom surface are surrounded by the silicon nitride film 123, and the second bottom surface is configured to protrude from the surface of the silicon nitride film using the silicon nitride film 123 as a pedestal. . The lower electrode 126 has a crown structure with the inner and outer walls exposed. A capacitor dielectric 127 and an upper electrode 128 are provided on the lower electrode to constitute a capacitor.
Further, when the crown structure is formed, a dummy groove 129 adjacent to the peripheral circuit region is provided so as to surround the memory cell region so that the interlayer insulating film in the peripheral circuit portion is not etched by the solution. The dummy groove 129 is not connected to the silicon plug 122. A fourth interlayer insulating film 130 is provided so as to cover the capacitor.

  On the other hand, the second p-well 104 is provided with a transistor constituting a peripheral circuit, and includes a source 109, a drain 112, a gate insulating film 110, and a gate electrode 111. A contact hole 131 is provided in a predetermined region of the interlayer insulating film 113 so as to be connected to the drain 112, and a contact plug made of titanium silicide 116, titanium nitride 117, and tungsten 118 is formed. Further, a first wiring layer made of tungsten nitride 119 and tungsten 120 is provided so as to be connected to the contact plug. A part of the first wiring layer is a contact provided through the first interlayer insulating film 121, the silicon nitride 123, the second interlayer insulating film 124, the third interlayer insulating film 125, and the fourth interlayer insulating film 130. It is connected to a second wiring layer made of titanium nitride 135, aluminum 136, and titanium nitride 137 through a plug made of titanium nitride 133 and tungsten 134 filling the hole 132.

  In addition, the upper electrode 128 of the capacitor provided in the memory array region is led out as a lead-out wiring 138 in the peripheral circuit region in a part of the region. Then, a second wiring layer made of titanium nitride 141, aluminum 142, and titanium nitride 143 is formed through titanium nitride 139 and tungsten 140 filling contact holes formed in a predetermined region of the fourth interlayer insulating film 130. Connected. Hereinafter, if necessary, an upper wiring layer is provided to constitute a DRAM.

In the second embodiment, a method for manufacturing a capacitor of the present invention will be described with reference to a series of process cross-sectional views of FIGS.
First, as shown in FIG. 3A, deep holes were formed. First, a silicon plug 302 was formed in a predetermined region of the first interlayer insulating film 301 by a known method. Thereafter, a silicon nitride film 303 having a thickness of 300 nm was deposited. The silicon nitride film was formed by a thermal CVD (Chemical Vapor Deposition) method. It can also be formed by plasma CVD instead of thermal CVD. A silicon nitride film formed by thermal CVD and a silicon nitride film formed by plasma CVD have internal stresses that are opposite to each other. Stress can be offset.

  After depositing the silicon nitride film 303, a second interlayer insulating film 304 made of a silicon oxide film having a thickness of 1700 nm was deposited by plasma CVD. Thereafter, deep holes 305 were formed using lithography and dry etching. At this time, since the photoresist has insufficient resistance as a mask for dry etching, amorphous carbon was used as a hard mask (not shown in the figure). Specifically, after depositing the second interlayer insulating film 304, amorphous carbon having a film thickness of 500 nm was further deposited to form a predetermined photoresist pattern. The pattern was once transferred to amorphous carbon using the photoresist as a mask. Thereafter, the second interlayer insulating film 304 and the silicon nitride film 303 were anisotropically dry etched using amorphous carbon as a mask to form deep holes 305. As a hard mask, a silicon film can be used instead of amorphous carbon.

  Next, as shown in FIG. 3B, a pedestal 306 was formed on the silicon nitride film 303. After forming the deep hole 305, the second interlayer insulating film 304 was etched with a hydrofluoric acid (HF) -containing solution to retract the side wall by 50 nm. As the second interlayer insulating film 304 recedes, a part of the upper surface of the silicon nitride 303 is exposed. As a result, a base 306 of the silicon nitride film 303 indicated by a circle is formed.

  Next, as shown in FIG.3 (c), the lower electrode 307 was formed in the deep hole inner wall. First, after removing the natural oxide film on the exposed silicon plug surface, polycrystalline silicon containing phosphorous and having a thickness of 40 nm was deposited on the entire surface by a well-known CVD method. Next, the deep hole was filled with photoresist, and the polycrystalline silicon exposed on the surface was etched back and removed. Thereafter, the photoresist filled with the deep holes was removed with oxygen plasma to form the lower electrode 307. As a result, the lower electrode 307 has a first bottom surface 308 that is in contact with the silicon plug 302 and a second bottom surface 309 that is located on the surface of the base 306 of the silicon nitride film 303, and is in contact with the side wall and part of the top surface of the silicon nitride film. Due to the structure, the mechanical strength against collapse increases. Further, the inner diameter of the first bottom surface 308 is formed to be smaller than the inner diameter of the second bottom surface 309.

Next, as shown in FIG. 3D, the dielectric 310 and the upper electrode 311 were formed. First, after forming the lower electrode 307 on the inner wall of the deep hole, the second interlayer insulating film 304 around the outer wall of the lower electrode was removed with an HF-containing solution. Since the thickness of the second interlayer insulating film is 1700 nm, it can be removed in about 15 minutes using a 10% HF aqueous solution. A buffered HF solution mixed with ammonium fluoride (NH4F) may be used. The etching rate can be arbitrarily controlled by adjusting their mixing ratio.
After removing the second interlayer insulating film to form a crown-shaped lower electrode having a structure fitted in the silicon nitride film 303, a dielectric 310 was formed on the entire surface.

Here, tantalum oxide is used for the dielectric 310. Tantalum oxide was formed by the following method. First, before forming tantalum oxide, silicon nitride of about 1 nm was previously formed on the surface of the lower electrode made of polycrystalline silicon from which the natural oxide film had been removed by a known thermal nitriding method or the like. Next, tantalum oxide having a thickness of 9 nm was deposited by a CVD method using pentaethoxytantalum (PET: Ta (OC2H5) 5) and oxygen as source gases. Next, heat treatment was performed in an N2O atmosphere to crystallize tantalum oxide.
Further, instead of tantalum oxide, an aluminum oxide single layer film, a laminated film of aluminum oxide and hafnium oxide, or the like can be used. For example, in the case of aluminum oxide, it can be formed by atomic layer deposition at about 350 ° C. using trimethylaluminum (TMA: Al (CH 3) 3) and H 2 O as source gases. Similarly, tantalum oxide and hafnium oxide can be formed using a known atomic layer deposition method. In the case of forming the dielectric by the atomic layer deposition method, the temperature at the time of forming the dielectric can be lowered and the oxidation of the lower electrode can be suppressed, so that a metal such as titanium nitride or tungsten can be used as the lower electrode. .

  On the other hand, the upper electrode 311 is made of titanium nitride. Titanium nitride was formed by the usual CVD method using titanium chloride (TiCl4) and ammonia (NH3) as raw materials. Titanium nitride can also be formed using atomic layer deposition. Alternatively, tungsten or the like may be laminated on titanium nitride by a sputtering method to a thickness of about 200 nm to ensure the thickness, thereby reducing the resistance of the upper electrode.

  According to the present embodiment, after the deep hole is formed, the second interlayer insulating film 304 is retracted in the lateral direction to expose a part of the upper surface of the silicon nitride film 303, and the base 306 of the silicon nitride film is formed. Since the lower electrode is formed, the lower electrode has a structure in contact with the side surface and part of the upper surface of the silicon nitride, and the mechanical strength can be increased. As a result, the lower electrode can be prevented from collapsing even if solution etching is performed to form a crown structure.

In this embodiment, in the case of performing the etching with the HF-containing solution in the stage of FIG. 3B, if the second interlayer insulating film 304 and the first interlayer insulating film 301 are made of similar materials, During the solution etching of the two interlayer insulating film, the first interlayer insulating film is similarly etched. The etching of 50 nm used in this embodiment is not substantially a problem, but when the first interlayer insulating film 301 is etched and becomes a problem, the etching rate of the material can be changed. When the first interlayer insulating film is silicon oxide, phosphorus-containing silicon oxide (PSG: Phospho Silicate Glass) or BPSG (Boro-Phospho Silicate Glass) further containing boron is used for the second interlayer insulating film. Since these materials have a higher etching rate with the HF-containing solution than silicon oxide, as a result, the etching amount of the first interlayer insulating film 301 can be reduced to half or less.
Further, as shown in the prior art of FIG. 2, if it is made of a material such as crystallized tantalum oxide instead of silicon nitride formed on the first interlayer insulating film, the first interlayer The insulating film can be protected from solution etching.

In the above embodiment, after forming the deep hole, the entire second interlayer insulating film is retracted. However, when the depth of the deep hole becomes deeper, it becomes difficult to retract the entire side wall of the deep hole due to the bowing phenomenon. There is. Boeing is a phenomenon in which a portion slightly below the deep hole opening is excessively etched in the lateral direction, and the hole width at that position widens. Therefore, before the solution etching, the width of the insulating film between the adjacent deep holes has already narrowed, and it is difficult to etch back.
In the third embodiment, a method for retracting only a part of the deep hole will be described with reference to a series of process sectional views of FIGS.

  First, as shown in FIG. 4A, a deep hole 406 was formed. After a silicon plug 402 is formed in a predetermined region of the first interlayer insulating film 401 made of silicon oxide, a silicon nitride film 403 having a thickness of 300 nm, a second interlayer insulating film 404 made of PSG having a thickness of 300 nm, and a thickness of 1700 nm. A third interlayer insulating film 405 made of silicon oxide was deposited. Deep holes 406 were formed at predetermined positions by lithography and dry etching. A hard mask was used for dry etching as in the previous example. As shown in the figure, when the depth of the deep hole becomes deep, the cross-sectional shape of the entire deep hole becomes a mortar shape, and the inner diameter of the hole bottom becomes narrower than the upper opening of the deep hole. Although not shown in detail in the drawing, due to the bowing phenomenon, the inner diameter of the region about 500 nm below the deep hole opening is the largest.

  Next, as shown in FIG. 4B, a base 407 was formed on the silicon nitride film 403. Etching was performed using a 1% HF aqueous solution so that the side wall of the second interlayer insulating film made of PSG receded by 50 nm. As a result, a part of the upper surface of the silicon nitride 403 is exposed and a pedestal 407 is formed. At this time, the third interlayer insulating film and the first interlayer insulating film recede only about 20 nm. By adjusting the phosphorus concentration in PSG, the amount of retreat can be further controlled.

Next, as shown in FIG. 4C, the lower electrode 408 was formed. After removing the natural oxide film on the surface of the silicon plug, a lower electrode 408 made of polycrystalline silicon having a thickness of 40 nm was formed in the same manner as in Example 1 on the inner wall of the deep hole in which the base 407 of the silicon nitride film 403 was formed. .
Further, as shown in FIG. 4D, a capacitor is formed by forming a dielectric 409 and an upper electrode 410 made of titanium nitride.

  According to the present embodiment, the second interlayer insulating film having a high etching rate with the HF-containing solution is provided immediately above the silicon nitride film, and the side walls of the second interlayer insulating film are selectively etched. As a result, the etching amount of the third interlayer insulating film and the first interlayer insulating film can be kept small, and the insulating film can be effectively retreated only in a deep region where the influence is not affected even if the deep hole is bowed. There is an effect that the mechanical strength of the lower electrode can be improved.

In the second and third embodiments, silicon nitride is formed so as to surround the entire periphery of the lower electrode. However, in the fourth embodiment, an example in which only a part of the outer periphery of the lower electrode is surrounded is shown in FIGS. A series of process cross-sectional views of (l) ((b) and (g) are plan views) and a plan view of FIG.
First, as shown in FIG. 5A, a first silicon nitride film 503 having a thickness of 300 nm was formed on the first interlayer insulating film 501 on which the silicon plug 502 was formed.

  Next, the silicon nitride film 503 was patterned by lithography and dry etching. FIG. 5B shows a plan view after the first silicon nitride film 503 is patterned. A silicon nitride film was patterned in a line shape so as to cover the silicon plug 502. For convenience, the silicon plug is shown to be seen through.

In the following description, the cross-section in the XX ′ direction and the cross-section in the YY ′ direction in the plan view of FIG.
FIGS. 5C-1 and 5C-2 respectively correspond to the XX′-direction section and the YY′-direction section in the plan view of FIG. 5B.

  Next, as shown in FIGS. 5D-1 and 5D-2, a second silicon nitride film 504 having a thickness of 50 nm was deposited on the entire surface. Next, as shown in FIGS. 5E-1 and 5E-2, a second interlayer insulating film 505 made of BPSG is deposited to 600 nm, and the surface is flattened by reflow and CMP (Chemical Mechanical Polishing). Thereafter, a third interlayer insulating film 506 made of a silicon oxide film having a thickness of 1400 nm was deposited.

  Next, as shown in FIGS. 5F-1 and 5F-2, the third interlayer insulating film 506, the second interlayer insulating film 505, the second silicon nitride film 504, and the first silicon nitride film 503 are formed. Deep holes 507 were formed at predetermined positions. Plan views in this state are shown in FIGS. 5 (g-1) and (g-2). The ellipse indicated by the deep hole 507 represents the planar shape of the deep hole. There is no silicon nitride film in the deep hole, and the silicon plug 502 is exposed. Further, since the first silicon nitride film 503 is patterned, the first silicon nitride film 503 is in contact with only the short side of the deep hole and does not surround the entire circumference.

  Next, as shown in FIGS. 5 (h-1) and 5 (h-2), the side wall of the second interlayer insulating film 505 is selectively etched back with an HF-containing solution so that a part of the silicon nitride film is removed. The surface was exposed. At this time, in FIG. (H-1), only a part of the upper surface of the second silicon nitride film 504 having a thickness of 50 nm is exposed, but in FIG. (H-2), it is caused by the line pattern of the first silicon nitride film 503. As a result, part of the upper surface and part of the side surface are exposed. As a result, in the same manner as in the previous embodiment, in addition to the pedestal facing from the upper surface to the center side of the deep hole, a pedestal extending from the upper surface to both side surfaces is newly formed, and a pedestal 508 facing in three directions is formed.

  Next, as shown in FIGS. 5 (i-1) and (i-2), a lower electrode 509 was formed on the inner wall of the deep hole. As a result, the lower electrode 509 has a first bottom surface 510 in contact with the silicon plug 502 and a second bottom surface 511 positioned on the surface of the base 508 of the second silicon nitride film 504. Therefore, the mechanical strength against collapse increases.

Further, as shown in FIGS. 5 (j-1) and (j-2), the third interlayer insulating film 506 and the second interlayer insulating film 505 were removed with an HF-containing solution. Thereafter, as shown in FIGS. 5 (k-1) and (k-2), a dielectric 512 made of aluminum oxide was formed. Next, as shown in FIGS. 5 (l-1) and (l-2), an upper electrode 513 made of titanium nitride was deposited to form a capacitor.
FIG. 6 schematically shows a plan view of the finished cross-sectional view shown in FIG. It can be seen that the lower electrode 602 is formed so as to cover the side surface of the line-shaped silicon nitride film 601 protruding into the deep hole.

According to the present embodiment, by retracting the second interlayer insulating film, the three-dimensional line pattern of the silicon nitride film protrudes into the deep hole, and a part of the upper surface and a part of the side surface are exposed. As a result, in the same way as the previous embodiment, in addition to the pedestal facing from the upper surface to the deep hole center side, a pedestal extending from the upper surface to both side surfaces is newly formed, and a pedestal facing in three directions can be configured. As a result, since the lower electrode is formed so as to cover the upper surface and the three side surfaces of the protruding silicon nitride film, there is an effect that the mechanical strength can be improved against the force applied from any direction.
Further, according to the present embodiment, even when the deep hole has a mortar shape, the mortar-shaped portion is selectively retracted to form a silicon nitride pedestal as a measure for increasing the mechanical strength of the lower electrode. As a result, there is an effect that the capacitor area is increased and the capacitance can be increased.

  FIG. 7 shows a modification of the fourth embodiment. The silicon nitride is projected from two directions intersecting the deep hole at right angles with the silicon plug as the center. The protruding portion of silicon nitride is composed of four locations, and the mechanical strength can be further improved. In addition, although the example in the case where the deep holes are laid out by shifting in parallel on a straight line has been described here, the present invention is not limited to this, and no matter how the layout is made, the silicon plug is the center. A silicon nitride pattern may be formed so as to be optimal for each deep hole.

  As described above, according to the present invention, the bottom of the deep hole is provided with a silicon nitride film at least three times the thickness of the lower electrode, and is composed of the side wall of the silicon nitride film and the partial surface of the silicon nitride film. The lower electrode is formed with the pedestal previously formed. As a result, the bottom surface of the lower electrode protrudes over the surface of the first bottom surface that is in contact with the conductive plug and at least partially surrounded by the silicon nitride film, and the surface of the silicon nitride film that surrounds at least part of the first bottom surface. And a second bottom surface formed. Accordingly, since the lower electrode itself is in contact with the upper surface of the silicon nitride in addition to the side wall of the silicon nitride, the mechanical strength can be improved against the force applied in the lateral direction, and the collapse can be prevented. it can.

In addition, since the silicon nitride is formed in a single layer with a thickness of three times or more the thickness of the lower electrode, the contact length between the silicon nitride and the lower electrode can be increased, and the solution soaks from the interface and penetrates the lower layer. Problems caused by inadvertently etching the silicon oxide can be avoided.
In addition, since the collapse of the silicon nitride film can be prevented, it is not necessary to form another film thickly to support it, and the outer wall of the lower electrode can be used effectively as a capacitor, which is effective in increasing the capacity.
Furthermore, since the structure for preventing the collapse is applied to the individual lower electrodes themselves, there is no need to support the connection between the lower electrodes, a problem newly generated in the connection support structure can be avoided, and the outermost periphery of the memory cell region can be avoided. Even in the capacitor located, the collapse can be effectively prevented.

Sectional drawing for demonstrating the 1st Example of this invention. A series of process sectional views showing a conventional problem. A series of process sectional views for explaining the second example of the present invention. The series of process sectional drawing for demonstrating the 3rd Example of this invention. A series of process sectional views for explaining the 4th example of the present invention. A series of process sectional views for explaining the 4th example of the present invention. A series of process sectional views for explaining the 4th example of the present invention. A series of process sectional views for explaining the 4th example of the present invention. A series of process sectional views for explaining the 4th example of the present invention. The top view for demonstrating the 4th Example of this invention. The top view for demonstrating the 5th Example of this invention.

Explanation of symbols

101 Silicon substrate 102 n-well 103 first p-well 104 second p-well 105 element isolation region 106, 107 transistor 108, 112 drain 109 source 110 gate insulating film 111 gate electrode 113 interlayer insulating film 114, 131, 132 contact hole 115 Polycrystalline silicon 116 Titanium silicide 117, 133, 135, 137, 139, 141, 143 Titanium nitride 118, 120, 134, 140 Tungsten 119 Tungsten nitride 121, 201, 301, 401, 501 First interlayer insulating film 122, 203, 302, 402, 502 Silicon plug 123, 202, 303, 403, 601, 701 Silicon nitride film 124, 204, 304, 404, 505 Second interlayer insulating film 125, 405, 506 Third interlayer insulation Edge film 126, 206, 307, 408, 509, 602, 702 Lower electrode 127, 310, 409, 512 Dielectric 128, 311, 410, 513 Upper electrode 129 Dummy groove 130 Fourth interlayer insulating film 136, 142 Aluminum 138 Lead Wiring 205, 305, 406, 507 Deep hole 306, 407, 508 Base 308, 510 First bottom surface 309, 511 Second bottom surface 503 First silicon nitride film 504 Second silicon nitride film

Claims (7)

In a capacitor having a conductive plug provided in an interlayer insulating film on a semiconductor substrate and a crown-shaped lower electrode in contact with the conductive plug,
A thickness of at least three times the thickness of the lower electrode is formed on at least a part of the surface of the interlayer insulating film provided with the conductive plug, where the bottom of the lower electrode does not contact the conductive plug. A bottom surface of the lower electrode is in contact with the conductive plug and is at least partially surrounded by the silicon nitride film; and at least part of the first bottom surface of the silicon nitride film A capacitor comprising a second bottom surface formed to project on a surface.   2. The capacitor according to claim 1, wherein the silicon nitride film is made of SiN or SiON.   3. The capacitor according to claim 1, wherein an inner diameter of the first bottom surface surrounded by the silicon nitride film is smaller than an inner diameter of a second bottom surface formed on the surface of the silicon nitride film in the same cross section. . In a method of manufacturing a capacitor having a conductive plug formed in a first interlayer insulating film on a semiconductor substrate and a crown-shaped lower electrode connected to the conductive plug,
(1) depositing a silicon nitride film having a thickness of at least three times the thickness of the lower electrode on the first interlayer insulating film on which the conductive plug is formed;
(2) depositing a second interlayer insulating film on the silicon nitride film;
(3) forming a deep hole through the second interlayer insulating film and the silicon nitride film to expose the surface of the conductive plug;
(4) retreating the side wall of the second interlayer insulating film out of the second interlayer insulating film and the silicon nitride film constituting the side wall of the deep hole to expose a part of the surface of the silicon nitride film;
(5) forming a lower electrode on the inner wall of the deep hole made of the second interlayer insulating film with the side wall set back and the silicon nitride film with the partial surface exposed;
(6) removing the second interlayer insulating film, exposing an outer wall of the lower electrode, and forming a crown-shaped lower electrode;
(7) forming a dielectric on the crown-shaped lower electrode;
(8) forming an upper electrode on the dielectric;
A method for producing a capacitor, comprising: In a method of manufacturing a capacitor having a conductive plug formed in a first interlayer insulating film on a semiconductor substrate and a crown-shaped lower electrode connected to the conductive plug,
(1) depositing a silicon nitride film having a thickness of at least three times the thickness of the lower electrode on the first interlayer insulating film on which the conductive plug is formed;
(2) depositing a second interlayer insulating film on the silicon nitride film;
(3) depositing a third interlayer insulating film having a wet etching rate slower than that of the second interlayer insulating film on the second interlayer insulating film;
(4) forming a deep hole through the third interlayer insulating film, the second interlayer insulating film and the silicon nitride film, and exposing the surface of the conductive plug;
(5) Of the third interlayer insulating film, the second interlayer insulating film, and the silicon nitride film constituting the side wall of the deep hole, the side wall of the second interlayer insulating film is retreated, and a partial surface of the silicon nitride film is formed. Exposing, and
(6) forming a lower electrode on the inner wall of the deep hole made of the third interlayer insulating film, the second interlayer insulating film with the side wall recessed, and the silicon nitride film with the partial surface exposed;
(7) removing the third interlayer insulating film and the second interlayer insulating film, exposing an outer wall of the lower electrode, and forming a crown-shaped lower electrode;
(8) forming a dielectric on the crown-shaped lower electrode;
(9) forming an upper electrode on the dielectric;
A method for producing a capacitor, comprising: In a method of manufacturing a capacitor having a conductive plug formed in a first interlayer insulating film on a semiconductor substrate and a crown-shaped lower electrode connected to the conductive plug,
(1) depositing a first silicon nitride film having a thickness of at least three times the thickness of the lower electrode on the first interlayer insulating film on which the conductive plug is formed;
(2) patterning the first silicon nitride film into a desired shape so as to cover the plug;
(3) depositing a second silicon nitride film on the entire surface;
(4) depositing a second interlayer insulating film on the second silicon nitride film and planarizing the surface;
(5) depositing a third interlayer insulating film having a wet etching rate slower than that of the second interlayer insulating film on the second interlayer insulating film having a planarized surface;
(6) forming a deep hole through the third interlayer insulating film, the second interlayer insulating film, the second silicon nitride film, and the patterned first silicon nitride film, and exposing the surface of the conductive plug; ,
(7) retreating the side wall of the second interlayer insulating film constituting a part of the side wall of the deep hole to expose a part of the surface of the second silicon nitride film;
(8) A deep hole made of the third interlayer insulating film, the second interlayer insulating film with the side wall receded, the second silicon nitride film with the partial surface exposed, and the patterned first silicon nitride film. Forming a lower electrode on the inner wall;
(9) removing the third interlayer insulating film and the second interlayer insulating film, exposing an outer wall of the lower electrode, and forming a crown-shaped lower electrode;
(10) forming a dielectric on the crown-shaped lower electrode;
(11) forming an upper electrode on the dielectric;
A method for producing a capacitor, comprising:   7. The method of manufacturing a capacitor according to claim 4, 5 or 6, wherein the silicon nitride film is made of SiN or SiON.

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