JP2006294760A - Method of manufacturing semiconductor device and support used for it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can perform easily a short-circuit and insulating with a semiconductor substrate and an electrode, can prevent the breakdown of an insulating film in a plasma processing step, and can prevent the curvature of the semiconductor substrate. <P>SOLUTION: An exposed part of the semiconductor substrate 11 and the through-electrode 12 is connected electrically through the conductor 3 for the short-circuit, respectively, to the support side conductor 22 of the stiff support 2, and the semiconductor substrate 11 and the through-electrode 12 are short-circuited. A plasma CVD is performed using a plasma CVD device 30 in this state. Since the semiconductor substrate 11 and the through-electrode 12 are in an equal potential, the breakdown is prevented in the side wall insulating film 13. Moreover, since the support 2 has the stiffness, the warpage of the semiconductor substrate 11 is prevented. After the plasma CVD, the conductor 3 for the short-circuit is removed, and a semiconductor device forming unit member 1 and the support 2 are made to exfoliate. Consequently, the semiconductor substrate 11 and the through-electrode 12 can be easily returned to the original insulated state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a stacked semiconductor integrated circuit device in which a large number of semiconductor chips having a multilayer wiring structure are stacked.

  In recent years, electronic devices typified by portable information devices such as mobile phones have been required to be smaller and lighter. In response to this requirement, miniaturization and high density of semiconductor devices mounted on electronic devices are being attempted. In order to miniaturize and increase the density of a semiconductor device, a stacked semiconductor integrated circuit device in which a plurality of semiconductor chips having a multilayer wiring structure are stacked has been proposed.

  FIG. 8 is a cross-sectional view showing a simplified configuration of a semiconductor device forming member 100 for forming a semiconductor chip included in a conventional stacked semiconductor integrated circuit device and a support 101 for supporting the semiconductor forming member 100. The semiconductor device forming member 100 is configured such that an internal circuit (not shown) including, for example, a field effect transistor (abbreviated as FET) is formed inside a semiconductor substrate 102 and has arbitrary characteristics as a device. . The gate electrode of the FET is electrically insulated from the semiconductor substrate 102 by a gate insulating film formed on the surface of the semiconductor substrate 102.

  Further, a plurality of through holes 103 penetrating in the thickness direction are formed in the semiconductor substrate 102, and a sidewall insulating film 104 is formed on the wall surface portion of the through hole 103. A conductive material is embedded in the through hole 103 to form a through electrode 105. The through electrode 105 is electrically connected to the internal circuit, and is used to obtain an electrical connection with another semiconductor chip stacked in the stacked semiconductor integrated circuit device. The sidewall insulating film 104 is provided in order to maintain electrical insulation between the through electrode 105 and the semiconductor substrate 102.

  The through electrode 105 has a non-through hole formed by dry etching or the like on a surface (hereinafter referred to as a device formation surface) 106 on which an internal circuit of the semiconductor substrate 102 is formed, and a sidewall insulating film 104 is formed on the wall surface portion. After the conductive material is embedded by plating or the like, the surface opposite to the device formation surface 106 (hereinafter referred to as the back surface) 107 is retracted to expose the conductive material embedded in the non-through hole. .

  When the back surface 107 of the semiconductor substrate 102 is retracted, as shown in FIG. 8, the device forming surface 106 is bonded to a support 101 made of an insulating material via a double-sided adhesive tape 108, and the back surface 107 is attached in this state. The conductive material is ground with a grindstone or the like, and the conductive material embedded in the non-through hole is exposed on the back surface 107 of the semiconductor substrate 102 to be flush with each other. As a result, the non-through hole enters the semiconductor substrate 102 and the through electrode 105 is formed.

  After the through electrode 105 is formed in this manner and the semiconductor device forming member 100 is manufactured, the back surface 107 of the semiconductor substrate 102 is etched, and the through electrode 105 is formed on the back surface 107 of the semiconductor substrate 102 as shown in FIG. The back surface protruding electrode 109 is formed so as to protrude from the semiconductor layer and be stacked as a semiconductor chip. Next, a passivation film (not shown) is formed on the back surface 107 of the semiconductor substrate 102 to obtain a semiconductor chip.

  A plasma etching apparatus is often used for etching the semiconductor substrate 102 to form the back protrusion electrode 109. A plasma chemical vapor deposition (abbreviated as CVD) apparatus is often used for forming a passivation film.

  FIG. 9 is a cross-sectional view showing a simplified configuration of a plasma CVD apparatus 110 used in the prior art. The plasma CVD apparatus 110 includes an upper insulating plate 112 and a lower stage 113 which are disposed in parallel with each other and inward of the dielectric container 111. A spiral antenna 114 is provided outside the dielectric container 111 and on the opposite side of the upper insulating plate 112 from the side facing the lower stage 113, and an AC power source 115 is connected to the spiral antenna 114.

  At the time of film formation, the semiconductor device forming member 100 held on the support 101 via the double-sided adhesive tape 108 is placed so that the support 101 is in contact with the lower stage 113, and then inside a vacuum processing chamber (not shown). A reactive gas is introduced into the dielectric container 111 by evacuation. A plasma discharge is generated in the dielectric container 111 by applying an AC voltage to the spiral antenna 114 by the AC power source 115 to generate plasma 116, and the reactive radicals and ions generated along with the plasma 116 are used to generate the plasma 116. A chemical reaction occurs on the back surface 107. As a result, a thin film such as an insulating film serving as a passivation film is formed on the back surface 107 of the semiconductor substrate 102.

  The plasma etching apparatus has the same configuration as the plasma CVD apparatus 110 shown in FIG. In the plasma etching apparatus, the back surface of the semiconductor substrate 107 is irradiated with reactive radicals and ions generated in the dielectric container 111, thereby etching the back surface 107 of the semiconductor substrate 102.

  In an apparatus for processing using plasma such as a plasma CVD apparatus or a plasma etching apparatus as shown in FIG. 9 (hereinafter collectively referred to as a plasma processing apparatus), the semiconductor substrate 102 and the through electrode 105 are made of ions, electrons, etc. in the plasma 116. It is easily charged because it is exposed to charged particles. The semiconductor substrate 102 is made of a semiconductor material such as silicon, and the through electrode 105 is formed of a conductive material containing silver or the like. That is, the semiconductor substrate 102 and the through electrode 105 are made of different materials. For this reason, even if the semiconductor substrate 102 and the through electrode 105 are charged under the same conditions, the charge amount is different, and as a result, a potential difference is generated between the semiconductor substrate 102 and the through electrode 105.

  FIG. 10 is an equivalent circuit diagram around the semiconductor device forming member 100 in the plasma CVD apparatus 110 shown in FIG. In FIG. 10, the point A ′ represents the potential of the through electrode 105, the point B ′ represents the potential of the semiconductor substrate 102, and the point C ′ represents the potential of the plasma 116. R1 ′ represents an equivalent resistance component between the through electrode 105 and the plasma 116, R2 ′ represents an equivalent resistance component between the semiconductor substrate 102 and the plasma 116, and R3 ′ represents the through electrode 105 and the semiconductor substrate 102. Represents a resistance component of the sidewall insulating film 104 provided between the two.

  As described above, since the through electrode 105 and the semiconductor substrate 102 are formed of different materials, there is a difference in the amount of charge that is charged on the surface when exposed to charged particles in the plasma 116. That is, the potential of the through electrode 105 represented by the point A ′ is not equal to the potential of the semiconductor substrate 102 represented by the point B ′. On the other hand, the resistance value of the sidewall insulating film 104 represented by R3 ′ is as extremely large as several MΩ, and almost no current flows between A ′ and B ′. A voltage is applied. Since this voltage is extremely high, such as about several tens of volts, when the plasma treatment is performed in such a state that the voltage is applied, the sidewall insulating film 104 provided between the through electrode 105 and the semiconductor substrate 102 is broken down. Problem arises. Further, the voltage applied between the through electrode 105 and the semiconductor substrate 102 is also transmitted to the gate electrode of the FET provided in the internal circuit (not shown) via the through electrode 105, so that the breakdown of the gate insulating film of the FET is also prevented. Arise. In particular, the sidewall insulating film 104 is often about 0.1 to 1.0 μm thick, but a gate insulating film (not shown) has a thickness of about several tens of nanometers and is often thinner than the sidewall insulating film 104. When the same voltage is applied, the dielectric breakdown is easier than in the sidewall insulating film 104.

  In order to prevent the breakdown of the gate insulating film of the FET, it is necessary to insert a protective diode between the through electrode 105 and the FET. However, when the protective diode is inserted, it is caused by the parasitic capacitance of the protective diode. A signal delay occurs, and a malfunction occurs in a device operating at high speed. Another problem is that the degree of freedom in design is reduced by forming the protective diode.

  For this reason, as a prior art for preventing dielectric breakdown of the gate insulating film due to charging during plasma processing without using a protective diode, a short-circuit wiring for short-circuiting the gate electrode and the semiconductor substrate is separately provided, and plasma processing, etc. It has been proposed to cut the short-circuit wiring at the same time as processing other thin films deposited on the semiconductor substrate by a photolithography method or the like after performing a process in which charging is likely to occur (for example, Patent Documents). 1 and 2).

  Further, although not a technique for preventing dielectric breakdown of the gate insulating film, a technique for preventing electrostatic breakdown of a semiconductor device has been proposed (see, for example, Patent Document 3). In Patent Document 3, a protective film sheet used for protecting a device forming surface of a semiconductor substrate in the step of grinding the back surface of the semiconductor substrate is made conductive to protect the device forming surface. It is disclosed that electrostatic breakdown of a semiconductor device due to static electricity when a film sheet is attached or peeled can be prevented.

JP-A-6-181220 (page 4-5, FIG. 2) Japanese Patent Laid-Open No. 5-166946 (page 3-4, Fig. 2-3) JP-A-5-275479 (2nd page, Fig. 1)

  In the techniques disclosed in Patent Documents 1 and 2, since the short-circuit wiring is cut at the same timing as the processing of other thin films, the short-circuit between the gate electrode and the semiconductor substrate cannot be maintained in subsequent processes, and gate insulation is performed. The dielectric breakdown of the film cannot be prevented. For this reason, when performing a process that may be charged after processing other thin films, the short-circuited wiring is cut separately after the process that may be charged without cutting the short-circuited wiring when processing other thin films. There is a problem that the manufacturing process is increased. In addition, since the dry etching using plasma such as reactive ion etching (abbreviation RIE) is used for cutting the short-circuit wiring, the manufacturing process becomes complicated and the breakdown of the gate insulating film is caused by the cutting of the short-circuit wiring. There is also a risk of it occurring.

  Further, in the techniques disclosed in Patent Documents 1 and 2, a short-circuit wiring is formed by leaving a part of the gate electrode layer for forming a gate electrode that is short-circuited with the semiconductor substrate. When it is cut, it is difficult to provide a new short-circuit wiring even if a short-circuit is required again due to a subsequent design change or the like. Even if a new short-circuit wiring can be provided, it is necessary to further add a step of cutting the short-circuit wiring, resulting in an increase in manufacturing steps. Further, when changing the design, it is necessary to consider the arrangement of the short-circuit wiring, and the design cannot be easily changed.

  Further, in the technologies disclosed in Patent Documents 1 and 2, the sidewall insulating film 104 generated when the plasma processing is performed on the semiconductor device forming member 100 in which the through electrode 105 and the internal circuit shown in FIG. 9 are formed. In addition, the dielectric breakdown of the gate insulating film cannot be prevented. In the semiconductor device forming member 100 shown in FIG. 8 described above, since the gate electrode is covered with the insulating film, the short-circuit wiring is formed integrally with the gate electrode as in the techniques disclosed in Patent Documents 1 and 2. It is not possible. For this reason, in the plasma CVD apparatus 110 shown in FIG. 9, an excessive potential difference is generated between the through electrode 105 and the semiconductor substrate 102, and dielectric breakdown of the sidewall insulating film 104 and the gate insulating film of the internal circuit occurs.

  On the other hand, the technique disclosed in Patent Document 3 is for preventing electrostatic breakdown of the semiconductor device, and does not have a problem with respect to the breakdown of the sidewall insulating film 104 and the gate insulating film in the plasma processing step. Patent Document 3 does not describe the state of the device formation surface of the semiconductor substrate in contact with the conductive adhesive, and is it possible to short-circuit the gate electrode and the semiconductor substrate? Whether or not is unknown.

  Moreover, since the protective film sheet disclosed in Patent Document 3 is in a film form and deforms following the deformation of the semiconductor substrate to be attached, when such a protective film sheet is attached to the semiconductor substrate and the back surface is ground, There is a problem that warpage occurs in the semiconductor substrate. A semiconductor device forming member having a warped semiconductor substrate is difficult to process, and problems occur when a semiconductor device is manufactured using such a semiconductor device forming member. For example, when the passivation film is formed using the plasma CVD apparatus 110 shown in FIG. 9 described above, the device formation surface 106 of the semiconductor substrate 102 cannot be placed in parallel to the lower stage 113, so that the semiconductor substrate 102 A passivation film having a uniform thickness cannot be formed on the entire back surface 107 of the film, and the in-plane uniformity is reduced. Also, during the plasma etching, the back surface 107 of the semiconductor substrate 102 cannot be etched uniformly, and the height of the protruding portion of the back surface protruding electrode 109 varies, making it difficult to stack on other semiconductor chips. . Further, when the semiconductor substrate 102 is warped, there is a problem that subsequent conveyance becomes difficult. Further, since the warped semiconductor substrate 102 is easily cracked even with a slight impact, the semiconductor substrate 102 may be cracked during the transport process, which may reduce the manufacturing yield.

  An object of the present invention is to easily perform a short circuit and insulation between a semiconductor substrate and an electrode provided on the semiconductor substrate, to prevent dielectric breakdown of the insulating film in the plasma processing step, and to prevent warping of the semiconductor substrate. It is to provide a method of manufacturing a semiconductor device that can be used and a support used in the method.

The present invention provides a semiconductor substrate provided between a semiconductor substrate and a substrate side electrode, a semiconductor substrate in which at least a part of a surface portion on one side in the thickness direction is exposed, a substrate side electrode exposed on the surface portion side of the semiconductor substrate, A semiconductor device manufacturing method for manufacturing a semiconductor device using a semiconductor device forming member including an insulator that electrically insulates the substrate side electrode from the substrate,
For a short circuit by electrically connecting a portion of the semiconductor device forming member where the semiconductor substrate and the substrate side electrode are exposed to each other through a short circuit conductor to a rigid and conductive support. A short-circuiting step of short-circuiting the semiconductor substrate and the substrate-side electrode via the conductor and the support;
A plasma processing step of performing plasma processing on the semiconductor device forming member;
A method of manufacturing a semiconductor device, comprising: a peeling step of peeling the semiconductor device forming member and the support by removing the short-circuiting conductor.

The present invention also provides a plasma processing step.
Plasma treatment is performed by generating plasma in a state where a support is electrically connected to a mounting electrode for supporting a semiconductor device forming member and applying a voltage to the plasma.

In the present invention, the support is capable of transmitting ultraviolet rays,
The short-circuiting conductor includes an ultraviolet peelable adhesive whose adhesive strength is reduced by ultraviolet irradiation,
In the peeling process,
The semiconductor device forming member and the support are peeled off by irradiating the short-circuiting conductor with ultraviolet rays through the support.

  Further, the invention is characterized in that the short-circuiting conductor is a conductive adhesive or a conductive adhesive sheet.

  In the invention, the short-circuiting conductor is an anisotropic conductive paste or an anisotropic conductive sheet.

The present invention also provides a semiconductor substrate in which at least a part of the surface portion on one side in the thickness direction is exposed, a substrate side electrode exposed on the surface portion side of the semiconductor substrate, and a semiconductor provided between the semiconductor substrate and the substrate side electrode. A support for performing plasma treatment on a semiconductor device forming member including an insulator that electrically insulates a substrate and a substrate-side electrode,
Have rigidity and conductivity,
A support for supporting a semiconductor device forming member by electrically connecting portions of the semiconductor device forming member where the semiconductor substrate and the substrate side electrode are exposed via a short-circuiting conductor.

  According to the present invention, in the short-circuiting step, the portions where the semiconductor substrate and the substrate-side electrode of the semiconductor device forming member are exposed to the rigid and conductive support are respectively exposed via the short-circuiting conductor. By electrically connecting, the semiconductor substrate and the substrate-side electrode are short-circuited via the short-circuiting conductor and the support, and the plasma processing is performed on the semiconductor device forming member in the plasma processing step. During the plasma processing, the semiconductor substrate and the substrate-side electrode are short-circuited and thus have the same potential. As a result, it is possible to prevent a voltage from being applied between the semiconductor substrate and the substrate-side electrode, so that it is possible to prevent dielectric breakdown of an insulator provided between the semiconductor substrate and the substrate-side electrode. Moreover, since the support body has rigidity, the semiconductor substrate can be prevented from warping. Thereby, since the plasma treatment can be performed uniformly over the entire surface to be processed of the semiconductor device forming member, the in-plane uniformity of the semiconductor device forming member after processing can be improved. In addition, the semiconductor device forming member can be easily transported, and a decrease in manufacturing yield due to breakage of the semiconductor substrate being transported can be suppressed.

  In the peeling step after the plasma treatment step, the semiconductor device forming member and the support are peeled off by removing the short-circuiting conductor. As a result, the semiconductor substrate and the substrate-side electrode can be easily returned to the original insulating state. In addition, since the semiconductor device forming member and the support can be electrically connected again via the short-circuit conductor, the semiconductor substrate and the substrate-side electrode need to be short-circuited again due to a design change or the like. Short circuit can be easily performed. Therefore, it is possible to efficiently deal with design changes and the like.

  According to the invention, in the plasma processing step, the plasma is generated by generating the plasma in a state where the support is electrically connected to the mounting electrode for supporting the semiconductor device forming member and applying a voltage to the plasma. Perform processing. Since the semiconductor substrate and the substrate side electrode are electrically connected to the support, the mounting electrode and the semiconductor substrate and the substrate side electrode are electrically connected through the support during the plasma processing. Thus, the semiconductor substrate and the substrate side electrode can be set to the same potential, and the semiconductor substrate, the substrate side electrode and the mounting electrode can be set to the same potential. Accordingly, the dielectric breakdown of the insulator between the semiconductor substrate and the substrate-side electrode is prevented, the change in potential of the mounting electrode is suppressed, and the energy imparted to charged particles such as ions and electrons in the plasma by the mounting electrode. Can be made constant, so that stable plasma treatment can be performed.

  Further, according to the present invention, the support can transmit ultraviolet rays, and the short-circuiting conductor includes an ultraviolet peelable adhesive whose adhesive strength is reduced by irradiation with ultraviolet rays. Thereby, in a peeling process, a semiconductor device formation member and a support body can be made to peel by irradiating a short circuit conductor with an ultraviolet-ray through a support body. Therefore, the semiconductor device forming member and the support can be easily separated.

  According to the invention, the short-circuiting conductor is a conductive adhesive or a conductive adhesive sheet. Thus, in the short-circuiting step, the short-circuiting conductor can be interposed between the semiconductor device forming member and the support without using a vacuum film forming apparatus that uses a vacuum pump or the like. Therefore, the time required for the short-circuit process can be shortened and the throughput can be improved. Also, when a conductive adhesive sheet is used as the short-circuiting conductor, in the peeling step, the semiconductor device forming member and the support can be peeled simply by peeling the conductive adhesive sheet from the semiconductor device forming member. Efficiency can be improved.

  According to the invention, the short-circuit conductor is an anisotropic conductive paste or an anisotropic conductive sheet. As a result, the electrical connection between the semiconductor substrate and the support and the electrical connection between the substrate-side electrode and the support can be more reliably performed, so that the semiconductor substrate and the substrate-side electrode can be reliably short-circuited. . Therefore, it is possible to more reliably prevent the dielectric breakdown of the insulator between the semiconductor substrate and the substrate side electrode in the plasma processing step.

  According to the invention, the support used when the plasma processing is performed on the semiconductor device forming member has rigidity and conductivity, and the semiconductor substrate and the substrate side electrode of the semiconductor device forming member are exposed. Are used in a state of being electrically connected via a short-circuiting conductor. As a result, the semiconductor substrate and the substrate-side electrode are short-circuited during plasma processing and become the same potential, preventing a voltage from being applied between the semiconductor substrate and the substrate-side electrode, and between the semiconductor substrate and the substrate-side electrode. It is possible to prevent dielectric breakdown of the insulator provided on the substrate. Moreover, since the support body has rigidity, the semiconductor substrate can be prevented from warping. Further, since the support can be peeled off from the semiconductor device forming member by removing the short-circuiting conductor, the semiconductor substrate and the substrate-side electrode can be easily returned to the original insulating state.

  FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device forming member 1 and a support 2 on which the semiconductor device forming member 1 is supported used in a method for manufacturing a semiconductor device according to an embodiment of the present invention. . In this embodiment, a semiconductor device used as a semiconductor chip in a stacked semiconductor integrated circuit device, for example, is formed using the semiconductor device forming member 1. The semiconductor device forming member 1 is supported by a support 2 and is subjected to a plasma processing step described later.

  The semiconductor device forming member 1 includes a semiconductor substrate 11, a through electrode 12 that is a substrate side electrode, and a sidewall insulating film 13 that is an insulator. An internal circuit including an active element such as a field effect transistor (abbreviated as FET) (not shown) is provided on a surface portion on one side in the thickness direction of the semiconductor substrate 11. By providing an internal circuit on the surface portion on one side in the thickness direction of the semiconductor substrate 11, the semiconductor device forming member 1 can be provided with a desired function as a device.

  The semiconductor substrate 11 is formed with a plurality of through-electrode insertion holes 14 extending in the thickness direction from a surface portion (hereinafter referred to as a device formation surface) 16 on which an internal circuit is formed. The through electrode insertion hole 14 is, for example, a substantially cylindrical shape, and is a through hole that penetrates the semiconductor substrate 11 in the thickness direction. At least a part of the device forming surface 16 of the semiconductor substrate 11 is exposed. In the present embodiment, a protective film (not shown) is formed on the device forming surface 16 of the semiconductor substrate 11 to protect the internal circuit, and a part of the protective film, specifically, the through electrode insertion hole 14 is formed. The vicinity of the through-electrode insertion hole 15 to be formed is opened to form an exposed portion 11a where the semiconductor substrate 11 is exposed.

The through electrode 12 is made of a conductive material such as copper, and is filled in the through electrode insertion hole 14. The through electrode 12 is formed so as to be exposed from both surface portions of the semiconductor substrate 11 in a state in which the through electrode insertion hole 14 is filled. A sidewall insulating film 13 is formed on the wall surface portion of the through electrode insertion hole portion 15 that forms the through electrode insertion hole 14. Sidewall insulating film 13 is formed of an insulating material such as silicon dioxide (SiO ₂ ). The sidewall insulating film 13 can electrically insulate the semiconductor substrate 11 and the through electrode 12.

  As the semiconductor substrate 11, a p-type semiconductor substrate, for example, a p-type single crystal silicon (Si) substrate is used. The material constituting the semiconductor substrate 11 is not limited to silicon, and various semiconductor materials can be used. Further, the conductivity of the semiconductor substrate 11 is not limited to p-type, and may be n-type.

  The support 2 is formed so as to have rigidity and conductivity. In the present embodiment, the support 2 includes a support body 21 and a support-side conductor 22. The support-side conductor 22 is provided on the surface portion of the support body 21 that faces the semiconductor device forming member 1. The support 2 can support the semiconductor device forming member 1 on a flat surface portion on which the support-side conductor 22 is provided.

  The support body 21 is formed of a material having rigidity and insulating properties. In the present embodiment, the support body 21 is made of a material that can transmit ultraviolet rays. The support body 21 is realized by heat-resistant glass such as quartz or Pyrex (registered trademark), calcium fluoride, or the like.

  The support-side conductor 22 is formed by depositing a conductive material on the surface of the support body 21 by, for example, sputtering. In the present embodiment, the support-side conductor 22 is formed of a conductive material that can transmit ultraviolet rays. The support-side conductor 22 is realized by, for example, indium tin oxide (Indium Tin Oxides; abbreviated as ITO), tin oxide, or IZO obtained by adding a small amount of zinc thereto. By forming the support body 21 and the support-side conductor 22 from a material that can transmit ultraviolet light, the support 2 that can transmit ultraviolet light can be realized.

  A short-circuiting conductor 3 is interposed between the semiconductor device forming member 1 and the support 2. The short-circuiting conductor 3 is formed of a conductive material. The exposed portion 11 a of the device forming surface 16 of the semiconductor substrate 11 is electrically connected to the support-side conductor 22 of the support 2 via the short-circuiting conductor 3. The exposed portion of the through electrode 12 is electrically connected to the support-side conductor 22 of the support 2 via the short-circuiting conductor 3. As a result, the semiconductor substrate 11 and the through electrode 12 are short-circuited via the short-circuiting conductor 3 and the support-side conductor 22 of the support 2.

  The short-circuiting conductor 3 is, for example, a conductive adhesive sheet, and includes an adhesive layer and a conductive filler. The adhesive layer is formed of an adhesive resin such as an epoxy thermosetting resin and has adhesiveness on both surface portions in the thickness direction. Conductive fillers are dispersed in the adhesive layer to form a conductive adhesive sheet having conductivity. As the conductive filler, metal particles such as gold, silver and nickel, resin particles such as styrene resin and acrylic resin, and inorganic particles such as titanium oxide plated with a metal such as gold are used. The particle size of the conductive filler is, for example, several μm.

  In this embodiment, it is preferable to use an anisotropic conductive sheet among the conductive adhesive sheets. An anisotropic conductive sheet is a conductive adhesive sheet having conductivity in the thickness direction and having insulation in other directions. In the anisotropic conductive sheet, the surface portion perpendicular to the thickness direction exposes one surface portion in the thickness direction of the semiconductor device forming member 1 and the support 2, that is, the device forming surface 16 of the semiconductor substrate 11 and the support-side conductor 22. It arrange | positions so that a surface part may be faced. Thereby, the short-circuiting conductor 3 made of an anisotropic conductive sheet conducts in the thickness direction. Therefore, the conduction between the semiconductor substrate 11 and the support-side conductor 22 of the support 2 and the conduction between the through electrode 12 and the support-side conductor 22 of the support 2 can be ensured. And the through electrode 12 can be short-circuited reliably.

  The anisotropic conductive sheet is formed, for example, by filling an adhesive layer formed as described above with a conductive filler that can be deformed by pressure. By sticking such an anisotropic conductive sheet to the semiconductor device forming member 1 and the support 2 and applying pressure or heat and pressure, the conductive filler is deformed, and between the semiconductor device forming member 1 and the support 2. Thus, the short-circuiting conductor 3 is realized which is sandwiched between and has conductivity in the thickness direction and insulation in other directions.

In the present embodiment, the conductive adhesive sheet such as an anisotropic conductive sheet is made of ultraviolet rays (Ultra
Violet (abbreviation UV) It is comprised as a UV peeling type adhesive tape which can be peeled off by irradiating. In this case, the adhesive layer is configured to include a UV peelable adhesive whose adhesive strength is reduced by irradiation with ultraviolet rays. As the UV peelable adhesive, for example, an acrylic copolymer containing a UV curable oligomer is used.

  The short-circuiting conductor 3 is not limited to a conductive adhesive sheet such as an anisotropic conductive sheet, and may be formed of a conductive adhesive. The conductive adhesive includes an adhesive resin and a conductive filler. As the resin having adhesiveness and the conductive filler, those similar to the conductive adhesive sheet can be used. The conductive adhesive may be used in any form of liquid, paste, and solid. In the case of using a solid conductive adhesive, the thickness can be made uniform by applying heat and pressure after being applied to the semiconductor device forming member 1 or the support 2. In addition, the above-mentioned conductive adhesive sheet can also be produced by forming a conductive adhesive into a sheet shape.

  Even when the conductive adhesive is used, it is preferable to use an anisotropic conductive paste. The anisotropic conductive paste includes particles that can be deformed by pressure as a conductive filler. By sticking the semiconductor device forming member 1 and the support 2 through an anisotropic conductive paste and applying pressure or heat and pressure, the conductive material is conductive in the thickness direction as in the case of using an anisotropic conductive sheet. And the short-circuiting conductor 3 having an insulation property in other directions is realized. Thereby, a short circuit between the semiconductor substrate 11 and the through electrode 12 can be made more reliable. The anisotropic conductive paste can be applied to the semiconductor device forming member 1 or the support 2 by, for example, spin coating. Note that the conductive adhesive such as the anisotropic conductive paste used in the present embodiment includes the above-described ultraviolet peelable adhesive, and the adhesive strength is reduced by irradiation with ultraviolet rays.

  FIG. 2 is a flowchart showing a procedure for manufacturing a semiconductor device by the method for manufacturing a semiconductor device of this embodiment. The method for manufacturing a semiconductor device of the present invention includes at least a short-circuiting process, a plasma processing process, and a peeling process. In this embodiment, a semiconductor device forming member manufacturing step and a conductive member exposing step are further included. That is, the semiconductor device manufacturing method according to this embodiment includes a semiconductor device forming member manufacturing step, a short-circuiting step, a conductive member exposing step, a plasma processing step, and a peeling step. The procedure starts at step s0 and proceeds to step s1.

  FIG. 3 is a partial cross-sectional view showing a simplified state after completion of the semiconductor device forming member manufacturing process. In FIG. 3, a part of the semiconductor device forming member 1a to be formed is shown enlarged. In step s1, which is a semiconductor device forming member manufacturing step, a semiconductor device forming member 1a to be the semiconductor device forming member 1 shown in FIG. 1 is manufactured. The semiconductor device forming member 1 a to be formed includes a semiconductor substrate 11, a conductive member 12 a that becomes the through electrode 12, and a sidewall insulating film 13. The semiconductor device forming member manufacturing process in step s1 includes a device forming step, a non-through-hole forming step, a sidewall insulating film forming step, and a conductive member filling step.

  In the device formation step, an internal circuit including an active element such as an FET (not shown) is formed. The internal circuit is formed as follows. Diffusion regions (not shown) that serve as FET source and drain regions are formed on the surface of the semiconductor substrate 11 that serves as the device formation surface 16. Next, a gate insulating film and a gate electrode (not shown) are sequentially formed on the surface portion of the semiconductor substrate 11 where the diffusion region is formed. As a result, an FET is formed. The gate electrode of the FET is electrically insulated from the semiconductor substrate 11 by a gate insulating film.

Next, an insulating film made of silicon dioxide (SiO ₂ ) or the like is formed so as to cover the gate electrode. Of the formed insulating film, the insulating film formed in the source and drain regions of the FET and the insulating film formed in a predetermined portion for forming the exposed portion 11a of the semiconductor substrate 11 are removed. Then, an opening is formed, and the semiconductor substrate 11 is exposed through the opening. Next, a conductive material is filled in the openings of the source electrode and drain electrode portions of the FET to form conductive plugs for electrically connecting the source and drain regions and the through electrode 12. As a result, an internal circuit is formed on the device forming surface 16 of the semiconductor substrate 11. In this way, the internal circuit is formed, and the process proceeds to the non-through hole forming step.

  In the non-through hole forming step, a plurality of non-through holes 14 a to be the through electrode insertion holes 14 are formed on the device forming surface 16 of the semiconductor substrate 11. The plurality of non-through holes 14a are formed by etching the semiconductor substrate 11 from the device forming surface 16 side, for example, by dry etching. As a result, a non-through hole 14 a which is a bottomed hole having a depth in the thickness direction is formed in the semiconductor substrate 11. In this way, the non-through hole 14a is formed, and the process proceeds to the side wall insulating film forming step.

In the side wall insulating film forming step, the side wall insulating film 13 made of silicon dioxide (SiO ₂ ) or the like is formed on the wall surface of the non-through hole 14a by, for example, thermal chemical vapor deposition. In this way, the sidewall insulating film 13 is formed, and the process proceeds to the conductive member filling step.

  In the conductive member filling step, the non-through holes 14a are filled with a conductive material, for example, by plating to form the conductive member 12a. For example, copper (Cu), aluminum (Al), polysilicon (p-Si), or the like is used as the conductive material. A barrier metal film (not shown) may be formed on the side surface in the longitudinal direction of the conductive member 12a in order to prevent diffusion due to heat in a subsequent process. When forming the barrier metal film, the barrier metal film is formed on the wall surface portion of the non-through hole 14a by plating or the like, and then the conductive material is filled to form the conductive member 12a. As the barrier metal film, for example, when copper is used as the conductive material, a titanium nitride (TiN) film or the like is formed. After filling the non-through hole 14a with the conductive member 12a in this manner, a connection wiring (not shown) that electrically connects the conductive member 12a and the conductive plug of the internal circuit is formed. Thereby, the semiconductor device forming member 1a is formed. In this way, the semiconductor device forming member 1a is manufactured, and the process proceeds from step s1 to step s2.

  In step s2 which is a short-circuiting process, the semiconductor device forming member 1a and the support 2 are bonded together via the short-circuiting conductor 3, and the semiconductor substrate 11 and the conductive member 12a serving as the through electrode 12 are short-circuited. The bonding of the semiconductor device forming member 1a and the support 2 can be performed, for example, as follows.

  For example, when a conductive adhesive sheet is used as the short-circuiting conductor 3, first, the conductive adhesive sheet 3 is attached to the device forming surface 16 side of the semiconductor device forming member 1a. Next, the surface of the conductive adhesive sheet 3 opposite to the side attached to the semiconductor device forming member 1a is attached to the surface of the support 2 on which the support-side conductor 22 is formed. As a result, the exposed portion 11a of the semiconductor substrate 11 and the conductive member 12a are electrically connected to the support-side conductor 22 formed on the surface of the support body 21 via the short-circuit conductor 3 made of a conductive adhesive sheet. The semiconductor substrate 11 and the conductive member 12a are short-circuited. In order to prevent air bubbles from being mixed between the conductive adhesive sheet and the semiconductor device forming member 1a or the support 2, the bonding between the conductive adhesive sheet and the semiconductor device forming member 1a or the support 2 is performed in the vacuum container. In this case, it is desirable to be performed in a high temperature and pressurized atmosphere. In addition, a conductive adhesive sheet may be affixed on the support body 2, and may be affixed on the semiconductor device formation member 1a after that.

  When a conductive adhesive is used as the short-circuiting conductor 3, the conductive adhesive is applied to one of the semiconductor device forming member 1 a and the support 2, and then the other is bonded. When a conductive adhesive sheet or a conductive adhesive is used in this way, a short-circuiting conductor is provided between the semiconductor device forming member 1a and the support 2 without using a vacuum film forming apparatus that uses a vacuum pump or the like. 3 can be interposed. Therefore, the time required for the short-circuit process can be shortened and the throughput can be improved. In this way, the semiconductor substrate 11 and the conductive member 12a are short-circuited, and the process proceeds from step s2 to step s3.

  In step s3, which is the conductive member exposing step, the back surface 17 which is the surface opposite to the device forming surface 16 of the semiconductor substrate 11 is ground with a grindstone or the like, for example, and moved back in the thickness direction. The conductive member 12 a and the sidewall insulating film 13 thus exposed are exposed from the back surface 17 of the semiconductor substrate 11. As a result, the non-through hole 14a penetrates the semiconductor substrate 11 to form the through electrode insertion hole 14, and the conductive member 12a penetrates the semiconductor substrate 11 to form the through electrode 12. The method of retracting the back surface 17 of the semiconductor substrate 11 in the thickness direction is not limited to grinding, and may be polishing, and is not limited as long as it can be retracted in the thickness direction.

  After the back surface 17 of the semiconductor substrate 11 is thus retracted in the thickness direction, the back surface 17 is polished with a slurry having chemical etching properties, such as an alkaline slurry mixed with alumina. Thus, polishing scratches or the like generated on the back surface 17 due to grinding or the like can be removed, and the back surface 17 can be mirror-finished. In this way, the semiconductor device forming member 1 shown in FIG. 1 is formed. The semiconductor device forming member 1 is subjected to the next plasma processing step while being supported by the support 2.

  The semiconductor substrate 11 of the semiconductor device forming member 1a is thinned to a thickness of, for example, about 300 μm or less by retracting the back surface 17 in the thickness direction. Although the semiconductor substrate 11 is likely to be warped due to the reduction in thickness, the semiconductor device forming member 1 is supported by the support 2 formed of a material having rigidity, so that the warpage of the semiconductor substrate 11 is suppressed. Is done. As a result, the semiconductor device forming member 1 can be easily transported, and a decrease in manufacturing yield due to damage to the semiconductor substrate 11 being transported can be suppressed. If the support 2 does not have rigidity, for example, if a substantially circular wafer having a diameter of 8 inches (about 203.2 mm) is used as the semiconductor substrate 11 and the thickness is reduced to about 300 μm or less, the amount of warpage of the wafer becomes large. Therefore, it becomes difficult to carry to the next process and to install in a device such as a plasma processing device described later.

  Further, when grinding the back surface 17 of the semiconductor substrate 11, the semiconductor device forming member 1 a is placed on the grinding stage such as a grinding device via the support 2 and is ground. Although the support 2 has rigidity, a short-circuit conductor 3 made of a conductive adhesive sheet or a conductive adhesive is interposed between the support 2 and the semiconductor device forming member 1a. The device forming surface 16 of the semiconductor device forming member 1a can be protected. That is, the short-circuiting conductor 3 also functions as a protective layer that protects the device forming surface 16 of the semiconductor device forming member 1a. In order to ensure protection of the device forming surface 16 of the semiconductor device forming member 1a, the thickness of the short-circuiting conductor 3 is preferably 50 to 500 μm.

Thus, the through electrode 12 is formed, and the process proceeds from step s3 to step s4. In step s4, which is a plasma processing step, the semiconductor device forming member 1 is subjected to plasma processing. Here, plasma treatment means plasma etching, plasma chemical vapor deposition (
Chemical Vapor Deposition (abbreviated as CVD), ashing, plasma cleaning, and the like are processes for processing a semiconductor device forming member using plasma. Among these plasma treatments, one or more plasma treatments are performed on the semiconductor device forming member 1. In this embodiment, plasma etching and plasma CVD are performed. That is, the plasma processing process includes a plasma etching step and a plasma CVD step.

  In the plasma etching step, the semiconductor device forming member 1 formed in step s3 is etched by dry etching using plasma, and the back surface 17 of the semiconductor substrate 11 is further retracted in the thickness direction. As a result, the through electrode 12 exposed on the back surface 17 of the semiconductor substrate 11 protrudes from the back surface 17 to form a back surface protruding electrode 18 shown in FIG. 4 to be described later. At this time, the sidewall insulating film 13 surrounding the through electrode 12 is also protruded from the back surface 17 of the semiconductor substrate 11. By adjusting the etching amount of the back surface 17 of the semiconductor substrate 11, the through electrode 12 can be protruded from the back surface 17 of the semiconductor substrate 11 by a desired height. The plasma etching of the semiconductor device forming member 1 is performed using a reactive ion etching (abbreviated as RIE) apparatus or the like.

  In the plasma CVD step, a passivation film made of an insulating material such as a silicon nitride film is formed on the entire back surface 17 of the plasma-etched semiconductor substrate 11 by plasma CVD. Further, if necessary, wiring is formed on the surface of the passivation film. Plasma CVD is performed using an inductively coupled plasma (abbreviated as ICP) type plasma CVD apparatus, a capacitively coupled plasma CVD apparatus, or the like.

  The state of the semiconductor device forming member 1 in these plasma processing steps will be described by taking a plasma CVD step as an example. FIG. 4 is a cross-sectional view showing a simplified configuration of the ICP type CVD apparatus 30 used in the plasma CVD step. An ICP type plasma CVD apparatus (hereinafter also simply referred to as a plasma CVD apparatus) 30 basically includes a dielectric container 31, an upper insulating plate 32, a mounting electrode 33, a plasma excitation coil 34, and an AC power source 35. It is comprised including.

The dielectric container 31 is connected to a vacuum pump and a gas supply device (not shown). The dielectric container 31 is formed so that it can withstand atmospheric pressure even if the inner space is evacuated. The dielectric container 31 is formed of a dielectric such as quartz or ceramics. The dielectric container 31 is used in a vacuum state with its inner space being evacuated by a vacuum pump. Here, the vacuum state is a state where the pressure is reduced to a pressure of 1 × 10 ⁻⁵ Pa to 1 × 10 ² Pa. Reactive gas is supplied to the inner space of the dielectric container 31 by a gas supply device. Silane gas, nitrogen gas, etc. are used as reactive gas.

  The upper insulating plate 32 is provided inside the dielectric container 31 and between the dielectric container 31 and the plasma excitation coil 34. The upper insulating plate 32 can electrically insulate the space inside the dielectric container 31 from the plasma excitation coil 34. The upper insulating plate 32 is a substantially flat plate-shaped insulator. In the present embodiment, the upper insulating plate 32 is formed in a substantially disc shape.

  In this embodiment, a spiral antenna that is a planar spiral antenna is used as the plasma excitation coil 34. The plasma excitation coil 34 is formed of a conductive material such as copper, for example. An AC power supply 35 is electrically connected to the plasma excitation coil 34 via an impedance matching unit (not shown). The AC power supply 35 is connected to both ends of the plasma excitation coil 34. The AC power source 35 can supply AC power, for example, high frequency AC power of 13.56 MHz to the plasma excitation coil 34. By supplying AC power to the plasma excitation coil 34 by the AC power source 35, the plasma 36 can be generated in the space inside the dielectric container 31. The plasma excitation coil 34 is not limited to the spiral antenna, but may be any coil that can generate the plasma 36 in the inner space of the dielectric container 31.

  The mounting electrode 33 is provided inside the dielectric container 31 so as to face the upper insulating plate 32. The mounting electrode 33 and the upper insulating plate 32 are disposed in parallel to each other in the inner space of the dielectric container 31. The mounting electrode 33 is a substantially flat conductor. In the present embodiment, the placement electrode 33 is formed in a substantially disc shape. The mounting electrode 33 is formed on the flat one surface portion so that the semiconductor device forming member 1 can be mounted via the support 2.

  The mounting electrode 33 is electrically grounded via the impedance matching unit 37 and the AC power source 38. The AC power source 38 can supply AC power, for example, high-frequency AC power such as 13.56 MHz, to the mounting electrode 33 via the impedance matching unit 37. By supplying AC power to the mounting electrode 33 in this way, a voltage can be applied to the plasma 36 generated in the inner space of the dielectric container 31. Thereby, charged particles such as ions and electrons in the plasma 36 can be uniformly drawn into the semiconductor device forming member 1 side.

  In the case of a capacitively coupled plasma CVD apparatus, plasma is excited by a pair of electrodes provided opposite to each other. In this case, one of the pair of electrodes is used as the placement electrode 33.

  When the above-described passivation film is formed using the plasma CVD apparatus 30, first, the semiconductor device forming member 1 is mounted on the mounting electrode 33 via the support 2. Next, the space inside the dielectric container 31 is evacuated to a vacuum state, and then a reactive gas is supplied and stored inside the dielectric container 31. The pressure of the reactive gas at this time is 0.01 Pa or more and 100 Pa or less, for example.

  Next, AC power, for example, high frequency AC power of 13.56 MHz, 10 W or more and 5000 W or less is supplied from the AC power source 35 to the plasma excitation coil 34 to generate a magnetic field in the plasma excitation coil 34. As a result, an eddy current in the circumferential direction of the upper insulating plate 32 is generated in the vicinity of the upper insulating plate 32 inside the dielectric container 31, and discharge is started. By this discharge, energy is given to the reactive gas introduced into the dielectric container 31, collision of gas molecules in the reactive gas occurs, and the reactive gas is changed from the state of only the gas molecules to the gas molecules, A plasma state in which electrons, radicals and ions are mixed is reached, and plasma 36 is generated.

  Active species in the generated plasma 36, that is, charged particles such as electrons, radicals, and ions, are attracted to the semiconductor device forming member 1 side by a voltage applied from the mounting electrode 33 and react with the back surface 17 of the semiconductor substrate 11. Then, this reaction product is deposited on the back surface 17 of the semiconductor substrate 11. Thereby, a thin film having a desired thickness can be formed on the back surface 17 of the semiconductor substrate 11.

  Thus, when film-forming using the plasma CVD apparatus 30, the semiconductor device formation member 1 is supported by the support body 2 which has electroconductivity via the shorting conductor 3, Therefore The semiconductor device formation member 1 The semiconductor substrate 11 and the through electrode 12 are short-circuited. Therefore, the semiconductor substrate 11 and the through electrode 12 have the same potential even when they are charged by being exposed to charged particles such as ions and electrons contained in the plasma 36.

  FIG. 5 is an equivalent circuit diagram around the semiconductor device forming member 1 in the plasma CVD apparatus 30 shown in FIG. In FIG. 5, point A represents the potential of the through electrode 12, point B represents the potential of the semiconductor substrate 11, and point C represents the potential of the plasma 36. R 1 represents an equivalent resistance component between the through electrode 12 and the plasma 36, R 2 represents an equivalent resistance component between the semiconductor substrate 11 and the plasma 36, and R 3 represents between the through electrode 12 and the semiconductor substrate 11. Represents a resistance component of the sidewall insulating film 13 provided in Actually, in addition to the resistance component, between the plasma 36 and the through electrode 12, between the plasma 36 and the semiconductor substrate 11, and between the through electrode 12 and the semiconductor substrate 11, a capacitive component and an inductive component. However, in FIG. 5, for the convenience of explanation, only the resistance component is shown.

  In the present embodiment, the semiconductor substrate 11 and the through electrode 12 are short-circuited via the short-circuiting conductor 3 and the support 2. That is, conduction is made between A and B. Since the semiconductor substrate 11 and the through electrode 12 are formed of different materials, there is a difference in the amount of charge that is charged on the surface when exposed to charged particles in the plasma 36, but conduction between A and B occurs. Therefore, the potential of the through electrode 12 represented by the point A is equal to the potential of the semiconductor substrate 11 represented by the point B. As a result, it is possible to prevent a potential difference from occurring between the through electrode 12 and the semiconductor substrate 11, so that the dielectric breakdown of the sidewall insulating film 13 can be prevented. In particular, when an anisotropic conductive sheet or anisotropic conductive paste is used as the short-circuiting conductor 3, the short-circuit between the through electrode 12 and the semiconductor substrate 11 can be more reliably performed. Can be further suppressed.

  The through electrode 12 is electrically connected to a gate electrode of an active element such as an FET provided in an internal circuit of the semiconductor substrate 11. For this reason, since the semiconductor substrate 11 and the gate electrode can be set to the same potential by short-circuiting the through electrode 12 and the semiconductor substrate 11, the gate insulating film provided between the semiconductor substrate 11 and the gate electrode It is also possible to prevent dielectric breakdown. Therefore, it is not necessary to form a protective diode between the through electrode 12 and an active element such as an FET, so that the degree of freedom in design is improved and signal delay due to the parasitic capacitance of the protective diode can be prevented.

  As described above, by performing plasma CVD in a state where the semiconductor substrate 11 and the through electrode 12 are short-circuited, dielectric breakdown of the sidewall insulating film 13 and the gate insulating film can be prevented. This effect is not limited to plasma CVD, but is also exhibited in other plasma processes such as plasma etching.

  In the present embodiment, the semiconductor device forming member 1 is supported by the support 2 having rigidity, and the semiconductor substrate 11 is not warped even after the conductive member exposing step described above. In the process, the plasma processing can be performed uniformly over the entire surface to be processed of the semiconductor device forming member 1. For example, when forming a passivation film using the plasma CVD apparatus 30, it is possible to form a passivation film having a uniform thickness over the entire back surface 17 of the semiconductor substrate 11 that is the surface to be processed of the semiconductor device forming member 1. In-plane uniformity of the semiconductor substrate 11 can be improved.

  In this manner, the plasma processing is performed on the semiconductor device forming member 1, and the process proceeds from step s4 to step s5. In step s5 which is a peeling process, the semiconductor device forming member 1 and the support 2 are peeled off by removing the short-circuiting conductor 3. As a result, the semiconductor substrate 11 and the through electrode 12 return to a state where they are electrically insulated by the sidewall insulating film 13, so that the circuit operation can be performed without any trouble. As described above, in the present embodiment, the semiconductor substrate 11 and the through electrode 12 can be easily returned to the original insulating state only by removing the short-circuiting conductor 3 without using a method such as plasma etching. it can. In this way, the semiconductor substrate 11 and the through electrode 12 are returned to the insulated state, and the semiconductor device forming member 1 is separated into pieces as necessary to obtain a semiconductor device. The process proceeds from step s5 to step s6, and the semiconductor device is manufactured. Ends.

  The peeled semiconductor device forming member 1 and the support 2 can be electrically connected again via the short-circuiting conductor 3. That is, in this embodiment, even if it is necessary to short-circuit the semiconductor substrate 11 and the through electrode 12 again due to a design change or the like, the semiconductor substrate 11 and the through electrode 12 can be easily short-circuited. Therefore, it is possible to efficiently deal with design changes and the like.

  In the present embodiment, since a conductive adhesive sheet or conductive adhesive containing a UV peelable adhesive is used as the short-circuiting conductor 3, the short-circuiting conductor 3 irradiates ultraviolet rays through the support 2. Can be easily peeled off or removed.

  In the case of using a conductive adhesive that does not include a UV peelable adhesive, the short-circuiting conductor 3 is prepared by dissolving the conductive adhesive with a resin-soluble solvent such as a mixture of halogenated hydrocarbon and propylene glycol. Can be removed. When the conductive adhesive remains on the semiconductor device forming member 1, the remaining conductive adhesive can be removed by polishing or the like.

  When a conductive adhesive sheet is used as the short-circuiting conductor 3, it can be easily peeled from the semiconductor device forming member 1 even if it is not configured as a UV peelable adhesive tape. That is, the semiconductor device forming member 1 and the support 2 can be peeled only by peeling from the semiconductor device forming member 1. Therefore, since it is not necessary to use methods such as dissolution and polishing, working efficiency can be improved by using a conductive adhesive sheet. However, as in this embodiment, it is preferable to use a UV peelable pressure-sensitive adhesive tape because it can be easily peeled off and the adhesive remains on the semiconductor device forming member 1.

  FIG. 6 is a cross-sectional view showing a simplified configuration of the support 4 used in the method for manufacturing a semiconductor device according to another embodiment of the present invention. In this embodiment, the semiconductor device forming member 1 is supported by the support 4 via the short-circuiting conductor 3 and used for the plasma processing step. The support 4 is similar to the support 2 used in the above-described embodiment, and corresponding portions are denoted by the same reference numerals and description thereof is omitted.

  What should be noted in the support 4 is that a support-side conductor 41 is provided on the entire surface of the support body 21. The support-side conductor 41 is formed by depositing a UV transmissive conductive film such as ITO on the entire surface of the support body 21 using a film forming apparatus such as a vapor deposition apparatus that is easy to wrap in the lateral direction. be able to.

  The support 4 is electrically connected to the exposed portion 11a of the semiconductor substrate 11 and the exposed portion of the through electrode 12 of the semiconductor device forming member 1 through the short-circuiting conductor 3 in the same manner as the support 2 described above. . As a result, the semiconductor substrate 11 and the through electrode 12 are short-circuited via the support 4 and the short-circuiting conductor 3.

  Further, the support 4 is formed on the surface 21 b of the support body 21 on the side opposite to the surface 21 a that supports the semiconductor device forming member 1, and is connected to the surface 21 a on the side that supports the semiconductor device forming member 1. Since the support side conductor 41 is provided, the plasma CVD apparatus 30 shown in FIG. 4 is electrically connected to the placement electrode 33 when placed on the placement electrode 33. In this state, plasma processing such as plasma CVD is performed.

  FIG. 7 is a cross-sectional view schematically showing a state in which the support 4 shown in FIG. 6 is used in the plasma CVD apparatus 30. The support 4 is mounted on the mounting electrode 33 such that the surface 21 b opposite to the surface 21 a of the support body 21 that supports the semiconductor device forming member 1 faces the mounting electrode 33. used. As a result, the support-side conductor 41 of the support 4 is short-circuited with the placement electrode 33. Since the support-side conductor 41 is electrically connected to the semiconductor substrate 11 and the through electrode 12 via the short-circuit conductor 3, the semiconductor substrate 11, the through-electrode 12, and the placement electrode 33 are connected to the support-side conductor. Shorted through the body 41. Therefore, the semiconductor substrate 11 and the through electrode 12 and the placement electrode 33 have the same potential.

  As a result, it is possible to prevent the potential of the semiconductor substrate 11 and the through electrode 12 from becoming larger or smaller than the potential of the mounting electrode 33, so that charged particles such as ions and electrons in the plasma 36 are formed by the mounting electrode 33. Can be prevented from changing. Therefore, stable plasma treatment is possible.

  That is, as in this embodiment, the semiconductor substrate 11 and the through electrode 12 are formed by performing plasma treatment while the semiconductor substrate 11 and the through electrode 12 are electrically connected to the mounting electrode 33 through the support 4. 12 can be set to the same potential, and the semiconductor substrate 11, the through electrode 12, and the placement electrode 33 can be set to the same potential. Therefore, the dielectric breakdown of the sidewall insulating film 13 between the semiconductor substrate 11 and the through electrode 12 can be prevented, and the change in the potential of the mounting electrode 33 can be suppressed to perform stable plasma processing.

  As a support body that can perform plasma treatment in a state where the semiconductor substrate 11 and the through electrode 12 are electrically connected to the mounting electrode 33, a support body that has conductivity as a whole can be used. However, as in this embodiment, it is more conductive without increasing the cost by forming the support-side conductor 41 on the entire surface of the support body 21 made of an insulating material to form the support 4. It is preferable because an excellent support can be realized.

  Even when the support 2 shown in FIG. 1 is used, the semiconductor substrate 11 and the through electrode 12 and the mounting electrode 33 can be electrically connected. In this case, the surface portion of the support 2 facing the semiconductor device forming member 1 is formed to be larger than the surface portion of the semiconductor device forming member 1 facing the support 2, that is, the device forming surface 16 of the semiconductor substrate 11. The end or peripheral edge of the support-side conductor 22 is fixed to the mounting electrode 33 with a conductive clamp. However, the semiconductor substrate 11, the through electrode 12, and the mounting electrode 33 are electrically connected to the mounting electrode 33 over the entire surface of the supporting body side conductor 41 as in the present embodiment. It is preferable because it is possible to improve the electrical connection with.

It is sectional drawing which simplifies and shows the structure of the support body 2 on which the semiconductor device formation member 1 used for the manufacturing method of the semiconductor device which is one aspect | mode of this invention and the semiconductor device formation member 1 are supported. It is a flowchart which shows the procedure which manufactures a semiconductor device with the manufacturing method of the semiconductor device of this embodiment. It is a fragmentary sectional view which simplifies and shows the state after completion | finish of a semiconductor device formation member preparation process. It is sectional drawing which simplifies and shows the structure of the ICP type CVD apparatus 30 used at a plasma CVD step. FIG. 5 is an equivalent circuit diagram around the semiconductor device forming member 1 in the plasma CVD apparatus 30 shown in FIG. 4. It is sectional drawing which simplifies and shows the structure of the support body 4 used for the manufacturing method of the semiconductor device which is the other aspect of implementation of this invention. It is sectional drawing which simplifies and shows a mode that the support body 4 shown in FIG. 6 is used with the plasma CVD apparatus 30. FIG. It is sectional drawing which simplifies and shows the structure of the support body 101 which supports the semiconductor device formation member 100 and semiconductor formation member 100 for forming the semiconductor chip with which the laminated semiconductor integrated circuit device by a prior art is equipped. It is sectional drawing which simplifies and shows the structure of the plasma CVD apparatus 110 used by a prior art. FIG. 10 is an equivalent circuit diagram around the semiconductor device forming member 100 in the plasma CVD apparatus 110 shown in FIG. 9.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device formation member 2, 4 Support body 3 Conductor for short circuit 11 Semiconductor substrate 12 Through electrode 13 Side wall insulating film 14 Through electrode insertion hole 21 Support body main body 22,41 Support body side conductor 30 ICP type CVD apparatus 31 Dielectric container 32 Upper insulating plate 33 Mounting electrode 34 Plasma excitation coil 35, 38 AC power source 36 Plasma 37 Impedance matching device

Claims (6)

A semiconductor substrate in which at least a part of the surface portion on one side in the thickness direction is exposed, a substrate side electrode exposed on the surface portion side of the semiconductor substrate, and the semiconductor substrate and the substrate side electrode provided between the semiconductor substrate and the substrate side electrode A semiconductor device manufacturing method for manufacturing a semiconductor device using a semiconductor device forming member including an insulator that electrically insulates the semiconductor device,
For a short circuit by electrically connecting a portion of the semiconductor device forming member where the semiconductor substrate and the substrate side electrode are exposed to each other through a short circuit conductor to a rigid and conductive support. A short-circuiting step of short-circuiting the semiconductor substrate and the substrate-side electrode via the conductor and the support;
A plasma processing step of performing plasma processing on the semiconductor device forming member;
A method for manufacturing a semiconductor device, comprising: a peeling step of peeling the semiconductor device forming member and the support by removing the short-circuiting conductor. In the plasma treatment process,
2. The plasma treatment is performed by generating plasma in a state where the support is electrically connected to a mounting electrode for supporting a semiconductor device forming member and applying a voltage to the plasma. Semiconductor device manufacturing method. The support is transparent to UV light,
The short-circuiting conductor includes an ultraviolet peelable adhesive whose adhesive strength is reduced by ultraviolet irradiation,
In the peeling process,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device forming member and the support are peeled off by irradiating the short-circuiting conductor with ultraviolet rays through the support.   The semiconductor device manufacturing method according to claim 1, wherein the short-circuiting conductor is a conductive adhesive or a conductive adhesive sheet.   The method for manufacturing a semiconductor device according to claim 1, wherein the short-circuiting conductor is an anisotropic conductive paste or an anisotropic conductive sheet. A semiconductor substrate in which at least a part of the surface portion on one side in the thickness direction is exposed, a substrate side electrode exposed on the surface portion side of the semiconductor substrate, and the semiconductor substrate and the substrate side electrode provided between the semiconductor substrate and the substrate side electrode A support for performing a plasma treatment on a semiconductor device forming member including an insulator that electrically insulates,
Have rigidity and conductivity,
A support body for supporting a semiconductor device forming member by electrically connecting portions of the semiconductor device forming member where the semiconductor substrate and the substrate side electrode are exposed via a short-circuiting conductor.

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