CN100536259C - Method for producing microconnector - Google Patents
Method for producing microconnector Download PDFInfo
- Publication number
- CN100536259C CN100536259C CNB2006100827310A CN200610082731A CN100536259C CN 100536259 C CN100536259 C CN 100536259C CN B2006100827310 A CNB2006100827310 A CN B2006100827310A CN 200610082731 A CN200610082731 A CN 200610082731A CN 100536259 C CN100536259 C CN 100536259C
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- CN
- China
- Prior art keywords
- wafer
- dielectric layer
- adhesion layer
- pattern
- thinning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 7
- 238000005516 engineering process Methods 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 7
- 239000002390 adhesive tape Substances 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000003486 chemical etching Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000004033 plastic Substances 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 44
- 239000000463 material Substances 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000000227 grinding Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Images
Abstract
A process method for minisize commutator includes: form a dielectric layer on the premier surface of a wafer and fix the dielectric layer to a supporting wafer and thin the wafer; fix the secondary surface of the wafer to the supporting wafer and form a conducting pattern on the dielectric layer; form an insulation layer on the dielectric layer and the conducting pattern and remove parts of the insulation layer to expose the conducting pattern; cut parts of dielectric layer and wafer to make them into minisize commutator.
Description
Technical field
The present invention relates to a kind of method of making micro connector, particularly relate to a kind of in advance wafer is thinned to predetermined thickness after, so the method for making wire pattern again is the pollution problem that can effectively avoid the wafer thinning to be caused.
Background technology
With regard to the development trend of present electronic product, the multifunction of electronic product has become main direction with microminiaturization, and its multi-functional performance often needs can reach in conjunction with the running of a plurality of chips, yet the connection between each chip is reached if see through the circuit office of joining of printed circuit board (PCB), certainly will cause the increase of the volume of electronic product, therefore present packaged type all (system in package, carry out towards system in package by direction SIP).The main notion of system in package utilizes connector to be media, a plurality of desires are integrated the also interconnected chip installing of application thereon, and said chip and connector be packaged into system packaging structure in the lump, then utilize the inner set wire pattern of connector to be electrically connected between each chip.
Because the size of connector can influence the volume of system packaging structure, the method of therefore existing making connector is behind the wire pattern of producing connector inside, can carry out the thickness of grinding technics to connector with the reduction connector, and then the volume of reduction system packaging structure.Yet this practice can increase the contaminated probability of wire pattern, and reduces process yield.
Summary of the invention
One of purpose of the present invention is to provide a kind of method of making the high density micro connector, with the volume of reduction system packaging structure.
For reaching above-mentioned purpose, the invention provides a kind of method of making micro connector.The method according to this invention at first provides wafer, and this wafer comprises first surface and second surface.Then on this first surface of this wafer, form dielectric layer, and utilize first adhesion layer to engage this dielectric layer and bearing wafer.Carry out thinning technology subsequently, this this wafer of second surface thinning by this wafer removes this first adhesion layer again, and will utilize second adhesion layer to engage this second surface and this bearing wafer of this wafer.Then on this dielectric layer, form wire pattern, and on this dielectric layer and this wire pattern, form insulating barrier.Form shielding pattern then on this insulating barrier, this shielding pattern comprises a plurality of first openings corresponding to this wire pattern, and a plurality of second openings that define the Cutting Road pattern.Remove this insulating barrier that described first opening exposes subsequently, exposing this wire pattern, and remove this insulating barrier, this dielectric layer and this wafer that this second opening is exposed, make this wafer be divided into a plurality of micro connectors.Remove this shielding pattern at last again, and this second adhesion layer.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 to Figure 16 makes the method schematic diagram of micro connector for one embodiment of the present invention.
The simple symbol explanation
10 wafers, 12 first surfaces
14 second surfaces, 16 dielectric layers
18 first adhesion layers, 20 bearing wafers
22 second adhesion layers, 24 conductive layers
26 shielding pattern, 28 wire patterns
30 insulating barriers, 32 shielding pattern
34 first openings, 36 second openings
38 micro connectors
Embodiment
Please refer to Fig. 1 to Figure 16.Fig. 1 to Figure 16 makes the method schematic diagram of micro connector for one embodiment of the present invention.As shown in Figure 1, at first provide wafer 10, for example silicon wafer, and wafer 10 comprises first surface 12 and second surface 14.As shown in Figure 2, on the first surface 12 of wafer 10, form dielectric layer 16.In the present embodiment, the oxide layer that dielectric layer 16 forms for the thermal oxidation mode, it acts on provides insulation effect, and avoiding leakage problem, the generation type and the material of right dielectric layer 16 are not limit, and for example can be deposited oxide layer or are made of other insulating material.
As shown in Figure 3, the second surface 14 of wafer 10 is carried out preliminary (preliminary) thinning technology, for example utilize corase grind (grinding) mode under the prerequisite that does not cause wafer 10 to damage, the thickness of wafer 10 is reduced to suitable thickness rapidly.As shown in Figure 4, then utilize first adhesion layer 18 to engage dielectric layer 16 and bearing wafer 20, wafer 10 is fixed on the bearing wafer 20.In the present embodiment, bearing wafer 20 can be silicon wafer, chip glass, quartz wafer or plastic substrate.First adhesion layer 18 selects for use heat to discharge adhesive tape or ultraviolet tape, its advantage is that heat discharges adhesive tape or ultraviolet tape can utilize the mode of heating or irradiation ultraviolet radiation to be removed easily in subsequent technique, but first adhesion layer 18 is not limited to use above-mentioned material, and also can be as photoresist, cured or polyimides materials such as (polyimide).
As shown in Figure 5, then carry out thinning technology, by the second surface 14 comprehensive ground chip thinnings 10 of wafer 10.The final thickness demand of the visual wafer 10 of thinning technology, surface characteristic demand and stress consideration etc. and adopt diverse ways to carry out.For instance, can utilize comprehensive ground of plasma etch process chip thinning 10, reduce previous thus because the corase grind stress that technology produced, or the demands of utilizing chemical etching process erosion that the second surface 14 of wafer 10 is satisfied for surface roughness, also or utilize grinding and polishing (polish) technology to make the second surface 14 of wafer 10 have required surface flatness.Certainly, thinning technology does not limit the above-mentioned arbitrary mode of independent use, and visual actual state is carried out the combination of above-mentioned technology, or uses other thinning technology, for example chemico-mechanical polishing (CMP) technology.
As shown in Figure 6, after thinning technology finished, the thickness of wafer 10 and surface characteristic can meet the specification requirement of connector.As shown in Figure 7, then remove first adhesion layer 18, and utilize the second surface 14 and bearing wafer 20 of second adhesion layer, 22 joint wafers 10.Similarly, second adhesion layer 22 can select for use heat to discharge materials such as adhesive tape, ultraviolet tape, photoresist, cured or polyimides.As shown in Figure 8, then on dielectric layer, form conductive layer 24, on conductive layer 24, form shielding pattern 26 again.Conductive layer 24 can be any electrical excellent material, for example aluminium, gold or silver etc., and utilize and electroplate or modes such as deposition are formed, shielding pattern 26 then can be the photoresist pattern.
As shown in Figure 9, then utilize shielding pattern 26 as etching mask, etching conductive layer 24 to be forming wire pattern 28, as the usefulness of the connection line and the connection gasket of connector inside.As shown in figure 10, remove shielding pattern 26, and then on dielectric layer 16 and wire pattern 28, form insulating barrier 30.The material of insulating barrier 30 can be silica, silicon nitride, silicon oxynitride, benzocyclobutene (Benzocyclobutene, BCB) or polyimides etc., and different and utilize modes such as deposition or coating to be formed according to material.
As shown in figure 11, on insulating barrier 30, form shielding pattern 32, for example photoresist pattern.Shielding pattern 32 comprises a plurality of first openings 34 corresponding to wire pattern 28, and a plurality of second openings 36 that define the Cutting Road pattern.As shown in figure 12, the insulating barrier 30 that etching first opening 34 exposes, exposing wire pattern 28, and the insulating barrier 30 and dielectric layer 16 that expose of etching second opening 36 in the lump.Subsequently as shown in figure 13, utilize the direct eating thrown wafer 10 of dark etching technique via second opening 36, this moment, wafer 10 was split into a plurality of micro connectors 38, but still was fixed on the bearing wafer 20 by second adhesion layer 22.
As shown in figure 14, remove shielding pattern 32 from the surface of insulating barrier 30.As shown in figure 15, the first surface 12 from wafer 10 removes second adhesion layer 22.As shown in figure 16, promptly produce micro connector 38 of the present invention.
In sum, the method utilization heat that the present invention makes micro connector discharges adhesive tape or ultraviolet tape and can effectively avoid the wire pattern that completes impaired in subsequent technique as the practice of adhesion layer, and its characteristic that easily removes also can effectively avoid wafer impaired after thinning simultaneously.In addition, the present invention utilizes preliminary thinning technology that the thickness of wafer is reduced rapidly earlier, and further be reduced to final thickness by thinning technology, make the surface of wafer have the surface characteristic of being desired simultaneously, on wafer, produce the wire pattern that provides chip chamber to communicate with each other again, issuable pollution problem in the time of therefore chip thinning can being avoided.Moreover thinning technology also can be eliminated the stress that produces in the preliminary thinning technology, and then avoids wafer to produce problems such as warpage.In addition, in the process of exposed leads pattern, can utilize dark etching technique to carry out cutting technique in the lump, not only can save clipping time, also can reduce the area of Cutting Road and improve the density that is installed in the chip on the wafer.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (11)
1, a kind of method of making micro connector comprises:
Wafer is provided, and described wafer comprises a first surface and a second surface;
On the described first surface of described wafer, form dielectric layer;
Utilize first adhesion layer to engage described dielectric layer and bearing wafer;
Carry out thinning technology, by the described wafer of described second surface thinning of described wafer;
Remove described first adhesion layer, and will utilize second adhesion layer to engage the described second surface and the described bearing wafer of described wafer;
On described dielectric layer, form wire pattern;
On described dielectric layer and described wire pattern, form insulating barrier;
Form shielding pattern on described insulating barrier, described shielding pattern comprises a plurality of first openings corresponding to described wire pattern, and a plurality of second openings that define the Cutting Road pattern;
Remove the described insulating barrier that described first opening exposes, exposing described wire pattern, and remove described insulating barrier, described dielectric layer and described wafer that described second opening is exposed, make described wafer be divided into a plurality of micro connectors;
Remove described shielding pattern; And
Remove described second adhesion layer.
2, the method for claim 1, wherein said dielectric layer are oxide layer.
3, the method for claim 1, wherein said first adhesion layer comprise that heat discharges adhesive tape or ultraviolet tape.
4, the method for claim 1, wherein said bearing wafer comprises silicon wafer, chip glass, quartz wafer or plastic substrate.
5, the method for claim 1 also is included in and utilizes described first adhesion layer to engage before described dielectric layer and the described bearing wafer, and the described second surface to described wafer carries out preliminary thinning technology earlier.
6, method as claimed in claim 5, wherein said preliminary thinning technology comprises corase grind technology.
7, the method for claim 1, wherein said thinning technology comprises plasma etch process.
8, the method for claim 1, wherein said thinning technology comprises chemical etching process.
9, the method for claim 1, wherein said thinning technology comprises abrasive polishing process.
10, the method for claim 1, wherein said second adhesion layer comprise that heat discharges adhesive tape or ultraviolet tape.
11, the method for claim 1 is wherein removed the dark etching technique of step utilization of the described wafer that described second opening exposed and is reached.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100827310A CN100536259C (en) | 2006-05-15 | 2006-05-15 | Method for producing microconnector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100827310A CN100536259C (en) | 2006-05-15 | 2006-05-15 | Method for producing microconnector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101075721A CN101075721A (en) | 2007-11-21 |
| CN100536259C true CN100536259C (en) | 2009-09-02 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100827310A Expired - Fee Related CN100536259C (en) | 2006-05-15 | 2006-05-15 | Method for producing microconnector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100536259C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847588B (en) * | 2009-03-27 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Semiconductor process |
| CN107705971A (en) * | 2017-08-30 | 2018-02-16 | 歌尔股份有限公司 | A kind of manufacture method of coil, coil, electronic equipment |
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2006
- 2006-05-15 CN CNB2006100827310A patent/CN100536259C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101075721A (en) | 2007-11-21 |
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Granted publication date: 20090902 Termination date: 20140515 |