CN110875207B

CN110875207B - Wafer level packaging method and packaging structure

Info

Publication number: CN110875207B
Application number: CN201811028264.2A
Authority: CN
Inventors: 罗海龙; 克里夫·德劳利
Original assignee: China Core Integrated Circuit Ningbo Co Ltd
Current assignee: China Core Integrated Circuit Ningbo Co Ltd
Priority date: 2018-09-04
Filing date: 2018-09-04
Publication date: 2021-05-07
Anticipated expiration: 2038-09-04
Also published as: CN110875207A

Abstract

A wafer level packaging method and a packaging structure are provided, the packaging method comprises the following steps: providing a device wafer, wherein the device wafer comprises a plurality of first chips, the first chips comprise first electrodes, the first electrodes are exposed out of the device wafer, and the surfaces of the device wafer, which are exposed out of the first electrodes, are the front surfaces of the device wafer; providing a bearing substrate, temporarily bonding a plurality of second chips on the bearing substrate, wherein the second chips comprise second electrodes, the second electrodes are exposed out of the second chips, the surfaces of the second chips, which are exposed out of the second electrodes, are front surfaces of the chips, and the surfaces, which are opposite to the front surfaces of the chips, are back surfaces of the chips; the back surface of the chip and the front surface of the wafer are oppositely arranged, and the back surface of the chip is bonded to the front surface of the wafer by adopting a fusion bonding process; performing debonding treatment on the second chip and the bearing substrate; forming an insulating side wall on the side wall of the second chip; and forming a conductive layer which conformally covers the front surface of the chip, the insulating side wall and the front surface of the wafer. The process for realizing the electrical connection is simple, the bonding strength of the device wafer and the second chip is high, and the electrical connection effect is ensured.

Description

Wafer level packaging method and packaging structure

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a wafer level package method and a package structure.

Background

With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), three-dimensional Package (3D), System In Package (SiP), and the like.

At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packaging, an advanced packaging method mainly adopts Wafer Level Package System In Package (WLPSiP), and compared with the conventional System packaging, the Wafer Level System packaging completes a packaging integration process on a Wafer, so that the Wafer Level System packaging has the advantages of greatly reducing the area of a packaging structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment.

Wafer level system packaging mainly includes two important processes of physical connection and electrical connection. Such as: the physical connection between the chip to be integrated and the wafer is realized by adopting a bonding process, the electrical connection between the semiconductor devices is realized by an electroplating technology, and the electrical connection between the chip and an external circuit is realized by a Through-Silicon Via (TSV).

However, the electrical connection method of the wafer level system package needs to be further simplified and the electrical connection effect needs to be improved.

Disclosure of Invention

The invention provides a wafer level packaging method and a packaging structure, which simplify the packaging process and improve the electrical connection effect.

To solve the above problems, the present invention provides a packaging method, comprising: providing a device wafer, wherein the device wafer comprises a plurality of first chips, the first chips comprise first electrodes, the first electrodes are exposed out of the device wafer, and the surfaces of the device wafer, which are exposed out of the first electrodes, are the front surfaces of the device wafer; providing a bearing substrate, temporarily bonding a plurality of second chips on the bearing substrate, wherein the second chips comprise second electrodes, the second electrodes are exposed out of the second chips, the surfaces of the second chips, which are exposed out of the second electrodes, are front surfaces of the chips, and the surfaces, which are opposite to the front surfaces of the chips, are back surfaces of the chips; enabling the back surface of the chip and the front surface of the wafer to be oppositely arranged, and enabling the back surface of the chip to be bonded to the front surface of the wafer by adopting a fusion bonding process; after bonding, performing bonding removal treatment on the second chip and the bearing substrate; after the bonding removing treatment, forming an insulating side wall on the side wall of the second chip; and forming a conductive layer which conformally covers the front surface of the chip, the insulating side wall and the front surface of the wafer.

Correspondingly, the invention also provides a wafer level packaging structure, which comprises: the device wafer comprises a plurality of first chips, the first chips comprise first electrodes, the first electrodes are exposed out of the device wafer, and the surfaces of the device wafer, which are exposed out of the first electrodes, are the front surfaces of the wafer; the second chips are bonded to the front side of the wafer through a fusion bonding process, the surfaces of the second chips bonded to the front side of the wafer are chip back surfaces, the surfaces opposite to the chip back surfaces are chip front surfaces, the second chips comprise second electrodes, and the second electrodes are exposed out of the chip front surfaces; the insulating side wall is positioned on the side wall of the second chip; and the conductive layer is covered on the front surface of the chip, the insulating side wall and the front surface of the wafer in a shape-preserving manner.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the invention adopts the fusion bonding process to bond the back surface of the second chip to the front surface of the wafer of the device wafer, so that the second chip and the device wafer have higher bonding strength, the reliability of the bonding process is improved, and the packaging yield is correspondingly improved; and after the fusion bonding process, forming an insulating side wall on the side wall of the second chip, and then forming a conductive layer which conformally covers the front surface of the chip, the insulating side wall and the front surface of the wafer, the conductive layer covers the front surface of the chip and is in contact with the second electrode on the front surface of the chip, the conductive layer also covers the front surface of the wafer and is in contact with the first electrode positioned on the front surface of the wafer, so that the first electrode and the second electrode are electrically connected, the invention can realize the electrical connection between the first chip and the second chip only by one conductive layer, has simple process, and the insulating side wall enables the conducting layer and the second chip to be mutually insulated, so that the influence of the conducting layer on the performance of the second chip is avoided.

Drawings

Fig. 1 to 9 are schematic structural diagrams corresponding to steps of an embodiment of a wafer level packaging method according to the present invention.

Detailed Description

As known from the background art, the electrical connection method of the front wafer level system package needs to be further simplified, and the electrical connection effect needs to be improved. The reason for this analysis is:

after the bare chip to be integrated is bonded to the device wafer, a first connection structure electrically connected to the bare chip, a second connection structure electrically connected to the chip in the device wafer, and an interconnection structure electrically connecting the first connection structure and the second connection structure need to be formed, so that the packaging process is complicated.

Moreover, the device wafer and the bare chip are usually physically connected through an adhesive layer (such as an adhesive film or a dry film), but the adhesive layer has poor temperature resistance, and when the process temperature in the subsequent process is too high, the adhesive layer is easily failed, so that the adhesiveness of the adhesive layer is reduced, and even the device wafer and the bare chip are peeled off, which seriously affects the electrical connection effect between the bare chip and the chip in the device wafer.

In order to solve the technical problem, the back surface of the second chip is bonded to the front surface of the wafer of the device wafer by adopting a fusion bonding process, so that the second chip and the device wafer have higher bonding strength, the reliability of the bonding process is improved, and the packaging yield is correspondingly improved; and after the fusion bonding process, forming an insulating side wall on the side wall of the second chip, and then forming a conductive layer which conformally covers the front surface of the chip, the insulating side wall and the front surface of the wafer, the conductive layer covers the front surface of the chip and is in contact with the second electrode on the front surface of the chip, the conductive layer also covers the front surface of the wafer and is in contact with the first electrode positioned on the front surface of the wafer, so that the first electrode and the second electrode are electrically connected, the invention can realize the electrical connection between the first chip and the second chip only by one conductive layer, has simple process, and the insulating side wall enables the conducting layer and the second chip to be mutually insulated, so that the influence of the conducting layer on the performance of the second chip is avoided.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 1, a device Wafer (CMOS Wafer)300 is provided, the device Wafer 300 includes a plurality of first chips 310, the first chips 310 include first electrodes 320, the first electrodes 320 are exposed from the device Wafer 300, and a surface of the device Wafer 300, where the first electrodes 320 are exposed, is a Wafer front surface 301.

In this embodiment, the packaging method is used to implement wafer level system packaging, and the device wafer 300 is used to bond with a chip to be integrated in a subsequent process.

The device wafer 300 is a wafer on which device fabrication is completed. In this embodiment, the substrate of the device wafer 300 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

The device wafer 300 has a plurality of first chips 310 formed therein. In this embodiment, the plurality of first chips 310 may be chips of the same type or different types. It should be noted that the device wafer 300 may be manufactured by using an integrated circuit manufacturing technology, for example, NMOS devices, PMOS devices and other devices are formed on a substrate through deposition, etching and other processes, and dielectric layers, metal interconnection structures, pads (pads) electrically connected to the metal interconnection structures and other structures are formed on the devices, so that the plurality of first chips 310 are formed in the device wafer 300.

It should be noted that, for convenience of illustration, the device wafer 300 of the present embodiment is described by taking three first chips 310 as an example. The number of the first chips 310 is not limited to three.

In this embodiment, the first chip 310 includes a first electrode 320. Specifically, the first electrode 320 is a Bond Pad (Bond Pad) for electrically connecting the first chip 310 to other circuits.

In this embodiment, the first electrode 320 is exposed from the device wafer 300, a surface of the device wafer 300, on which the first electrode 320 is exposed, is a wafer front surface 301, and a surface opposite to the wafer front surface 301 is a wafer back surface 302. Wherein the wafer backside 302 refers to a bottom surface of the substrate of the device wafer 300 away from the first electrode 320.

Referring to fig. 2, a carrier substrate 10 is provided, a plurality of second chips 200 are temporarily bonded on the carrier substrate 10, the second chips 200 include second electrodes 210, the second electrodes 210 are exposed from the second chips 200, a surface of the second chip 200, where the second electrodes 210 are exposed, is a chip front surface 202, and a surface opposite to the chip front surface 202 is a chip back surface 201.

The second chips 200 are used as chips to be integrated in a wafer level system package, the number of the second chips 200 is at least one, and the number of the second chips 200 is the same as that of the first chips 310 (shown in fig. 1).

The second chip 200 may be one or more of (active element, passive element, micro electro mechanical system, optical element, etc.. specifically, the second chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip.

In this embodiment, the wafer level system package is used to combine a plurality of second chips 200 with different functions into one package structure, so that the second chips 200 are obtained by cutting a plurality of wafers with different function types. In other embodiments, the functional types of the plurality of second chips may also be the same according to actual process requirements.

By integrating the plurality of second chips 200 into the device wafer 300 (as shown in fig. 1) and completing the package integration process on the device wafer 300, the area of the package structure can be greatly reduced, the manufacturing cost can be reduced, the electrical performance can be optimized, the batch manufacturing can be optimized, and the workload and the equipment requirement can be significantly reduced.

It should be noted that the wafer level packaging method of the present embodiment is used to implement heterogeneous integration, and therefore the plurality of second chips 200 are chips made of silicon wafers. In other embodiments, the second chip may also be a chip formed by other materials.

It should be noted that, for convenience of illustration, only three second chips 200 are illustrated in the present embodiment. The number of the second chips 200 is not limited to three.

In this embodiment, the second chip 200 includes a second electrode 210. Specifically, the second electrode 210 is a lead pad for electrically connecting the second chip 200 to other circuits.

In this embodiment, the second electrode 210 is exposed from the second chip 200, a surface of the second chip 200, which is exposed from the second electrode 210, is a chip front surface 202, and a surface opposite to the chip front surface 202 is a chip back surface 201. Wherein the chip back side 201 refers to a bottom surface of the substrate of the second chip 200 away from the second electrode 210.

It should be noted that, in this embodiment, the chip back side 201 of the second chip 200 is a surface to be bonded, and is suitable for being bonded with the device wafer 300 (as shown in fig. 1).

The carrier substrate 10 is used for supporting the plurality of second chips 200, so that the subsequent process is facilitated, and the operability of the subsequent process is improved; and the subsequent separation of the second chip 200 and the carrier substrate 10 is also facilitated by means of Temporary Bonding (Temporary Bonding).

In this embodiment, the Carrier substrate 10 is a Carrier Wafer (Carrier Wafer). Specifically, the carrier substrate 10 may be a semiconductor substrate (e.g., a silicon substrate), an organic glass wafer, an inorganic glass wafer, a resin wafer, a semiconductor material wafer, an oxide crystal wafer, a ceramic wafer, a metal wafer, an organic plastic wafer, an inorganic oxide wafer, or a ceramic material wafer.

In this embodiment, since the chip back surface 201 of the second chip 200 is a surface to be bonded, the chip front surface 202 of the second chip 200 is temporarily bonded to the carrier substrate 100 through the adhesive layer 15. The adhesive layer 15 is used to temporarily bond the second chip 200 and the carrier substrate 10, so as to facilitate the subsequent separation of the second chip 200 and the carrier substrate 10.

In this embodiment, the adhesive layer 15 is a Die Attach Film (DAF). The adhesive film is an ultra-thin film adhesive used for connecting a semiconductor chip and a packaging substrate and connecting the chip and the chip in a semiconductor packaging process, has high reliability and convenient process performance, and is beneficial to realizing the lamination and thinning of the semiconductor packaging.

In other embodiments, the adhesive layer may also be a Dry Film (Dry Film), a UV glue, or a thermosetting glue.

The dry film is a sticky photoresist film used for semiconductor chip packaging or printed circuit board manufacturing, and the dry film photoresist is manufactured by coating solvent-free photoresist on a polyester film base and then coating a polyethylene film; when the dry film photoresist is used, the polyethylene film is uncovered, the solvent-free photoresist is pressed on the base plate, and a pattern can be formed in the dry film photoresist through exposure and development treatment.

The UV adhesive is also called ultraviolet curing adhesive, is a kind of adhesive which can be cured only by ultraviolet irradiation, has high curing speed, high bonding strength after curing and high environmental protection property.

The thermosetting adhesive is an adhesive taking thermosetting resin as a main component, has good performances such as solvent resistance, weather resistance and the like, is high in curing speed and high in bonding strength, and can be suitable for bonding of different surfaces according to different viscosities, curing times and additives.

It should be noted that, in other embodiments, the plurality of second chips may also be temporarily bonded to the carrier substrate by electrostatic bonding. Electrostatic bonding technology is a method of achieving bonding without any adhesive. In the bonding process, the second chip to be bonded and the bearing substrate are respectively connected with different electrodes, electric charges are formed on the surfaces of the second chip and the bearing substrate under the action of voltage, and the electric charges on the surfaces of the second chip and the bearing substrate are different, so that a larger electrostatic attraction is generated in the bonding process of the second chip and the bearing substrate, and the physical connection of the second chip and the bearing substrate is realized.

With continuing reference to fig. 1 and 2 and with combined reference to fig. 3 to 5, the chip back side 201 (shown in fig. 2) and the wafer front side 301 (shown in fig. 1) are disposed opposite to each other, and the chip back side 201 is bonded to the wafer front side 301 by using a fusion bonding process.

The fusion bonding is a process for completing bonding by mainly utilizing interfacial chemical force, so that the reliability of the bonding process is improved, the bonding strength of the second chip 200 and the device wafer 300 is further improved, the subsequent process has small influence on the bonding strength, and the packaging yield is correspondingly improved.

Correspondingly, for the fusion bonding process, the packaging method further comprises the following steps:

referring to fig. 1 and fig. 2 in combination, a first oxide layer 350 (shown in fig. 1) is formed on the front surface 301 (shown in fig. 1) of the wafer; a second oxide layer 250 (shown in fig. 2) is formed on the chip back side 201 (shown in fig. 2).

The first oxide layer 350 and the second oxide layer 250 serve as Bonding layers of a subsequent Fusion Bonding (Fusion Bonding) process, which are used for achieving physical connection between the device wafer 300 and the second chip 200 and enabling the device wafer 300 and the second chip 200 to have higher Bonding strength.

In this embodiment, the first oxide layer 350 is made of silicon oxide. By selecting the silicon oxide material, the device wafer 300 and the chip to be integrated can be bonded by a covalent bond of Si-O-Si, and the bond energy of the Si-O bond is large, so as to further improve the bonding strength between the device wafer 300 and the second chip 200; in addition, the silicon oxide material has higher process compatibility, and the silicon oxide is a material which is commonly used in the process and has lower cost, so the mode of selecting the silicon oxide material is favorable for reducing the process difficulty and the process cost and reducing the performance influence on the formed packaging structure. In other embodiments, the first oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide.

In this embodiment, the process of forming the first oxide layer 350 may be an atomic layer deposition process. Through an atomic layer deposition process, the first oxide layer 350 is formed on the front surface 301 of the wafer in an atomic layer manner, so that the uniformity of the deposition rate, the thickness uniformity of the first oxide layer 350 and the structural uniformity of the first oxide layer 350 are improved, and the first oxide layer 350 has good covering capability; in addition, the process temperature of the ald process is usually lower, so that the Thermal Budget (Thermal Budget) is also reduced, and the probability of Wafer deformation (Wafer deformation) and device performance deviation is reduced.

In other embodiments, the process of forming the first oxide layer may also be a low pressure chemical vapor deposition process, a metal organic chemical vapor deposition process, a physical vapor deposition process, or a laser pulse deposition process according to the material of the first oxide layer.

It should be noted that the first oxide layer 350 covers a portion of the front surface 301 of the wafer, and the first oxide layer 350 exposes the first electrode 320 of the first chip 310. After the device wafer 300 and the to-be-integrated chip are bonded, the first chip 310 and the to-be-integrated chip are electrically connected by conformally covering the wafer front surface 301 and the conductive layer of the to-be-integrated chip, so that the conductive layer can contact with the first electrode 320 by exposing the first oxide layer 350 to the first electrode 320 of the first chip 310.

In this embodiment, in order to reduce the difficulty in forming the subsequent conductive layer and improve the electrical connection effect between the conductive layer and the first electrode 320, the first oxide layer 350 is staggered from the first chip 310, and covers a part of the wafer front surface 301 in the corresponding region according to the predetermined relative position relationship between the subsequent chip to be integrated and the first chip 310. In other embodiments, the first oxide layer may further cover a portion of the first chip and expose the first electrode.

In this embodiment, the material of the second oxide layer 250 is the same as the material of the first oxide layer 350 (shown in fig. 1), so as to improve the bonding strength between the second chip 200 and the device wafer 300. Specifically, the material of the second oxide layer 250 is silicon oxide, and the process of forming the second oxide layer 250 is an atomic layer deposition process.

In other embodiments, the second oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide, and the process for forming the second oxide layer may also be a low pressure chemical vapor deposition process, a metal organic chemical vapor deposition process, a physical vapor deposition process, or a laser pulse deposition process.

For a detailed description of the second oxide layer 250, reference may be made to the foregoing description of the first oxide layer 350, and this embodiment is not repeated herein.

It should be noted that, since the plurality of second chips 200 can be obtained by cutting a plurality of wafers, in order to improve the forming efficiency and the forming quality of the second oxide layer 250, after the second oxide layer 250 covering the chip back surface 201 is formed on the plurality of wafers integrated with the second chips 200, the plurality of wafers formed with the second oxide layer 250 may be cut, so as to obtain the plurality of second chips 200 having the chip back surfaces 201 formed with the second oxide layer 250.

In this embodiment, after the second oxide layer 250 is formed on the chip back surface 201 of the second chip 200, the chip front surface 202 of the second chip 200 is temporarily bonded to the carrier substrate 10. Thereby facilitating a simplification of the process difficulty of forming the second oxide layer 250.

In other embodiments, according to actual process conditions, after the chip front side 202 of the second chip 200 is temporarily bonded to the carrier substrate 10, the second oxide layer may be formed on the surface to be bonded.

Therefore, referring to fig. 2 to 5 in combination, after the chip back surface 201 (shown in fig. 2) and the wafer front surface 301 (shown in fig. 1) are disposed opposite to each other, the chip back surface 201 is bonded to the wafer front surface 301 through the first oxide layer 350 (shown in fig. 1) and the second oxide layer 250 (shown in fig. 2) by using a fusion bonding process.

In the process of the fusion bonding process, unsaturated bonded Si atoms are formed on the surfaces of the first oxide layer 350 and the second oxide layer 250, and covalent bonding can be achieved, so that through the fusion bonding process, the contact surfaces of the first oxide layer 350 and the second oxide layer 250 are bonded in a covalent bonding manner, and the first oxide layer 350 and the second oxide layer 250 have high bonding strength, so that the reliability of the bonding process is improved, the bonding strength of the device wafer 300 and the second chip 200 is further improved, the influence of subsequent processes on the bonding strength is small, and the packaging yield is correspondingly improved.

Specifically, with combined reference to fig. 3 and 4, the steps of the fusion bonding process include: and carrying out plasma activation treatment 110 on the surface of the first oxidation layer 350 (shown in figure 3) and the surface of the second oxidation layer 250 (shown in figure 4).

On one hand, the contaminants, impurities, and the like on the surfaces of the first oxide layer 350 and the second oxide layer 250 are made into a gaseous state by the plasma activation treatment 110, and are exhausted by a vacuum pump of a plasma system, thereby performing a function of removing the contaminants and impurities, for example, metal contaminants and organic contaminants can be removed well. On the other hand, the plasma of the plasma activation process 110 collides with the surfaces of the first oxide layer 350 and the second oxide layer 250, and energizes unstable non-bridging oxygen atoms to move the oxygen atoms away from the original bonded atoms, thereby providing a good basis for the subsequent formation of covalent bonds at the contact surfaces of the first oxide layer 350 and the second oxide layer 250.

In this embodiment, the first oxide layer 350 and the second oxide layer 250 are made of silicon oxide, so that unsaturated bonded Si atoms are formed on the surfaces of the first oxide layer 350 and the second oxide layer 250 after the plasma activation treatment 110.

The reactive gas used in the plasma activation process 110 may include Ar and N₂、O₂And SF₆One or more of (a). In this embodiment, the reaction gas used in the plasma activation treatment 110 is O₂I.e. the plasma activation treatment 110 is oxygenAnd (5) performing plasma activation treatment.

Wherein, the rf power of the plasma activation treatment 110 should not be too small or too large. In the plasma activation process 110, electrons are accelerated by the radio frequency electric field generated by the radio frequency power source, and each electron collides with a reaction gas molecule to transfer kinetic energy, so that each reaction gas molecule is ionized to generate plasma.

If the radio frequency power is too low, the reaction gas is difficult to be converted into plasma, which is likely to cause the problems of insufficient plasma and poor plasma stability, so as to reduce the effect of the plasma activation treatment 110, and further reduce the bonding strength between the subsequent first oxide layer 350 and the subsequent second oxide layer 250; if the rf power is too high, the kinetic energy obtained after the reaction gas is turned into plasma is too high, the bombardment effect on the first oxide layer 350 and the second oxide layer 250 is correspondingly too strong, so that the surfaces of the first oxide layer 350 and the second oxide layer 250 are easily damaged, Micro-defects (Micro-defects) are formed on the surfaces of the first oxide layer 350 and the second oxide layer 250, annealing holes are easily generated after subsequent annealing treatment, the bonding strength between the first oxide layer 350 and the second oxide layer 250 is easily reduced, and the rf power is too high, and too much energy is consumed, thereby increasing the process cost.

For this reason, in the present embodiment, the rf power of the plasma activation process 110 is 20W to 200W.

The process pressure of the plasma activation treatment 110 should not be too low or too high. The process pressure affects the rf power, and the greater the process pressure, the shorter the mean free path of the plasma, and the greater the probability of collision between the plasmas, thereby causing the effect of the plasma activation processing 110 to be poor, and correspondingly, the higher the rf power required to ensure the effect of the plasma activation processing 110; in addition, when the process pressure is too small, the stability of the plasma is easily lowered, and accordingly, the higher the rf power required to suppress the plasma from being unstable.

To this end, in this embodiment, the process pressure is adjusted to a matching value range according to the rf power of the plasma activation process 110. In particular, the process pressure is between 0.1mBar and 10 mBar.

The treatment time of the plasma activation treatment 110 is not preferably too short, nor too long. If the processing time is too short, the effect of the plasma activation processing 110 is correspondingly deteriorated under the condition of certain radio frequency power and the flow rate of the reaction gas, thereby causing the bonding strength between the first oxide layer 350 and the second oxide layer 250 to be reduced; if the treatment time is too long, the surface of the first oxide layer 350 and the second oxide layer 250 is easily damaged, so that micro defects are formed on the surface of the first oxide layer 350 and the second oxide layer 250, and the treatment time is too long, so that an excessive amount of hydroxyl groups is generated, and an excessive amount of by-products (H) is easily generated after the subsequent annealing treatment₂O and H₂Etc.), thereby causing the generation of annealing voids, which in turn tends to decrease the bonding strength between the first oxide layer 350 and the second oxide layer 250, and further, the process cost increases due to the long process time. For this reason, in the present embodiment, the treatment time of the plasma activation treatment 110 is 0.1 minute to 10 minutes.

In this embodiment, the rf power, the process pressure, the flow rate of the reactive gas, and the processing time of the plasma activation processing 110 are set within a reasonable range and are matched with each other, so that the activation effect on the first oxide layer 350 and the second oxide layer 250 is improved while the processing efficiency and stability are improved and the process cost is reduced.

In this embodiment, the step of the fusion bonding process further includes: after the plasma activation treatment 110 (shown in fig. 3 and 4), performing a deionized water cleaning treatment on the surface of the first oxide layer 350 and the surface of the second oxide layer 250; after the deionized water pre-cleaning treatment, the surface of the first oxide layer 350 and the surface of the second oxide layer 250 are dried.

Through the deionized water cleaning treatment and the drying treatment, the surface quality of the first oxide layer 350 and the second oxide layer 250 is improved, and thus the bonding strength of the first oxide layer 350 and the second oxide layer 250 is improved.

Specifically, the surfaces of the first oxide layer 350 and the second oxide layer 250 are rinsed with deionized water, thereby completing the deionized water cleaning process; after the deionized water cleaning treatment, N is adopted₂The first and second oxide layers 350 and 250 are blow-dried, thereby completing the drying process.

Referring to fig. 5, in this embodiment, the step of the fusion bonding process further includes: after the drying process, the second oxide layer 250 and the first oxide layer 350 are oppositely disposed and attached according to the preset relative position relationship between the second chip 200 and the first chip 310, and a bonding pressure is applied to the device wafer 300 and the second chip 200 to perform a pre-bonding process 120.

After the plasma activation treatment 110, unsaturated bonded Si atoms are formed on the surfaces of the first oxide layer 350 and the second oxide layer 250, and thus the first oxide layer 350 and the second oxide layer 250 are bonded by interfacial chemical bonding through the pre-bonding treatment 120.

In this embodiment, after the second oxide layer 250 and the first oxide layer 350 are oppositely disposed and bonded according to actual process requirements, the second chips 200 are vertically corresponding to the corresponding first chips 310 one by one, projections of the second chips 200 and the first chips 310 on the first oxide layer 350 are staggered with each other, and bonding pressure is applied to the first back surface 302 of the device wafer 300 and the surface of the carrier substrate 100 opposite to the second chip 200, so as to perform the pre-bonding process 120.

The mode of temporarily bonding the second back surfaces 202 of the second chips 200 to the carrier substrate 100 and then performing the pre-bonding process 120 is favorable for improving the stress uniformity of the plurality of second chips 200, and compared with the scheme of directly applying bonding pressure to the second chips 200, the mode of performing the pre-bonding process 120 is favorable for reducing the damage of the pre-bonding process 120 to the second chips 200.

It should be noted that, although increasing the bonding pressure of the pre-bonding process 120 is beneficial to improving the chemical bond effect and strength at the interface between the first oxide layer 350 and the second oxide layer 250, if the bonding pressure is too high, adverse effects, such as deformation, may be easily caused on the device wafer 300, the first oxide layer 350, the second oxide layer 250, and the second chip 200. For this reason, in the present embodiment, in order to reduce the process risk while the first oxide layer 350 and the second oxide layer 250 effectively achieve the interfacial chemical bond connection, the bonding pressure of the pre-bonding treatment 120 is 1 newton to 20 newton.

It should be noted that, although increasing the processing time of the pre-bonding process 120 is also beneficial to improve the chemical bond connection effect and strength of the contact surface between the first oxide layer 350 and the second oxide layer 250, if the processing time is too long, the processing time will be wasted and the efficiency will be reduced. For this reason, in the present embodiment, in order to improve the process efficiency while the first oxide layer 350 and the second oxide layer 250 effectively achieve the interfacial chemical bond connection, the processing time of the pre-bonding treatment 120 is 1 second to 60 seconds.

In this embodiment, the step of the fusion bonding process further includes: after the pre-bonding process 120, an annealing process is performed on the device wafer 300 and the second chip 200.

By the annealing treatment, dehydration condensation reaction occurs on the contact surface of the first oxide layer 350 and the second oxide layer 250, so that the first oxide layer 350 and the second oxide layer 250 form Si-O-Si covalent bond; the bonding strength between the first oxide layer 350 and the second oxide layer 250 is improved due to the larger bonding energy of the silicon-oxygen bond.

Wherein, the process temperature of the annealing treatment is not suitable to be too low or too high. If the process temperature is too low, the effect of dehydration condensation reaction is easily reduced, which is not beneficial to improving the bonding strength of the first oxide layer 350 and the second oxide layer 250; if the process temperature is too high, the performance of the devices formed in the device wafer 300 and the second chip 200 may be adversely affected. For this reason, in this embodiment, the process temperature of the annealing treatment is 200 ℃ to 500 ℃.

In this embodiment, the annealing process has a lower process temperature, and thus, the influence on the performance of the devices formed in the device wafer 300 and the second chip 200 is also reduced.

The process time of the annealing treatment is not too short or too high. If the process time is too short, it is difficult to sufficiently complete the dehydration condensation reaction, thereby being disadvantageous to improve the bonding strength of the first and second oxide layers 350 and 250; if the process time is too long, the process time is wasted, and the efficiency is reduced, and the risk of the process is increased when the device wafer 300 and the second chip 200 are placed in the annealing environment for a long time. For this reason, in this embodiment, the process time of the annealing treatment is 20 minutes to 200 minutes.

In this embodiment, the process temperature and the process time of the annealing treatment are set within a reasonable range and are matched with each other, so that the bonding strength is improved and the probability of side effects is reduced.

It should be noted that, because the number of the second chips 200 is multiple and discrete, in the process of the fusion bonding process, the carrier substrate 100 is used to support the multiple second chips 200, so as to reduce the probability of the second chips 200 falling off and facilitate the performance of the fusion bonding process.

It should be noted that in other embodiments, the bonding may also be implemented in other manners, such as: adhesive bonding or glass dielectric bonding.

Specifically, the bonding temperature of the adhesive bonding is low and compatible with CMOS; so that the wafer is bonded in the heterogeneous integration process. Specifically, the adhesive bonding process comprises: forming an adhesive, typically a polymer, on a bonding face of a chip and the wafer; (ii) bringing the binder in an unpolymerized or partially polymerized state by soft-baking or pre-curing the polymer; and placing the chip and the wafer in the chamber oppositely, and vacuumizing to enable the bonding surfaces of the chip and the wafer to be in contact. And pressing to make the surfaces needing to be bonded tightly bonded.

Glass dielectric bonding refers to printing glass solder on a wafer to form a closed ring, and then placing the cover plate into a reflow oven for pre-sintering. And aligning the wafer and the chip after the presintering is finished, positioning the chip in the closed ring, and then putting the closed ring into a bonding machine for sintering to form a sealed cavity. The glass medium bonding process is simple, the bonding strength is high, the sealing effect is good, and the glass medium bonding process is particularly suitable for mass production.

Accordingly, referring to fig. 6 in combination, after bonding, the adhesive layer 15 (shown in fig. 5) and the carrier substrate 10 (shown in fig. 5) are removed, that is, after the fusion bonding process, a De-bonding process is performed on the second chip 200 and the carrier substrate 10.

Through the debonding process, the second chip 200 and the carrier substrate 10 are separated to remove the carrier substrate 10 and the adhesive layer 15.

Moreover, through the debonding process, the chip front surface 202 of the second chip 200 is exposed, thereby providing a process foundation for the subsequent formation of a conductive layer electrically connected to the second electrode 210.

Specifically, the process of the debonding treatment may be one or more of chemical etching, mechanical peeling, mechanical grinding, thermal baking, ultraviolet irradiation, laser ablation, chemical mechanical polishing, and wet peeling, and a suitable process is selected according to the material of the adhesive layer 15.

Referring to fig. 7 and 8 in combination, after the adhesive layer 15 (shown in fig. 5) and the carrier substrate 10 (shown in fig. 5) are removed, insulating side walls 450 (shown in fig. 8) are formed on the side walls of the second chip 200.

And forming a conductive layer electrically connected to the second electrode 210 and the first electrode 320 to electrically connect the first chip and the second chip, wherein the insulating side wall 450 is used to insulate the conductive layer from the second chip 200, so as to prevent the conductive layer from affecting the performance of the second chip 200.

Therefore, the insulating sidewall spacers 450 are made of an insulating material. In this embodiment, the insulating sidewall spacers 450 are made of silicon oxide. In other embodiments, the insulating sidewall spacer may also be made of silicon nitride or silicon oxynitride.

In this embodiment, the insulating sidewall spacers 450 completely expose the first electrode 320, so that the conductive layer is in complete contact with the first electrode 320, and the electrical connection effect between the conductive layer and the first electrode 320 is further improved.

Specifically, the step of forming the insulating sidewall spacers 450 includes: forming an insulating layer 400 (shown in fig. 7) conformally covering the second chips 200 and the front surface 301 of the wafer between adjacent second chips 200; the insulating layer 400 on the front surface 202 of the chip and the front surface 301 of the wafer is removed, and the insulating layer 400 on the sidewall of the second chip 200 is remained as the insulating sidewall spacer 450.

The insulating sidewall 450 is made of silicon oxide, and correspondingly, the insulating layer 400 is made of silicon oxide. In other embodiments, the material of the insulating layer may also be silicon nitride or silicon oxynitride.

In this embodiment, the insulating layer 400 is formed by an atomic layer deposition process in order to improve the conformal coverage of the insulating layer 400.

In this embodiment, the insulating layer 400 on the front surface 202 of the chip and the front surface 301 of the wafer is removed by a dry etching process. Through the dry etching process, the insulating layer 400 on the front surface 202 of the chip and the insulating layer 400 on the front surface 301 of the wafer can be removed in a maskless etching manner, and the insulating layer 400 on the sidewall of the second chip 200 is remained.

In the step of forming the insulating layer 400, the thickness of the insulating layer 400 is not necessarily too small or too large. If the thickness of the insulating layer 400 is too small, the insulating property of the insulating sidewall 450 is easily reduced, which is not favorable for realizing the mutual insulation between the conductive layer and the second chip 200; if the thickness of the insulating layer 400 is too large, not only the process cost and time are wasted, but also the process difficulty of etching the insulating layer 400 is increased, and in addition, the formation quality of the insulating layer 400 between the adjacent second chips 200 is easily reduced. For this reason, in the present embodiment, the thickness of the insulating layer 400 is 0.1 to 5 μm.

Referring to fig. 9, a conductive layer 500 is formed conformally covering the chip front side 202, the insulating sidewalls 450, and the wafer front side 301.

The conductive layer 500 covers the chip front side 202 and contacts with the second electrode 210 on the chip front side 202, and the conductive layer 500 also covers the wafer front side 301 and contacts with the first electrode 320 on the wafer front side 301, so that the first electrode 320 and the second electrode 210 are electrically connected, and further the first chip 200 and the second chip 310 are electrically connected.

Therefore, the material of the conductive layer 500 has better conductivity and higher stability, so that the influence on the performance of the formed package structure can be reduced. In this embodiment, the material of the conductive layer 500 is one or more of copper, aluminum, tin and nickel.

Note that the thickness of the conductive layer 500 is not too small or too large. If the thickness of the conductive layer 500 is too small, the conductive layer 500 is prone to have a problem of too large resistance, so that the electrical connection effect of the first chip and the second chip is prone to be reduced; if the thickness of the conductive layer 500 is too large, not only the process cost and time are wasted, but also the quality of the conductive layer 500 formed between the adjacent second chips 200 is easily reduced. For this reason, in the present embodiment, the thickness of the conductive layer 500 is 0.1 to 5 μm.

In this embodiment, the process of forming the conductive layer 500 is an atomic layer deposition process. The mode of forming the conductive layer 500 by using the atomic layer deposition process is beneficial to improving the thickness uniformity of the conductive layer 500 and the structural uniformity in the conductive layer 500, and the conductive layer 500 has good covering capability, so that the first chip 310 and the second chip 200 can have a good electrical connection effect.

In this embodiment, the electrical connection between the first chip 310 and the second chip 200 can be realized only by one conductive layer 500, so that the packaging process is simplified, and since the device wafer 300 and the second chip 200 are bonded by the first oxide layer 350 and the second oxide layer 250 in a fusion bonding manner, the bonding strength between the device wafer 300 and the second chip 200 is high, so that the packaging structure as a whole can maintain good reliability, thereby ensuring the electrical connection effect between the first chip 310 and the second chip 200.

It should be further noted that the packaging method further includes: after the conductive layer 500 is formed, an encapsulation layer (not shown) is covered on the conductive layer 500.

The packaging layer fills the gap between the second chips 200 and covers the conductive layer 500, and contacts with the conductive layer 500 to realize sealing, so that air and moisture can be better isolated, and the conductive layer 500, the second chips 200 and the device wafer 300 are protected, so that the packaging effect is improved, and the performance of the obtained packaging structure is further optimized.

The detailed description of the encapsulation layer is not repeated herein.

Correspondingly, the invention also provides a packaging structure.

With continued reference to fig. 9, a schematic structural diagram of a wafer level package structure according to an embodiment of the invention is shown.

The package structure includes: a device wafer 300, wherein the device wafer 300 includes a plurality of first chips 310, the first chips 310 include first electrodes 320, the first electrodes 320 are exposed from the device wafer 300, and a surface of the device wafer 300, on which the first electrodes 320 are exposed, is a wafer front surface 301; a plurality of second chips 200 bonded to the wafer front surface 301 through a fusion bonding process, a surface of the second chip 200 bonded to the wafer front surface 301 is a chip back surface 201, a surface opposite to the chip back surface 201 is a chip front surface 202, the second chip 200 includes a second electrode 210, and the second electrode 210 is exposed from the chip front surface 202; an insulating sidewall spacer 450 on a sidewall of the second chip 200; a conductive layer 500 conformally covering the chip front side 202, the insulating sidewalls 450 and the wafer front side 301.

In this embodiment, the package structure is a wafer level system package structure.

The device wafer 300 has a plurality of first chips 310 formed therein. In this embodiment, the plurality of first chips 310 may be chips of the same type or different types. It should be noted that the device wafer 300 may be fabricated by using an integrated circuit fabrication technology, and therefore the device wafer 300 generally includes devices such as NMOS devices and PMOS devices formed on a substrate, a dielectric layer formed on the devices, a metal interconnection structure, and a pad electrically connected to the metal interconnection structure.

In this embodiment, the first chip 310 includes a first electrode 320. Specifically, the first electrode 320 is a wire bonding pad for electrically connecting the first chip 310 to other circuits.

The second chips 200 are used as chips to be integrated in the wafer level system package, the package structure of this embodiment is heterogeneous integration, and accordingly, the second chips 200 may be chips made of silicon wafers or chips made of other materials.

The plurality of second chips 200 may be chips having the same function or different functions, and the number of the second chips 200 is the same as that of the first chips 310.

The second chip 200 may be made by using an integrated circuit fabrication technology, and may be a memory chip, a communication chip, a processor, or a logic chip. In other embodiments, chips with other functions may be selected according to actual process requirements.

It should be noted that the second chip 200 generally also includes devices such as NMOS devices or PMOS devices formed on the substrate, and further includes structures such as a dielectric layer, a metal interconnection structure, and a bonding pad. In this embodiment, the substrate of the second chip 200 is a silicon substrate. In other embodiments, the material of the substrate of the second chip may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material of the second chip may be a material that is suitable for process requirements or easy to integrate.

In this embodiment, the second chip 200 and the corresponding first chip 310 have a predetermined relative position relationship. Specifically, the second chip 200 and the first chip 310 are staggered.

By staggering the second chip 200 and the first chip 310, the difficulty in forming the conductive layer 500 can be reduced, and the electrical connection effect between the conductive layer 500 and the first electrode 320 can be improved, thereby improving the electrical connection effect between the first chip 310 and the second chip 200.

In other embodiments, the second chip and the first chip may also partially overlap, and the second chip exposes the first electrode of the first chip.

In this implementation, the second chip 200 is bonded to the device wafer 300 through a fusion bonding process, so that the second chip 200 and the device wafer 300 have a higher bonding strength.

Specifically, a first oxide layer 350 is formed on the front surface 301 of the wafer, a second oxide layer 250 is formed on the back surface 201 of the chip, and the second oxide layer 250 is disposed opposite to the first oxide layer 350 and bonded through a fusion bonding process, so as to achieve physical connection between the device wafer 300 and the second chip 200.

The fusion bonding is a process that mainly uses interfacial chemical force to complete bonding, and the contact surface of the second oxide layer 250 and the first oxide layer 350 is connected in a covalent bond manner, so that the second oxide layer 250 and the first oxide layer 350 have higher bonding strength, thereby improving the bonding strength between the device wafer 300 and the second chip 200, and enabling the whole package structure to maintain better reliability.

The material of the second oxide layer 250 is the same as the material of the first oxide layer 350, so that covalent bonding can be better achieved, which is beneficial to further improving the bonding strength between the second oxide layer 250 and the first oxide layer 350.

In this embodiment, the first oxide layer 350 and the second oxide layer 250 are made of silicon oxide. The silicon oxide material has higher process compatibility, and the silicon oxide is a material which is commonly used in the process and has lower cost, so that the process difficulty and the process cost are favorably reduced by selecting the silicon oxide material, and the performance influence on the formed packaging structure is favorably reduced; moreover, the contact surfaces of the first oxide layer 350 and the second oxide layer 250 are bonded by covalent bonds of Si-O-Si, and the bonding strength between the second chip 200 and the device wafer 300 can be effectively improved because the bonding energy of the Si-O bonds is large.

In other embodiments, the material of the first oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide, and the material of the second oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide.

In this embodiment, in order to reduce the process difficulty, the thicknesses of the first oxide layer 350 and the second oxide layer 250 are equal. However, the thicknesses of the first oxide layer 350 and the second oxide layer 250 are not necessarily too small, and are not necessarily too large. If the thickness is too small, the uniformity and quality of the thickness of the first oxide layer 350 and the second oxide layer 250 are easily reduced, and the bonding strength between the first oxide layer 350 and the second oxide layer 250 is also easily adversely affected; if the thickness is too large, the whole thickness of the packaging structure is correspondingly too large, which is not beneficial to improving the process integration level. For this reason, in this embodiment, the first oxide layer 350 and the second oxide layer 250 have both thicknesses

To

It should be noted that the first oxide layer 350 covers a portion of the front surface 301 of the wafer, and the first oxide layer 350 exposes the first electrode 320 of the first chip 310, so that the conductive layer 500 can contact with the first electrode 320.

In this embodiment, the projection of the first oxide layer 350 on the front surface 301 of the wafer coincides with the projection of the first oxide layer 350 on the front surface 301 of the wafer, and the first oxide layer 350 is staggered from the first chip 310, so that the difficulty in forming the conductive layer 500 is reduced, and the electrical connection effect between the conductive layer 500 and the first electrode 320 is improved.

In other embodiments, a projection of the first oxide layer on the front surface of the wafer may be located in the projection of the first oxide layer on the front surface of the wafer, and the first oxide layer covers a portion of the first chip and exposes the first electrode.

The insulating side walls 450 cover the side walls of the second chip 200, and the insulating side walls 450 are used for insulating the conductive layer 500 from the second chip 200, so that the conductive layer 500 is prevented from affecting the performance of the second chip 200.

In this embodiment, the insulating sidewall spacers 450 completely expose the first electrode 320, so that the conductive layer 500 is in complete contact with the first electrode 320, and the electrical connection effect between the conductive layer 500 and the first electrode 320 is further improved.

It should be noted that the thickness of the insulating sidewall spacers 450 is not too small, and is not too large. If the thickness of the insulating sidewall 450 is too small, the insulating property of the insulating sidewall 450 is easily reduced, which is not favorable for realizing the mutual insulation between the conductive layer 500 and the second chip 200; if the thickness of the insulating sidewall spacers 450 is too large, not only the process cost and time are wasted, but also the process difficulty of forming the insulating sidewall spacers 450 is increased, and in addition, the forming quality of the insulating sidewall spacers 450 is easily reduced. For this reason, in the present embodiment, the thickness of the insulating sidewall spacers 450 is 0.1 to 5 μm. The thickness of the insulating sidewall spacers 450 refers to a dimension of the insulating sidewall spacers 450 along a direction perpendicular to the sidewall of the second chip 200.

Therefore, the material of the conductive layer 500 has better conductivity and higher stability, so that the influence on the performance of the package structure can be reduced. In this embodiment, the material of the conductive layer 500 is one or more of copper, aluminum, tin and nickel.

Note that the thickness of the conductive layer 500 is not too small or too large. If the thickness of the conductive layer 500 is too small, the conductive layer 500 is prone to have a problem of too large resistance, so that the electrical connection effect of the first chip 200 and the second chip 310 is prone to be reduced; if the thickness of the conductive layer 500 is too large, not only the process cost and time are wasted, but also the quality of the conductive layer 500 formed between the adjacent second chips 200 is easily reduced. For this reason, in the present embodiment, the thickness of the conductive layer 500 is 0.1 to 5 μm.

In this embodiment, the electrical connection between the first chip 310 and the second chip 200 can be realized only by one conductive layer 500, the packaging process is simple, and since the device wafer 300 and the second chip 200 are bonded by the first oxide layer 350 and the second oxide layer 250 in a fusion bonding manner, the bonding strength between the device wafer 300 and the second chip 200 is high, the overall packaging structure can maintain good reliability, thereby ensuring the electrical connection effect between the first chip 310 and the second chip 200.

It should be further noted that the package structure further includes: an encapsulation layer (not shown) on the conductive layer 500.

The packaging layer fills the gap between the second chips 200 and covers the conductive layer 500, and is in contact with the conductive layer 500 to realize sealing, so that air and moisture can be better isolated, and the conductive layer 500, the second chips 200 and the device wafer 300 are protected, so that the packaging effect is improved, and the performance of the packaging structure is further optimized.

The detailed description of the encapsulation layer is not repeated herein.

The package structure of this embodiment may be formed by the package method described in the foregoing embodiments, or may be formed by other package methods. In this embodiment, for the specific description of the package structure, reference may be made to the corresponding description in the foregoing embodiment, and this embodiment is not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A wafer level packaging method, comprising:

providing a device wafer, wherein the device wafer comprises a plurality of first chips, the first chips comprise first electrodes, the first electrodes are exposed out of the device wafer, and the surfaces of the device wafer, which are exposed out of the first electrodes, are the front surfaces of the device wafer;

providing a bearing substrate, temporarily bonding a plurality of second chips on the bearing substrate, wherein the second chips comprise second electrodes, the second electrodes are exposed out of the second chips, the surfaces of the second chips, which are exposed out of the second electrodes, are front surfaces of the chips, and the surfaces, which are opposite to the front surfaces of the chips, are back surfaces of the chips;

enabling the back surface of the chip and the front surface of the wafer to be oppositely arranged, and enabling the back surface of the chip to be bonded to the front surface of the wafer by adopting a fusion bonding process;

after bonding, performing bonding removal treatment on the second chip and the bearing substrate;

after the bonding removing treatment, forming an insulating side wall on the side wall of the second chip;

and forming a conductive layer which conformally covers the front surface of the chip, the insulating side wall and the front surface of the wafer.

2. The packaging method of claim 1, further comprising: forming a first oxide layer on the front surface of the wafer; forming a second oxide layer on the back surface of the chip;

the fusion bonding process is performed through the first oxide layer and the second oxide layer.

3. The packaging method of claim 2, wherein the step of the fusion bonding process comprises: sequentially carrying out plasma activation treatment, deionized water cleaning treatment and drying treatment on the surface of the first oxidation layer and the surface of the second oxidation layer;

after the drying treatment, the second oxidation layer and the first oxidation layer are oppositely arranged and attached, and bonding pressure is applied to the device wafer and the second chip to carry out pre-bonding treatment;

and after the pre-bonding treatment, annealing the device wafer and the second chip.

4. The packaging method of claim 1, wherein the step of forming insulating spacers on the sidewalls of the second chip comprises: forming an insulating layer which conformally covers the second chip and the front surface of the wafer between the second chips;

and removing the insulating layers on the front surfaces of the chips and the front surface of the wafer, and reserving the insulating layer on the side wall of the second chip as the insulating side wall.

5. The packaging method of claim 1, wherein the step of forming insulating spacers on the sidewalls of the second chip comprises: the insulating side wall completely exposes the first electrode.

6. The packaging method of claim 1, further comprising: after the conductive layer is formed, an encapsulation layer is covered on the conductive layer.

7. The packaging method according to claim 2, wherein the front side of the chip is temporarily bonded to the carrier substrate after the second oxide layer is formed on the back side of the chip;

alternatively, the first and second electrodes may be,

and forming the second oxidation layer on the back surface of the chip after the front surface of the chip is temporarily bonded on the bearing substrate.

8. The packaging method according to claim 2, wherein a material of the first oxide layer is silicon oxide, hafnium oxide, aluminum oxide, or lanthanum oxide, a material of the second oxide layer is silicon oxide, hafnium oxide, aluminum oxide, or lanthanum oxide, and the materials of the first oxide layer and the second oxide layer are the same.

9. The packaging method according to claim 3, wherein the reactive gas used in the plasma activation process comprises Ar, N₂、O₂And SF₆One or more of (a).

10. The packaging method according to claim 4, wherein the insulating layers of the front surface of the chip and the front surface of the wafer are removed by a dry etching process.

11. The packaging method according to claim 4, wherein the insulating layer is made of silicon nitride, silicon oxide, or silicon oxynitride.

12. The packaging method of claim 1, wherein the material of the conductive layer is one or more of copper, aluminum, tin, and nickel.

13. A wafer level package structure, comprising:

the device wafer comprises a plurality of first chips, the first chips comprise first electrodes, the first electrodes are exposed out of the device wafer, and the surfaces of the device wafer, which are exposed out of the first electrodes, are the front surfaces of the wafer;

the second chips are bonded to the front side of the wafer through a fusion bonding process, the surfaces of the second chips bonded to the front side of the wafer are chip back surfaces, the surfaces opposite to the chip back surfaces are chip front surfaces, the second chips comprise second electrodes, and the second electrodes are exposed out of the chip front surfaces;

the insulating side wall is positioned on the side wall of the second chip;

and the conductive layer is covered on the front surface of the chip, the insulating side wall and the front surface of the wafer in a shape-preserving manner.

14. The package structure of claim 13, wherein a first oxide layer is formed on the front surface of the wafer; a second oxide layer is formed on the back surface of the chip;

the second oxide layer is disposed opposite the first oxide layer and bonded by a fusion bonding process.

15. The package structure of claim 13, wherein the package structure further comprises: and the packaging layer is positioned on the conductive layer.

16. The package structure of claim 13, wherein the insulating spacers are made of silicon nitride, silicon oxide, or silicon oxynitride.

17. The package structure of claim 13, wherein the insulating spacers have a thickness of 0.1 to 5 microns.

18. The package structure of claim 13, wherein the conductive layer is made of one or more of copper, aluminum, tin, and nickel.

19. The package structure of claim 13, wherein the conductive layer has a thickness of 0.1 to 5 microns.

20. The package structure of claim 14, wherein the first oxide layer is made of silicon oxide, hafnium oxide, aluminum oxide, or lanthanum oxide, the second oxide layer is made of silicon oxide, hafnium oxide, aluminum oxide, or lanthanum oxide, and the first oxide layer and the second oxide layer are made of the same material.