JP2006288055A - Motor driving integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor driving integrated circuit capable of suppressing noise by motor driving. <P>SOLUTION: This motor driving integrated circuit includes: a plurality of transistors for successively supplying currents in different directions to coils; an output circuit for outputting a driving signal of a binary level for switching and driving the plurality of transistors; an oscillation circuit for generating an oscillation signal for a first period; an input terminal in which a PWM signal of a second period (>the first period) is input; a rectangular signal generation circuit for successively generating a rectangular signal for the second period to which a duty is made variable on the basis of the oscillation signal in a prescribed period (>the second period) extending over before and after the change of the level of the driving signal; a synchronizing circuit for synchronization with the PWM signal and the rectangular signal; and a selection circuit for selecting a logical sum signal of the synchronized PWM signal and rectangular signal instead of the driving signal in the prescribed period. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit for driving a motor.

  A motor (for example, a sensorless three-phase brushless DC motor) drive device is connected in series between a power supply voltage VP and a ground VSS as an output stage, for example, and one end of a coil is connected to the connection point of the power supply voltage VP side Source-side transistors and ground VSS-side sink-side transistors for each of the three-phase coils. The other ends of the three-phase coils are connected in common. In the motor drive device, the part excluding the coil is integrated, for example, on the same chip (hereinafter, the integrated circuit is referred to as an IC).

  When the source side transistor is turned on, a current flows in the direction of the power supply voltage VP → the source side transistor → the coil connected to the source side transistor. On the other hand, when the sink-side transistor is turned on, a current flows in the direction of the coil to which the sink-side transistor is connected → the sink-side transistor → the ground VSS. The motor drive integrated circuit drives the motor by sequentially switching the coil current flowing through the three-phase coil for each predetermined electrical angle. FIG. 9 is a diagram for explaining a waveform of a current flowing in each phase of the motor drive integrated circuit. As shown in FIG. 9, the U-phase, V-phase, and W-phase motor coils have a high level (upper portion of the staircase waveform), a middle level (center portion of the staircase waveform), and a low level (lower portion of the staircase waveform). ) And the coil currents that are sequentially switched flow with a phase difference of 120 electrical degrees. Here, the current flowing through the coil is at a high level when the source-side transistor connected to one end of the coil is on, and the current flowing through the coil is at the low level This is a period during which the sink-side transistor connected to one end is on. The current flowing through the coil is at the middle level during the period when both the source side transistor and the sink side transistor connected to one end of the coil are off.

  FIG. 8 is a diagram for explaining changes in the coil current flowing in the three-phase coil in the T period shown in FIG. The current flowing through the U-phase coil 2 changes from the middle level to the high level during the T period, and the current flowing through the W-phase coil 6 changes from the high level to the middle level. The current flowing through the V-phase coil 4 remains at a low level. That is, the current flowing through the W-phase coil 6 or the U-phase coil 2 flows into the V-phase coil 4. Thus, in the case of switching the energization of the coil in the T period of FIG. 9, the path of the current flowing through the three-phase coil is switched from the broken line direction to the solid line direction in FIG. Note that this is not only when current flows from the U-phase coil 2 or W-phase coil 6 to the V-phase coil 4, but also when current flows from the U-phase coil 2 or V-phase coil 4 to the W-phase coil 6. The same can be said for the case where current flows from the phase coil 4 or the W-phase coil 6 to the U-phase coil 2.

  As one of motor driving methods, there is known PWM (Pulse Width Modulatin) control for driving a motor by intermittently supplying a driving current to a coil. In the PWM control, any one of the source side transistor and the sink side transistor driven by energization every 60 degrees of electrical angle is intermittently turned on / off according to the PWM signal. Then, a drive current corresponding to the on / off duty is passed through the coil to drive the motor. Such an integrated circuit for driving a motor using PWM control has low power consumption, and can suppress heat generation during driving of the motor.

  By the way, as shown in FIG. 9, when the coil current changes stepwise when the coil energization is switched, the driving of the motor becomes unstable and noise is generated when the motor is driven. Therefore, in a PWM control motor drive integrated circuit, a soft switch is known that smoothes changes in coil current (for example, currents in the U phase and W phase during the T period in FIG. 9) when energization is switched ( For example, see Patent Document 1).

  In the soft switch, for example, a rectangular signal with a gradually changing duty (hereinafter referred to as a soft switch signal) is generated, and a combined signal obtained by synthesizing the soft switch signal and a PWM signal having the same cycle is used when the coil is switched in energization. Turn on the power.

The soft switch signal whose duty gradually changes can be generated based on, for example, a signal obtained by multiplying a frequency signal proportional to the rotation speed of the motor and a clock signal.
JP-A-6-165576

The clock signal and the PWM signal used for the soft switch can be generated inside the IC or input from the outside of the IC.
When inputting a clock signal and a PWM signal from the outside of the IC, an input terminal is required. Therefore, there is a problem that the number of terminals increases. Further, when the clock signal is taken from outside the IC, the clock signal may not be input. When the clock signal is not input, operations other than PWM cannot be performed normally. Therefore, it is desirable to obtain the clock signal from an oscillation circuit provided with an oscillation circuit inside the IC, for example.

The PWM signal can be generated by dividing the clock signal. However, if the clock signal is generated inside the IC and further divided, the power consumption inside the IC increases.
Therefore, in order to reduce the number of terminals while suppressing the power consumption of the IC, it is desirable to generate a clock signal inside the IC and capture a PWM signal from the outside of the IC.
However, in this case, the soft switch signal obtained based on the clock signal and the PWM signal are not synchronized.

  FIG. 10 is a waveform diagram showing a combined signal when the soft switch signal and the PWM signal are not synchronized. This synthesized signal is obtained by the logical product of the PWM signal and the soft switch signal. The period of the PWM signal is equal to the period of the soft switch signal. A synthesized signal obtained by synthesizing a soft switch signal obtained based on a PWM signal input from outside the IC and a clock signal generated inside the IC, for example, irregularly changes between a high level and a low level as shown in FIG. Signal. When the coil is energized using this synthesized signal, noise is generated when the motor is driven.

  As described above, when the clock signal is generated inside the IC and the PWM signal is taken in from the outside of the IC, the soft switch signal and the PWM signal are not synchronized, so the high level and the low level of the composite signal change irregularly. As a result, there has been a problem that the motor drive sound cannot be silenced optimally.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit for driving a motor that can reduce the noise of motor driving.

  A main invention for solving the above problems includes a plurality of transistors that sequentially supply currents in different directions to the coil, an output circuit that outputs a binary level drive signal for switching and driving the plurality of transistors, An oscillation circuit that generates an oscillation signal of one cycle, an input terminal to which a PWM signal of a second cycle (> the first cycle) is input, and a predetermined period (> the first cycle) before and after the level of the drive signal changes 2 cycles), a rectangular signal generation circuit for sequentially generating a rectangular signal of the second cycle with a variable duty based on the oscillation signal, a synchronization circuit for synchronizing the PWM signal and the rectangular signal, and the predetermined signal And a selection circuit that selects a logical product signal of the PWM signal and the rectangular signal that are synchronized in a period instead of the drive signal.

  According to the present invention, it is possible to reduce the noise of the motor drive.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

=== Configuration of Integrated Circuit for Motor Drive ===
A motor drive integrated circuit according to the present invention will be described with reference to FIGS. 1, 2, and 3. FIG. 1 is a circuit block diagram for explaining an integrated circuit for driving a motor according to the present invention. 2 and 3 are waveform diagrams for explaining the motor drive integrated circuit according to the present invention. In this embodiment, the motor is a sensorless motor of PWM control, for example, a three-phase brushless DC motor. Further, in the motor drive integrated circuit shown in FIG. 1, the portions excluding the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 are integrated on the same chip, for example.

  The U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 are motor coils, and are wound around the stator with a star connection and a phase difference of 120 electrical degrees.

  The N-channel MOSFET (hereinafter referred to as NMOS) 8 is a source side transistor for supplying a coil current from the power supply voltage VP to the U-phase coil 2, and the NMOS 10 supplies a coil current from the U-phase coil 2 to the ground VSS. This is a sink-side transistor. The drain / source paths of the NMOSs 8 and 10 are connected in series between the power supply voltage VP and the ground VSS, and the drain / source connection portions of the NMOSs 8 and 10 are connected to one end of the U-phase coil 2. The NMOS 12 is a source-side transistor for supplying a coil current from the power supply voltage VP to the V-phase coil 4, and the NMOS 14 is a sink-side transistor for supplying a coil current from the V-phase coil 4 to the ground VSS. The drain / source paths of the NMOS 12 and 14 are connected in series between the power supply voltage VP and the ground VSS, and the drain / source connection portion of the NMOS 12 and 14 is connected to one end of the V-phase coil 4. The NMOS 16 is a source-side transistor for supplying a coil current from the power supply voltage VP to the W-phase coil 6, and the NMOS 18 is a sink-side transistor for supplying a coil current from the W-phase coil 6 to the ground VSS. The drain / source paths of the NMOSs 16 and 18 are connected in series between the power supply voltage VP and the ground VSS, and the drain / source connection portions of the NMOSs 16 and 18 are connected to one end of the W-phase coil 6. When the NMOSs 8, 10, 12, 14, 16, 18 are turned on / off at an appropriate timing, the motor is supplied with coil currents to the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 and predetermined. It will rotate in the direction (for example, forward rotation). As a result, coil voltages VU, VV, and VW having a phase difference of 120 electrical degrees are generated at one end of the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6. Note that not only the MOSFET but also a bipolar transistor can be used as the source-side transistor and the sink-side transistor.

  The comparator 22U receives the coil voltage VU at the + (non-inverting input) terminal and the neutral point voltage VCOM at the-(inverting input) terminal, and compares the coil voltage VU with the neutral point voltage VCOM. A rectangular comparison signal CPU that changes at an electrical angle of 180 degrees is output. A pulse based on the kickback pulse KB is superimposed on the comparison signal CPU. In addition, the comparator 22V receives the coil voltage VV applied to the + terminal and the neutral point voltage VCOM applied to the − terminal, and compares the coil voltage VV and the neutral point voltage VCOM so that the timing of the electrical angle is 180 degrees. The rectangular comparison signal CPV that changes in the above is output. A pulse based on the kickback pulse KB is superimposed on the comparison signal CPV. Further, the comparator 22W receives the coil voltage VW at the + terminal and the neutral point voltage VCOM at the − terminal, and compares the coil voltage VW with the neutral point voltage VCOM to thereby obtain a timing of an electrical angle of 180 degrees. A rectangular comparison signal CPW that changes at A pulse based on the kickback pulse KB is superimposed on the comparison signal CPW. The comparison signals CPU, CPV, and CPW each have a phase difference of 120 electrical degrees.

  The mask circuit 26 removes (masks) noise corresponding to the kickback pulse KB from the comparison signal CPU, which is the output of the comparator 22U, based on the rectangular signal RE1, and generates and outputs a mask signal UMASK. The mask circuit 26 removes (masks) noise corresponding to the kickback pulse KB from the comparison signal CPV output from the comparator 22V based on the rectangular signal RE1, and generates and outputs a mask signal VMASK. Further, the mask circuit 26 removes (masks) noise corresponding to the kickback pulse KB from the comparison signal CPW, which is the output of the comparator 22W, based on the rectangular signal RE1, and generates and outputs a mask signal WMASK. Here, the mask signals UMASK, VMASK, and WMASK have a phase difference of an electrical angle of 120 degrees.

  Further, as shown in FIG. 3, the mask circuit 26 generates a MASK signal indicating a predetermined period (for example, 14 pulses of the RE1 signal) within a half cycle of the rectangular composite signal FG, and the timing synthesis circuit 50. Output to.

  The combining circuit 28 combines the mask signals UMASK, VMASK, and WMASK output from the mask circuit 26, and outputs a rectangular combined signal FG that changes at a timing of an electrical angle of 60 degrees.

  The multiplier circuit 30 generates a rectangular signal RE1 having a higher frequency than the combined signal FG by multiplying the combined signal FG output from the combining circuit. As a result, the phase of the synthesized signal FG matches the phase of the rectangular signal RE1, and the ½ period of the synthesized signal FG matches the n period (for example, 16 periods) of the rectangular signal RE1. For example, a PLL (Phase Locked Loop) that performs analog signal processing and a DLL (Delay Locked Loop) that performs digital signal processing can be applied to the multiplication circuit 30.

  The sensorless logic circuit 40 outputs a signal for energizing the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 at an appropriate timing. In other words, the sensorless logic circuit 40 considers that the sensorless motor itself cannot determine the relative position between the rotor and the stator before starting, and when the rotor is stopped, the mask signals UMASK, VMASK, and WMASK are predetermined. It operates from the initial level (for example, UMASK = “L”, VMASK = “L”, WMASK = “H”). In addition, the sensorless logic circuit 40 generates energization signals ULOGIC1 (= UMASK-VMASK), VLOGIC1 (= VMASK-WMASK), and WLOGIC1 (= WMASK-UMASK). When the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 are energized, the sensorless logic circuit 40 outputs energization signals ULOGIC2, VLOGIC2, and WLOGIC2 that are delayed from the energization signals ULOGIC1, VLOGIC1, and WLOGIC1.

  The signal processing circuit 44 generates UH, UL, VH, VL, WH, and WL signals shown in FIG. 3 from the energization signals ULOGIC2, VLOGIC2, and WLOGIC2. The UH signal is a signal for driving the U-phase source-side transistor NMOS8, and the UL signal is a signal for driving the U-phase sink-side transistor NMOS10. The VH signal is a signal for driving the V-phase source-side transistor NMOS12, and the VL signal is a signal for driving the V-phase sink-side transistor NMOS14. Further, the WH signal is a signal for driving the W-phase source-side transistor NMOS16, and the WL signal is a signal for driving the W-phase sink-side transistor NMOS18.

  The RE1 counter 34 (“first counter”) is, for example, a 4-bit counter, and counts the number of pulses of the RE1 signal (“third period signal”) output from the multiplier circuit 30. FIG. 6 is a diagram illustrating an example of the configuration of the RE1 counter 34. The RE1 counter 34 shown in FIG. 6 includes D-type flip-flop circuits (hereinafter referred to as DFF) 70, 72, 74, and 76. The 4-bit signals Q1, Q2, Q3, and Q4 are output from the DFFs 70, 72, 74, and 76 as count outputs. Assuming that the initial values of Q1 to Q4 are all 0, every time the rising edge of the RE1 signal is added, the Q output (Q4, Q3, Q2, Q1) becomes (0, 0, 0, 0), (0 , 0, 0, 1), (0, 0, 1, 0)...

  The oscillation circuit 38 generates a clock signal CLK (“oscillation signal”) having a predetermined period.

  The CLK counter 42 (“second counter”) is a 4-bit counter having the same DFF as the RE1 counter, for example, and repeatedly counts the number of pulses of the clock signal CLK from 0 to 15, for example.

  The count output of the CLK counter 42 is input to the + terminal of the comparator 46 (“second comparator”), and the count output of the RE1 counter 34 is input to the − terminal of the comparator 46. The comparator 46 outputs “L” when the count value of the RE1 counter 34 is larger than the count value of the CLK counter 42, and outputs “H” when the count value of the RE1 counter 34 is smaller than the count value of the CLK counter 42. Output.

  The count output of the RE1 counter 34 is input to the + terminal of the comparator 48 (“first comparator”), and the count output of the CLK counter 42 is input to the − terminal of the comparator 48. The comparator 48 outputs “H” when the count value of the RE1 counter 34 is larger than the count value of the CLK counter 42, and outputs “L” when the count value of the RE1 counter 34 is smaller than the count value of the CLK counter 42. Output.

  Based on the MASK signal and the binary level UH, UL, VH, VL, WH, and WL signals ("drive signal") output from the signal processing circuit 44, the timing synthesis circuit 50 generates a switching signal M1, M2, M3, M4, M5 and M6 are generated.

  The switching circuit 52 appropriately switches the output signal of the signal processing circuit 44, the output signal of the comparator 46, and the output signal of the comparator 48 in accordance with the switching signals M1, M2, M3, M4, M5, and M6 and performs PWM synthesis. This is output to the circuit 54.

  The DFF 60 (“synchronous circuit”) applies a PWM signal having a cycle (“second cycle”) longer than the clock signal CLK to the data input (hereinafter referred to as “D input”) via the PWM signal input terminal (“input terminal”). The clock signal CLK is applied to the clock input (hereinafter referred to as C input). The DFF 60 holds the PWM signal at the timing when the clock signal CLK changes and outputs it from the Q output.

  When the signal processing circuit 44 side is selected in the switching circuit 52, the PWM synthesis circuit 54 drives the MOSFETs 8, 10, 12, 14, 16, and 18 based on the output signal of the signal processing circuit 44 and the PWM signal. Output a signal. Further, when the comparators 46 and 48 are selected in the switching circuit 52, the PWM synthesis circuit 54 is based on the rectangular signal output from the comparators 46 and 48 and the PWM signal, and the MOSFETs 8, 10, 12, 14, 16 , 18 are output.

  The sensorless logic circuit 40 and the signal processing circuit 44 constitute an output circuit, and the switching circuit 52 and the PWM synthesis circuit 54 constitute a selection circuit. Further, the RE1 counter 34, the CLK counter 42, the comparator 46, and the comparator 48 constitute a rectangular signal generation circuit.

=== Comparator 46, 48 ===
FIG. 4 is a diagram for explaining the outputs of the comparators 46 and 48. Comparators 46 and 48 compare the count output of the RE1 counter 34 with the count output of the CLK counter 42. The CLK counter 42 counts the number of pulses of the clock signal CLK, and the RE1 counter 34 counts the number of pulses of the RE1 signal.

  In this embodiment, both the PWM counter 42 and the RE1 counter 34 are 4 bits. The CLK counter 42 is reset after counting 16 pulses of the clock signal CLK, and starts counting again. The RE1 counter is reset after counting the number of pulses of the RE1 signal to a predetermined value, and starts counting again. Here, the rectangular signal RE1 is a signal whose period changes in proportion to the rotational speed of the motor. The clock signal CLK is a signal having a constant period shorter than the period (“third period”) of the rectangular signal RE1. Therefore, the count outputs of the PWM counter 42 and the RE1 counter 34 have a relationship as shown in FIG. 4, for example. By comparing the count outputs of the two counters, the comparator 48 outputs a soft switch signal whose duty gradually increases, and the comparator 46 outputs a soft switch signal whose duty gradually decreases. The

=== Switching circuit and PWM synthesis circuit ===
The switching circuit 52 and the PWM synthesis circuit 54 will be described with reference to FIGS. 3 and 5. FIG. 5 is a circuit diagram showing an example of the configuration of the switching circuit 52 and the PWM synthesis circuit 54.

  The switching circuit 52 includes a plurality of NAND circuits and a plurality of inverter circuits. In the switching circuit 52, the configuration of the portion for each output transistor (NMOS 8, 10, 12, 14, 16, 18) is the same, so for convenience, only the portion corresponding to the NMOS 8 (dotted line portion in FIG. 5) will be described.

The inverter circuit 104 inverts the M1 signal.
The NAND circuit 102 outputs a low level (hereinafter referred to as “L”) when both the UH signal and the output of the inverter circuit 104 are at a high level (hereinafter referred to as “H”), and otherwise outputs “H”. Output.
The NAND circuit 106 outputs “L” when both the output of the comparator 48 and the M1 signal are “H”, and otherwise outputs “H”.
The NAND circuit 108 outputs “L” when both the output of the NAND circuit 102 and the output of the NAND circuit 106 are “H”, and otherwise outputs “H”.

The inverter circuit 152 inverts the M2 signal.
The NAND circuit 150 outputs “L” when both the output of the NAND circuit 108 and the output of the inverter circuit 152 are “H”, and otherwise outputs “H”.
The NAND circuit 154 outputs “L” when both the output of the comparator 46 and the M2 signal are “H”, and otherwise outputs “H”.
The NAND circuit 156 outputs “L” when both the output of the NAND circuit 150 and the output of the NAND circuit 154 are “H”, and otherwise outputs “H”.

  Next, the operation of the portion corresponding to the UH signal will be described.

≪For TA period≫
As shown in FIG. 3, the UH signal changes from “L” to “H” in the TA period. In the TA period, the switching signal M1 is “H” and the switching signal M2 is “L”.
When the switching signal M1 becomes “H”, the output of the inverter circuit 104 becomes “L”. Therefore, the output of the NAND circuit 102 is fixed to “H”.
The output of the NAND circuit 106 becomes “H” when the output of the comparator 48 is “L”, and becomes “L” when the output of the comparator 48 is “H”.
Since the output of the NAND circuit 102 is “H”, the output of the NAND circuit 108 is “H” when the output of the NAND circuit 106 is “L”, and is “L” when the output of the NAND circuit 106 is “H”. . Accordingly, the output of the comparator 48 is output from the NAND circuit 108.
Further, as described above, the switching signal M2 is “L” in the TA period. Therefore, the output of the inverter circuit 52 is “H”, and the output of the NAND circuit 154 is fixed to “H”.
Therefore, when the output of the NAND circuit 108 is “H”, the output of the NAND circuit 150 is “L”, and the output of the NAND circuit 156 is “H”. On the other hand, when the output of the NAND circuit 108 is “L”, the output of the NAND circuit 150 is “H”, and the output of the NAND circuit 156 is “L”.
Therefore, the output of the comparator 48 is output from the NAND circuit 156 during the TA period.

≪For TC period≫
As shown in FIG. 3, the UH signal changes from “H” to “L” in the TC period. In the TC period, the switching signal M1 is “L” and the switching signal M2 is “H”.
When the switching signal M2 becomes “H”, the output of the inverter circuit 152 becomes “L”. Accordingly, the output of the NAND circuit 150 is fixed to “H”.
The output of the NAND circuit 154 becomes “H” when the output of the comparator 46 is “L”, and becomes “L” when the output of the comparator 46 is “H”.
Since the NAND circuit 150 is “H”, the output of the NAND circuit 156 is “L” when the output of the NAND circuit 154 is “H”, and is “H” when the output of the NAND circuit 154 is “L”.
Accordingly, in the TC period, the output of the comparator 46 is output from the NAND circuit 156.

≪In case other than TA period and TC period≫
During periods other than the TA period and the TC period, the switching signals M1 and M2 are both “L” as shown in FIG.
When the switching signal M1 becomes “L”, the output of the NAND circuit 106 is fixed to “H”.
Further, when the switching signal M2 becomes “L”, the output of the NAND circuit 154 is fixed to “H”.
Since the switching signal M1 is “L”, the output of the inverter circuit 104 is “H”, and since the switching signal M2 is “L”, the output of the inverter circuit 152 is “H”.
Therefore, when the UH signal is “H”, the output of the NAND circuit 102 is “L”, the output of the NAND circuit 108 is “H”, the output of the NAND circuit 150 is “L”, and the output of the NAND circuit 156 is “H”. It becomes.
When the UH signal is “L”, the output of the NAND circuit 102 is “H”, the output of the NAND circuit 108 is “L”, the output of the NAND circuit 150 is “H”, and the output of the NAND circuit 156 is “L”. .
Therefore, the UH signal is output from the NAND circuit 156 outside the TA period and the TC period.

Similarly, the output of the NAND circuit 164 becomes the output of the comparator 48 during the TD period when the switching signal M3 becomes “H”, and becomes the output of the comparator 46 during the TF period when the switching signal M4 becomes “H”. The UL signal is used outside the TD period and the TF period.
The output of the NAND circuit 172 becomes the output of the comparator 48 during the TC period when the switching signal M2 becomes “H”, and becomes the output of the comparator 46 during the TE period when the switching signal M5 becomes “H”. And it becomes a VH signal except TC period and TE period.
The output of the NAND circuit 180 is the output of the comparator 48 during the TF period when the switching signal M4 is “H”, and the output of the comparator 46 during the TB period when the switching signal M6 is “H”. The VL signal is used outside the TF period and the TB period.
The output of the NAND circuit 188 becomes the output of the comparator 48 during the TE period when the switching signal M5 becomes “H”, and becomes the output of the comparator 46 during the TA period when the switching signal M1 becomes “H”. The WH signal is used during periods other than the TE period and the TA period.
The output of the NAND circuit 196 is the output of the comparator 48 during the TB period when the switching signal M6 is “H”, and the output of the comparator 46 during the TD period when the switching signal M3 is “H”. The WL signal is used in periods other than the TB period and the TD period.

  In this way, the switching circuit 52 switches to the comparator 48 side for a predetermined period before and after each signal UH, UL, VH, VL, WH, WL changes from “L” to “H”. Switching to the comparator 46 side is performed for a predetermined period before and after the change from “H” to “L”. In other periods, the output of the signal processing circuit 44 is output.

The PWM synthesis circuit 54 includes AND circuits 202, 204, 206, 208, 210, and 212 as shown in FIG.
The AND circuit 202 outputs the logical product of the output of the NAND circuit 156 and the PWM signal to the NMOS 8.
The AND circuit 204 outputs the logical product of the output of the NAND circuit 164 and the PWM signal to the NMOS 10.
The AND circuit 206 outputs the logical product of the output of the NAND circuit 172 and the PWM signal to the NMOS 12.
The AND circuit 208 outputs the logical product of the output of the NAND circuit 180 and the PWM signal to the NMOS 14.
The AND circuit 210 outputs a logical product of the output of the NAND circuit 188 and the PWM signal to the NMOS 16.
The AND circuit 212 outputs the logical product of the output of the NAND circuit 196 and the PWM signal to the NMOS 18.

=== Operation of Motor Driven Integrated Circuit ===
The operation of the motor drive integrated circuit of the present invention will be described with reference to FIGS. FIG. 7 is a waveform diagram showing a composite signal of the motor drive integrated circuit according to the present invention.

  The synthesizing circuit 28 synthesizes the mask signals UMASK, VMASK, and WMASK to generate a synthesized signal FG, which is output to the multiplier circuit 30. The rising and falling changes of the composite signal FG coincide with the zero crossing of the coil voltages VU, VV, and VW.

  The multiplication circuit 30 multiplies the combined signal FG into a rectangular signal RE1 having a period that is an integral multiple of the combined signal FG, for example, 16 times. That is, a rectangular signal RE1 having 16 periods (16 pulses) is generated in a half period between the rising edge and the falling edge of the composite signal FG. In the multiplier circuit 30, the immediately preceding 1/2 cycle is actually reflected in the operation of the next 1/2 cycle. Specifically, when the half cycle of the combined signal FG in the period T1 is “b”, the multiplier circuit 30 operates to generate 16 pulses within the “b” period in the next period T2.

  The rectangular signal RE1 is input to the mask circuit 26, and is used to remove (mask) noise corresponding to the kickback pulse KB from the comparison signals CPU, CPV, CPW. In the mask circuit 26, mask signals UMASK, VMASK, and WMASK are generated by removing the noise corresponding to the kickback pulse KB from the comparison signals CPU, CPV, and CPW. Further, the mask circuit 26 generates a MASK signal based on the rectangular signal RE1. The period in which the MASK signal is “H” indicates the period before and after the level of each of the UH, UL, VH, VL, WH, and WL signals changes within a ½ cycle of the combined signal FG.

  Further, ULOGIC2, VLOGIC2, and WLOGIC2 are output from the sensorless logic circuit 40 based on the mask signals UMASK, VMASK, and WMASK. The signal processing circuit 44 outputs binary level signals UH, UL, VH, VL, WH, and WL for driving the NMOSs 8, 10, 12, 14, 16, and 18.

  In the switching circuit 52, among the outputs of the signal processing circuit 44, signals whose output level changes while the MASK signal is “H” are switching signals M 1, M 2, M 3, M 4, M 5 output from the timing synthesis circuit 50. , M6 to switch to the output of the comparator 46 or the comparator 48. For example, in the TA period of FIG. 3, the UH signal changes from “L” to “H”, and the WH signal changes from “H” to “L”. The UH signal is switched to the output of the comparator 48 whose duty gradually increases when the M1 signal becomes “H”, and the WH signal gradually changes in duty when the M1 signal becomes “H”. The output of the comparator 46 is decreased.

  The PWM combining circuit 54 combines the output of the comparators 46 and 48 or the output of the signal processing circuit 44 output from the switching circuit 52 with the PWM signal. Then, the NMOSs 8, 10, 12, 14, 16, 18 are driven at an appropriate timing by the combined signal.

  The PWM signal output from the DFF 60 is a signal synchronized with the clock signal CLK. Therefore, as shown in FIG. 7, the soft switch signal output from the comparator 46 and the comparator 48 and the PWM signal are also synchronized. Then, by synthesizing the PWM signal and the soft switch signal, it is possible to generate a synthesized signal whose duty changes regularly.

  As described above, even when the clock signal is generated inside the IC and the PWM signal is input from the outside, the DFF 60 can synchronize the soft switch signal and the PWM signal. Therefore, a soft switch can be performed effectively, and the motor drive sound can be silenced.

=== Other Embodiments ===
The motor driving integrated circuit of the present invention can be used in addition to a three-phase sensorless motor. For example, it can also be used for a three-phase motor having a Hall element that detects the relative position of the rotor with respect to the stator.
Also in a single-phase motor, the motor driving sound can be silenced by gradually changing the current for a predetermined period before and after the switching of the current flowing through the coil.

As described above, the PWM signal and the soft switch signal can be synchronized by synchronizing the PWM signal with the clock signal CLK. Therefore, even when the clock signal CLK is generated inside the IC and the PWM signal is input from the outside of the IC, the motor driving sound can be effectively silenced.
Further, by using the DFF 60, the PWM signal can be synchronized with the clock signal with a simple configuration.

  Also, for example, the output of the 4-bit CLK counter 42 that counts the number of pulses of the clock signal CLK is compared with the output of the 4-bit RE1 counter that counts the number of pulses of the RE1 signal having a period different from that of the clock signal CLK, for example. Thus, a soft switch signal whose duty gradually changes can be generated. Further, the comparator 48 can generate a soft switch signal whose duty gradually increases, and the comparator 46 can generate a soft switch signal whose duty gradually decreases. A signal that changes from “L” to “H” in the output of the signal processing circuit 44 in accordance with the switching signal output from the timing synthesis circuit 50 during the period when the MASK signal is “H” by the switching circuit 52. Can be switched to the output of the comparator 48, and the signal that changes from “H” to “L” among the outputs of the signal processing circuit 44 can be switched to the output of the comparator 46.

  Further, the output of the comparator 46 or the output of the comparator 48 output from the switching circuit 52 and the PWM signal output from the DFF 60 can be synchronized. Therefore, the current change at the switching of energization can be smoothed by the composite signal synthesized by the PWM synthesis circuit 54.

  As described above, the present embodiment has been specifically described based on the embodiment. However, the present embodiment is not limited to this, and various modifications can be made without departing from the scope of the present embodiment.

It is a circuit block diagram for demonstrating the integrated circuit for motor drive concerning this invention. It is a wave form diagram for demonstrating the integrated circuit for motor drive concerning this invention. It is a wave form diagram for demonstrating the integrated circuit for motor drive concerning this invention. It is a figure for demonstrating the output of the comparators 46 and 48. FIG. It is a circuit diagram which shows an example of a structure of a switching circuit and a PWM synthetic | combination circuit. It is a figure which shows an example of a structure of RE1 counter. It is a wave form diagram which shows the synthetic signal of the integrated circuit for motor drive concerning this invention. It is a figure for demonstrating the change of the coil electric current which flows into a three-phase coil. It is a figure for demonstrating the current waveform which flows into each phase of the integrated circuit for motor drive. It is a wave form diagram which shows a synthetic | combination signal when a soft switch signal and a PWM signal are not synchronizing.

Explanation of symbols

2 U-phase coil 4 V-phase coil 6 W-phase coil 8, 10, 12, 14, 16, 18 NMOS
22U, 22V, 22W Comparator 26 Mask circuit 28 Synthesis circuit 30 Multiplication circuit 34 RE1 counter 38 Oscillation circuit 40 Sensorless logic circuit 42 CLK counter 44 Signal processing circuit 46, 48 Comparator 50 Timing synthesis circuit 52 Switching circuit 54 PWM synthesis circuit 60, 70 , 72, 74, 76 DFF

Claims (5)

A plurality of transistors for sequentially supplying currents in different directions to the coil;
An output circuit for outputting a binary level drive signal for switching and driving the plurality of transistors;
An oscillation circuit for generating an oscillation signal of a first period;
An input terminal to which a PWM signal of a second period (> the first period) is input;
A rectangular signal generating circuit for sequentially generating rectangular signals of the second period with a variable duty based on the oscillation signal in a predetermined period (> second period) before and after the level of the drive signal changes; ,
A synchronization circuit for synchronizing the PWM signal and the rectangular signal;
A selection circuit that selects a logical product signal of the synchronized PWM signal and the rectangular signal instead of the drive signal in the predetermined period;
An integrated circuit for driving a motor. The synchronization circuit includes:
A D-type flip-flop that holds and outputs the PWM signal at a timing when the oscillation signal changes;
The motor drive integrated circuit according to claim 1, wherein the PWM signal is synchronized with the oscillation signal. The rectangular signal generation circuit includes:
A first counter that counts the predetermined period using a signal of a third period (> the first period);
A second counter that repeatedly counts the second period using the oscillation signal of the first period;
A comparator that compares the count value of the first counter with the count value of the second counter and outputs the rectangular signal;
The integrated circuit for driving a motor according to claim 1, wherein: The duty is a duty for driving the plurality of transistors,
The comparator comprises: a first comparator that outputs a rectangular signal that increases the duty every second period; and a second comparator that outputs a rectangular signal that decreases the duty every second period;
The selection circuit selects a logical product signal of the rectangular signal output from the first comparator and the PWM signal for a predetermined period before and after the drive signal level rises, and before and after the drive signal level falls. In a predetermined period of time, a logical product signal of the rectangular signal output from the second comparator and the PWM signal is selected.
The motor driving integrated circuit according to claim 3. The selection circuit includes:
A switching circuit that selects the driving signal at a time other than the predetermined period, and selects the rectangular signal at the predetermined period;
5. The motor drive integrated circuit according to claim 1, further comprising: a PWM synthesis circuit that outputs a logical product signal of the output signal of the switching circuit and the PWM signal.

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