JP4709560B2 - Motor drive device - Google Patents

Description

  The present invention relates to a motor drive device.

  A motor (for example, a sensorless three-phase brushless DC motor) driving device is connected in series between a power supply voltage VP and a ground VSS as an output stage, and one end of a coil is connected to the connection point of the source on the power supply voltage VP side. Each of the three-phase coils includes a side transistor and a ground VSS side sink side transistor. The other ends of the three-phase coils are connected in common. In addition, the motor driving device has a control circuit that controls driving of the source-side transistor and the sink-side transistor connected to the three-phase coil.

  FIG. 9 is a diagram for explaining the output configuration of the three-phase motor. One end of the U-phase coil 2 is connected in series with an N-channel MOSFET (hereinafter referred to as NMOS) 8 of a source side transistor and an NMOS 10 of a sink side transistor. One end of the V-phase coil 4 is connected in series with a source-side transistor NMOS 12 and a sink-side transistor NMOS 14. One end of the W-phase coil 6 is connected in series with an NMOS 16 as a source side transistor and an NMOS 18 as a sink side transistor. The other ends of the drive coils 2, 4, 6 are connected in common at point C. The control circuit (not shown) selectively drives the NMOS 8, 10, 12, 14, 16, and 18 in an appropriate order by combining a source-side transistor of one phase and a sink-side transistor of another phase as one combination. .

  FIG. 7 is a diagram for explaining the relationship between the drive voltage applied to the coils of each phase during the rotation of the motor, for example, forward rotation, and the counter electromotive voltage generated in proportion to the rotation of the motor. FIG. 7A shows the back electromotive force of each phase coil, and FIG. 7B shows the drive voltage applied to each phase coil. As shown in FIG. 7B, the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 have a high level (upper part of the staircase waveform), a middle level (center part of the staircase waveform), and a low level. Driving voltages that are sequentially switched (lower part of the stepped waveform) are applied with a phase difference of 120 degrees in electrical angle. Here, during a period in which the source-side transistor connected to one end of the coil of each phase is to be turned on, the drive voltage for the coil is at a high level. Further, during a period in which the sink-side transistor connected to one end of the coil of each phase is to be turned on, the driving voltage for the coil is at a low level. Further, during the period in which both the source-side transistor and the sink-side transistor connected to one end of the coil of each phase are to be turned off, the driving voltage for the coil becomes a middle level. For example, in the period a in FIG. 7, the U-phase NMOS 8 and the V-phase NMOS 14 in FIG. 9 are on. Similarly, in the period b, the U-phase NMOS 8 and the W-phase NMOS 18 are on, and in the period c, the V-phase NMOS 12 and the W-phase NMOS 18 are on.

  The counter electromotive voltages of the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 are sinusoidal waves having a phase difference of 120 degrees in electricity as shown in FIG. Then, a current corresponding to the difference between the drive voltage and the counter electromotive voltage flows through the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 (see, for example, Patent Document 1).

  In this way, by switching the energization phase every 60 degrees of electrical angle, the motor rotates forward, for example. As one of motor driving methods, there is known PWM (Pulse Width Modulatin) control for driving a motor by intermittently supplying a driving current to a coil. In PWM control, either the source-side transistor or the sink-side transistor that is driven in energization every 60 degrees of electrical angle is intermittently turned on / off at a predetermined frequency, and a drive current corresponding to the on / off duty is generated. The motor is driven by flowing through the coil.

  The control circuit is set with a forward rotation logic for switching the energized phase to rotate the motor in the forward direction and a reverse rotation logic for switching the energized phase to rotate the motor in the reverse direction. When the motor is rotated in reverse, the logic of the control circuit is switched to reverse logic.

Switching between forward rotation logic and reverse rotation logic is performed, for example, by comparing a control voltage VCTL (hereinafter simply referred to as VCTL) input from a microcomputer or the like with a predetermined reference voltage VREF (hereinafter simply referred to as VREF). FIG. 8 is a diagram for explaining switching between forward rotation logic and reverse rotation logic. In FIG. 8, when VCTL> VREF, the forward logic is obtained, and when VCTL <VREF, the reverse logic is obtained. The duty of PWM control is determined according to the slope of the solid line S when VCTL> Va, and according to the slope of the solid line G when VCTL <Vb. In FIG. 8, the range where the value of VCTL is Vb <VCTL <Va is a dead zone in which the value of the drive current cannot be determined. In this range, the PWM on-duty is 0%.
JP 2000-236684 A

  Problems in the PWM control of the conventional motor drive device will be described with reference to FIGS. 7, 9, and 10. FIG. 10 is a diagram showing a change in voltage at the connection point (hereinafter referred to as point X) between the NMOS 12 and the NMOS 14 when the NMOS 14 is turned on / off during the period when the NMOS 8 in FIG. 9 is on.

  In the period a in FIG. 7, the NMOS 8 and the NMOS 14 are turned on, and the current in the path indicated by the solid line in FIG. 9 flows from the power supply voltage VP → NMOS 8 → U-phase coil 2 → V-phase coil 4 → NMOS 14 → VSS. Here, when the NMOS 14 is turned off by PWM control, the U-phase coil 2 and the V-phase coil 4 continue to flow current in the direction of the solid line, so the power supply voltage VP → NMOS8 → U-phase coil 2 → V-phase coil 4 → A regenerative current of a path indicated by a broken line in FIG. 9 flows from the regenerative diode D3 to the power supply voltage VP.

  The voltage at the point X changes as shown in FIG. That is, during the period when the NMOS 14 is turned on and the current in the solid line path flows (t <ta), the voltage at the point X becomes the saturation voltage VL of the NMOS 14, but when the NMOS 14 is turned off at t = ta, the broken line path Therefore, the voltage at the point X becomes VP + VF obtained by adding the forward voltage VF of the regenerative diode D3 to the power supply voltage VP. For this reason, the voltage at the point C also increases, that is, the midpoint voltage of the back electromotive voltage amplitude shown in FIG. 7 increases. Then, the relationship between the back electromotive voltage and the drive voltage changes. As a result, the U-phase coil 2 and the V-phase coil 4 gradually try to pass a current in the reverse direction.

  For example, when the regenerative current of the broken line in FIG. 9 is flowing, if the NMOS 14 is turned on, the current of the solid line flows again, but if the off period of the NMOS 14 continues until no regenerative current flows in the broken line direction, A current in a path in the direction opposite to the solid line of VSS → regenerative diode D4 → V phase coil 4 → U phase coil 2 → NMOS 8 → power supply voltage VP flows.

  As described above, when the PWM off period continues until the regenerative current stops flowing, the current flows from the ground VSS to the power source VP. Therefore, the power supply voltage VP may be raised. Also, the NMOS 8 that is originally a source side transistor serves as a sink side transistor, and the PWM operation becomes unstable.

  The same problem occurs when the source side transistor is PWM-controlled. For example, when the NMOS 8 is intermittently turned on / off while the NMOS 14 is on, when the NMOS 8 is turned off, the path of the ground VSS → the regenerative diode D 2 → the U phase coil 2 → the V phase coil 4 → the NMOS 14 → the ground VSS. The regenerative current flows. However, if the NMOS 8 continues off until the regenerative current stops flowing, a current of a path opposite to the solid line flows, that is, ground VSS → NMOS 14 → V phase coil 4 → U phase coil 2 → regenerative diode D1 → power supply voltage VP. .

  Here, in the dead zone shown in FIG. 8, the PWM on-duty is 0% as described above. Therefore, when VCTL becomes a voltage in the dead band range (Vb <VCTL <Va) while the motor is rotating, the PWM on-duty becomes 0%, so that a current flows from the ground VSS to the power supply voltage VP. It becomes like this. Therefore, the power supply voltage VP is raised.

  As described above, in the conventional motor driving apparatus, when the motor is rotating, for example, when the VCTL becomes a voltage in the dead band range, and the PWM off period continues until the regenerative current stops flowing, the power supply voltage As a result, the PWM operation becomes unstable.

  Therefore, an object of the present invention is to provide a motor drive device that can realize a stable PWM operation regardless of the PWM off period.

The main invention for solving the above problems is that a first source side transistor that discharges a drive current in one direction of the coil, a first sink side transistor that sucks a drive current flowing in one direction of the coil, and the other of the coil A second source side transistor that discharges a driving current in a direction, a second sink side transistor that sucks a driving current flowing in the other direction of the coil, the first source side transistor, the first sink side transistor, and the second source. Side transistor, a regenerative diode for regenerating current flowing in the coil when the second sink side transistor is selectively turned off, the first source side transistor and the first sink side transistor, or the second source side Outputs a drive signal for selectively driving a transistor and the second sink side transistor And a control circuit that varies the magnitude of the drive signal in accordance with an instruction signal that determines the magnitude of the drive current, and one of the first source-side transistor and the first sink-side transistor, or the first And a PWM control circuit that outputs a PWM control signal for selectively PWM driving one of the two source side transistors and the second sink side transistor, and a first voltage corresponding to the instruction signal. And a second voltage corresponding to the voltage generated in the voltage detection resistor through which the drive current flows, and a predetermined magnitude that the instruction signal cannot determine the magnitude of the drive current The comparator outputs a determination signal of a predetermined level, and the comparator outputs the determination signal of the predetermined level. When the PWM off period of one of the first source side transistor and the first sink side transistor or one of the second source side transistor and the second sink side transistor exceeds a predetermined period, the detection signal And the control circuit, based on the detection signal, the first source side transistor and the first sink side transistor, or the second source side transistor and the second sink side. of the transistors, it turns off the transistors on the side that was driven, the current flowing before Symbol coil outputs a drive signal for driving the side of a transistor which is not driven to be regenerated, and wherein the To do.

  According to the present invention, a stable PWM operation can be realized regardless of the PWM off period.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

=== Configuration of Motor Drive Device ===
A motor driving apparatus according to the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a circuit block diagram for explaining a motor drive device according to the present invention. FIG. 2 is a waveform diagram for explaining the motor driving apparatus according to the present invention. In this embodiment, the motor is a sensorless motor under PWM control, for example, a three-phase brushless DC motor.

  The U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 are motor coils, and are wound around the stator with a star connection and a phase difference of 120 electrical degrees.

  The NMOS 8 is a source side transistor for supplying a coil current from the power source VP to the U-phase coil 2, and the NMOS 10 is a sink for supplying a coil current from the U-phase coil 2 to the ground VSS via the voltage detection resistor 50. Side transistor. The drain / source paths of the NMOSs 8 and 10 are connected in series to the power source VP and the non-ground side of the resistor 50, and the drain / source connection portions of the MOSFETs 8 and 10 are connected to one end of the U-phase coil 2. The NMOS 12 is a source side transistor for supplying a coil current from the power source VP to the V-phase coil 4, and the NMOS 14 is a sink for supplying the coil current from the V-phase coil 4 to the ground VSS via the voltage detection resistor 50. Side transistor. The drain / source paths of the NMOSs 12 and 14 are connected in series to the power source VP and the non-ground side of the voltage detection resistor 50, and the drain / source connection part of the NMOSs 12 and 14 is connected to one end of the V-phase coil 4. Yes. The NMOS 16 is a source side transistor for supplying a coil current from the power source VP to the W-phase coil 6, and the NMOS 18 is a sink for supplying a coil current from the W-phase coil 6 to the ground VSS via the voltage detection resistor 50. Side transistor. The drain / source paths of the NMOSs 16 and 18 are connected in series to the power supply VP and the non-ground side of the voltage detection resistor 50, and the drain / source connection portions of the NMOSs 16 and 18 are connected to one end of the W-phase coil 6. Yes. When the NMOSs 8, 10, 12, 14, 16, 18 are turned on / off at appropriate timings, the motor is supplied with coil currents to the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 and is predetermined. It will rotate to the direction (for example, normal rotation). As a result, coil voltages VU, VV, and VW having a phase difference of 120 electrical degrees are generated at one end of the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6. In addition, it is possible to use not only MOSFETs but also bipolar transistors as source side transistors and sink side transistors. Further, regenerative diodes D1, D2, D3, D4, D5, and D6 are connected to the NMOSs 8, 10, 12, 14, 16, and 18, respectively, between the drain and the source.

  The comparator 22U is applied with the coil voltage VU applied to the + terminal and the neutral point voltage VCOM applied to the − terminal, and changes at the timing of an electrical angle of 180 degrees by comparing the coil voltage VU and the neutral point voltage VCOM. The rectangular comparison signal CPU is output. A pulse based on the kickback pulse KB is superimposed on the comparison signal CPU. In addition, the comparator 22V receives the coil voltage VV applied to the + terminal and the neutral point voltage VCOM applied to the − terminal, and compares the coil voltage VV and the neutral point voltage VCOM so that the timing of the electrical angle is 180 degrees. The rectangular comparison signal CPV that changes in the above is output. A pulse based on the kickback pulse KB is superimposed on the comparison signal CPV. Further, the comparator 22W receives the coil voltage VW at the + terminal and the neutral point voltage VCOM at the − terminal, and compares the coil voltage VW with the neutral point voltage VCOM to thereby obtain a timing of an electrical angle of 180 degrees. A rectangular comparison signal CPW that changes at A pulse based on the kickback pulse KB is superimposed on the comparison signal CPW. The comparison signals CPU, CPV, and CPW each have a phase difference of 120 electrical degrees.

  The mask circuit 26 removes (masks) noise corresponding to the kickback pulse KB from the comparison signal CPU, which is the output of the comparator 22U, based on the rectangular signal RE1, and generates and outputs a mask signal UMASK. The mask circuit 26 removes (masks) noise corresponding to the kickback pulse KB from the comparison signal CPV output from the comparator 22V based on the rectangular signal RE1, and generates and outputs a mask signal VMASK. Further, the mask circuit 26 removes (masks) noise corresponding to the kickback pulse KB from the comparison signal CPW, which is the output of the comparator 22W, based on the rectangular signal RE1, and generates and outputs a mask signal WMASK. Here, the mask signals UMASK, VMASK, and WMASK have a phase difference of an electrical angle of 120 degrees.

  The combining circuit 28 combines the mask signals UMASK, VMASK, and WMASK output from the mask circuit 26, and outputs a rectangular combined signal FG that changes at a timing of an electrical angle of 60 degrees.

  The multiplier circuit 30 generates a rectangular signal RE1 having a higher frequency than the combined signal FG by multiplying the combined signal FG output from the combining circuit. As a result, the phase of the synthesized signal FG matches the phase of the rectangular signal RE1, and the ½ period of the synthesized signal FG matches the n period (for example, 16 periods) of the rectangular signal RE1. For example, a PLL (Phase Locked Loop) that performs analog signal processing and a DLL (Delay Locked Loop) that performs digital signal processing can be applied to the multiplication circuit 30.

  The sensorless logic circuit 40 (“control circuit”) outputs a signal (“drive signal”) for energizing the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 at an appropriate timing. In other words, the sensorless logic circuit 40 considers that the sensorless motor itself cannot determine the relative position between the rotor and the stator before starting, and when the rotor is stopped, the mask signals UMASK, VMASK, and WMASK are predetermined. It operates from the initial level (for example, UMASK = “L”, VMASK = “L”, WMASK = “H”). In addition, the sensorless logic circuit 40 creates energization signals ULOGIC1 (= UMASK-VMASK), VLOGIC1 (= VMASK-WMASK), and WLOGIC1 (= WMASK-UMASK). When the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 are energized, the sensorless logic circuit 40 outputs energization signals ULOGIC2, VLOGIC2, and WLOGIC2 that are delayed from the energization signals ULOGIC1, VLOGIC1, and WLOGIC1.

  In addition, the sensorless logic circuit 40 receives a PWM signal from a D-type flip-flop circuit (hereinafter referred to as DFF) 60, and supplies either a source-side transistor or a sink-side transistor that is driven by energization every 60 degrees of electrical angle. PWM control for intermittently turning on / off at a predetermined frequency is performed. Further, the sensorless logic circuit 40 receives the REV signal from the DFF 66, and when the REV signal changes from “L” to “H”, the sensorless logic circuit 40 switches to the reverse logic for the specific two phases.

The amplifier 52 amplifies the difference between VCTL (“instruction signal”) and VREF.
The amplifier 54 amplifies the voltage generated in the voltage detection resistor 50 with, for example, the same gain as that of the amplifier 52 (for convenience, 1).
The output of the amplifier 52 is applied to the non-inverting input terminal (+ terminal) of the comparator 56 (“comparator”), and the offset voltage V0 (“ A voltage obtained by adding a “constant voltage”) is applied. The comparator 56 compares the magnitude relationship between the output of the amplifier 54, the added voltage of the offset voltage V0, and the output of the amplifier 52, and outputs a PWMOFF signal that is the comparison result.
The oscillation circuit 58 generates a pulse signal PWMCLK having a constant cycle.

  For example, a high level voltage of the power supply voltage VP is applied to the data input (hereinafter referred to as D input) of the DFF 60 (“PWM control circuit”). The clock input (hereinafter referred to as C input) of the DFF 60 is connected to the output of the oscillation circuit 58, and the reset input (hereinafter referred to as R input) is connected to the output of the comparator 56. The DFF 60 outputs a PWM signal from the Q output to the sensorless logic circuit 40. The DFF 60 outputs a PWM signal that becomes “H” when the PWMCLK signal becomes “H” while the PWMOFF signal is “H”, and is reset when the PWMOFF signal becomes “L”.

The inverter 62 inverts the PWMOFF signal and outputs a LIM signal.
The D input and R input of the DFF 64 are connected to the output of the inverter 62, and the C input is connected to the output of the oscillation circuit 58. The Q output of DFF 64 is connected to the D input of DFF 66. The DFF 64 outputs a signal that becomes “H” when the PWMCLK signal becomes “H” while the LIM signal is “H”, and is reset and becomes “L” when the LIM signal becomes “L”.

  The C input of the DFF 66 is connected to the output of the oscillation circuit 58, and the R input is connected to the output of the inverter 62. The D input of DFF 66 is connected to the Q output of DFF 64. The DFF 66 outputs a REV signal that becomes “H” when the PWMCLK signal becomes “H” while the Q output of the DFF 64 is “H”, and is reset and becomes “L” when the LIM signal becomes “L”.

The amplifier 52, the amplifier 54, and the comparator 56 constitute a discrimination circuit, and the inverter 62, DFF 64, and DFF 66 constitute a detection circuit.
Further, in FIG. 1, the portions excluding the U-phase coil 2, the V-phase coil 4, and the W-phase coil 6 can be integrated. In that case, since the parasitic diodes are formed between the source and the drain in the NMOSs 8, 10, 12, 14, 16, and 18, the regenerative diodes D1, D2, D3, D4, D5, and D6 may not be provided.

=== Operation of PWM control ===
The operation of PWM control in the motor drive device of the present invention will be described with reference to FIGS. 1, 3, 4, 5, and 9. FIG. FIG. 3 is a diagram for explaining the relationship between VCTL and the offset voltage V0. FIG. 4 is a time chart for explaining the PWM control operation of the motor drive device of the present invention. FIG. 5 is a flowchart for explaining the PWM control operation of the motor drive device of the present invention.

First, generation of the PWMOFF signal will be described.
3A and 3B, the vertical axis V indicates the output of the amplifier 52.

  In the amplifier 52, the difference between VCTL and VREF is amplified. The output of the amplifier 52 is 0 volt when the VCTL is VREF as shown in FIG. It is set to rise linearly. The amplifier 54 amplifies the voltage generated in the voltage detection resistor 50 with the same gain as the amplifier 52.

  The broken line in FIG. 3B is a voltage obtained by adding the offset voltage V 0 to the output of the amplifier 54 when no current flows through the voltage detection resistor 50. In the dead band range of Vb <VCTL <Va, the sum of the output of the amplifier 54 and the offset voltage V0 is larger than the output of the amplifier 52.

  The output of the amplifier 54, the added voltage of the offset voltage V0, and the output of the amplifier 52 are compared in magnitude by the comparator 56. When the output of the amplifier 52 is greater than the sum of the output of the amplifier 54 and the offset voltage V0, the output PWMOFF signal of the comparator 56 is at a high level (hereinafter referred to as “H”). On the other hand, when the output voltage of the amplifier 54 and the added voltage of the offset voltage V0 are larger than the output of the amplifier 52, the PWMOFF signal is at a low level (hereinafter referred to as “L”).

  When VCTL becomes a voltage in the dead band range (“predetermined magnitude”), the sum of the output of the amplifier 54 and the offset voltage V0 becomes larger than the output of the amplifier 52, so the PWMOFF signal is fixed at “L”. It becomes. Further, the LIM signal obtained by inverting the PWMOFF signal by the inverter 62 becomes “H”.

Next, the operation of PWM control will be described using FIG. 4 and FIG.
First, it is assumed that VCTL is a voltage outside the range of the dead zone.
The PWMCLK signal output from the transmission circuit 58 is a pulse signal having a constant period tpwm as shown in FIG.

  When the pulse of the PWMCLK signal is input to the DFF 60 at time t1 in FIG. 4, the PWM signal becomes “H”. (S100). When the PWM signal becomes “H”, a drive current flows and the voltage generated in the voltage detection resistor 50 increases. At time t2, the sum of the output of the amplifier 54 and the offset voltage V0 becomes larger than the output of the amplifier 52, and the PWMOFF signal becomes “L”. Therefore, the DFF 60 is reset and the PWM signal becomes “L” (S102). When the PWM signal becomes “L”, the voltage generated in the voltage detection resistor 50 decreases, and the output of the amplifier 52 becomes larger than the sum of the output of the amplifier 54 and the offset voltage V0. Therefore, the PWMOFF signal becomes “H” immediately after becoming “L”. Similarly, the PWM signal becomes “L” when the pulse of the PWMCLK signal is inputted at time t3 to t7, and becomes “L” when the PWMOFF signal becomes “L”. Thus, the PWM signal at times t1 to t7 is a PWM signal that repeats “H” and “L” at the pulse interval tpwm of the PWMCLK signal.

  However, for example, when VCTL becomes a voltage in the dead zone at time t8, the PWMOFF signal is fixed to “L”, that is, the LIM signal is set to “H” (S104). Then, even if the pulse of the PWMCLK signal is input to the DFF 60 at time t9, the PWM signal remains “L”.

  When the PWMOFF signal is “H” at the time of the next pulse input of the PWMCLK signal, that is, when the LIM signal is “L” (S106: NO), the PWM signal becomes “H” by the pulse input, and Step 102 is executed again. To do.

  On the other hand, as shown at time t10 in FIG. 4, when the LIM signal is “H” when the next PWM pulse signal is input (S106: YES), the REV signal that is the Q output of the DFF 66 becomes “H”, The reverse logic is output to the sensorless logic circuit 40 as a signal for switching between two specific phases (S108).

  Next, the PWM control method of the motor drive device of the present invention will be described with reference to FIG. First, in FIG. 9, it is assumed that PWM control is performed to intermittently turn on / off the NMOS 14 during a period in which the NMOS 8 is on. Power supply voltage VP → NMOS8 → U-phase coil 2 → V-phase coil 4 → NMOS14 → When the NMOS 14 is turned off in a state where the current in the solid line of the ground VSS flows, the power supply voltage VP → NMOS8 → U-phase coil 2 → A regenerative current flows in the path of V-phase coil 4 → regenerative diode D3 → power supply voltage VP.

  Here, for example, when VCTL becomes a voltage in the dead band range and the NMOS 14 is turned off until the regenerative current stops flowing, the U-phase coil 2 and the V-phase coil 4 are connected to the ground VSS → regenerative diode D4 → drive coil 4. → Drive coil 2 → NMOS 8 → A current in the direction opposite to the solid line of the power supply voltage VP is applied. Therefore, when the “H” REV signal is input, the sensorless logic circuit 40 switches the logic for two phases, for example, the U phase and the V phase. In this case, PWM control is performed in which the NMOS 12 is intermittently turned on / off during the period in which the NMOS 10 is on, but the NMOS 12 is off because the PWM on-duty is 0%. Therefore, the regenerative current of ground VSS → regenerative diode D4 → drive coil 4 → drive coil 2 → NMOS 10 flows.

  When the REV signal becomes “H”, the energy stored in the U-phase coil 2 and the V-phase coil 4 can be released by regenerating the current in this way. And when the energy stored in the U-phase coil 2 and the V-phase coil 4 is lost, the regenerative current does not flow. As described above, when the REV signal becomes “H”, for example, by switching the logic for the U phase and the V phase, it is possible to prevent the power supply voltage VP from rising due to the current flowing from the ground VSS to the power supply voltage VP.

  Similarly, when the PWM control of the other phase is performed, the logic is switched for a specific two phase when the REV signal becomes “H”. As a result, current can be regenerated between the sink-side transistors or the source-side transistors in specific two phases, and current can be prevented from flowing from the ground VSS to the power supply voltage VP. Therefore, it is possible to prevent the power supply voltage VP from rising and to perform stable PWM control.

  When the DFF 64 and DFF 66 constituting the detection circuit are one DFF, a malfunction may occur if the “L” period of the PWMOFF signal overlaps the pulse of the PWMCLK signal. Since the DFF 64 and the DFF 66 are provided in the present embodiment, the output REV signal changes when the PWMCLK pulse is input twice while the LIM signal is “H”. Therefore, it is possible to accurately detect that the PWM off period continues with a simple configuration. If the detection circuit is constituted by three or more DFFs, it is possible to more reliably detect that the PWM on-duty is in the 0% state.

=== Other Embodiments ===
The motor driving device of the present invention can be used in addition to a sensorless three-phase brushless DC motor. For example, you may use for the PWM control of the three-phase motor which has a Hall element which detects the relative position of the rotor with respect to a stator. Also in this case, when the REV signal becomes “H”, stable PWM control can be realized by switching the logic for specific two phases.

  Similarly, the motor driving device of the present invention can be applied to a single-phase motor. FIG. 6 is a diagram for explaining the operation when the motor driving apparatus of the present invention is applied to a single-phase motor. At one end of the coil 609, an NMOS 601 and an NMOS 602 are connected in series between the power supply voltage VP and the non-grounded side of the voltage detection resistor 50. Further, NMOS 603 and NMOS 604 are connected in series between the power supply voltage VP and the non-grounded side of the voltage detection resistor 50 at the other end of the coil 609. Regenerative diodes 605, 606, 607, and 608 are connected to the NMOS 601, 602, 603, and 604, respectively.

  The control circuit (not shown) selectively drives the NMOSs 601, 602, 603, and 604 by combining the NMOSs 601 and 604 and the NMOSs 602 and 603. Further, it is assumed that the configuration of the determination circuit for generating the PWM signal and the REV signal, the PWM control circuit, and the detection circuit are the same as those in FIG. It is assumed that the control circuit receives the PWM signal and the REV signal and performs PWM control for intermittently turning on / off the NMOS 604 based on the PWM signal, for example, during a period in which the NMOS 601 is on.

  When the PWM signal becomes “H” and the NMOS 604 is turned on, a path current indicated by a solid line in FIG. 6 flows in the path of the power supply voltage VP → NMOS 601 → coil 609 → NMOS 604 → voltage detection resistor 50 → ground VSS. Then, when the PWM signal becomes “L” and the NMOS 604 is turned off, a regenerative current flows along the one-dot chain line in FIG. 6 of the power supply voltage VP → NMOS 601 → the coil 609 → the regenerative diode 607 → the power supply voltage VP. When the on-duty of PWM becomes 0% and the regenerative current of this one-dot chain line does not flow, the current of the path opposite to the solid line of ground VSS → voltage detection resistor 50 → regenerative diode 608 → coil 609 → NMOS 601 → power supply voltage VP. Will flow.

  Therefore, the control circuit switches the logic when the REV signal of “H” is input. Then, for example, PWM control is performed to intermittently turn on / off the NMOS 603 while the NMOS 602 is on. When the REV signal is “H”, the NMOS 603 is turned off because the PWM on-duty is 0%. Therefore, the regenerative current in the path of the broken line in FIG. 6 flows from the ground VSS to the voltage VSS, the voltage detection resistor 50, the regenerative diode 608, the coil 609, and the NMOS 602, and the energy stored in the coil 609 can be released. It is possible to prevent a current from flowing through the power supply voltage VP.

  As described above, when the REV signal becomes “H”, the motor driving device according to the present invention regenerates current between source-side transistors or between sink-side transistors by switching logic in specific two phases. Therefore, it is possible to prevent a current from flowing from the ground VSS to the power source VP, and stable PWM control can be performed.

  When VCTL becomes a voltage in the dead band range, the PWMOFF signal is fixed to “L” and the LIM signal is fixed to “H”. When the pulse of the PWMCLK signal is input to the DFF 64 and the DFF 66 when the LIM signal is “H”, it can be detected that the PWM on-duty state is 0%.

  Further, since DFF 64 and DFF 66 are provided as detection circuits, the logical value of the output REV signal changes when the pulse of the PWMCLK signal is input twice while the LIM signal is “H”. Therefore, it is possible to reliably detect that the on-duty of the PWM is 0% with a simple configuration.

  Further, when the PWMCLK signal is input to the C input of the DFF 60 and the PWMOFF signal is input to the R input, either the source-side transistor or the sink-side transistor that is driven by energization at every 60 electrical angles is set to a predetermined frequency. Thus, a PWM signal for intermittently turning on / off can be generated.

  Further, since the voltage generated in the voltage detection resistor 50 is amplified by the amplifier 54 having the same gain as the amplifier 52 and the output obtained by adding the offset voltage V0 to the output of the amplifier 52 is compared by the comparator 56, the driving is performed. In the dead zone where no current flows, the output voltage of the amplifier 54 and the added voltage of the offset voltage V0 are larger than the output of the amplifier 52. Therefore, the VCTL becomes a voltage in the range of the dead zone, so that the “L” PWMOFF signal can be accurately output from the comparator 56.

  As described above, the present embodiment has been specifically described based on the embodiment. However, the present embodiment is not limited to this, and various modifications can be made without departing from the scope of the present embodiment.

It is a circuit diagram which shows the structure of the motor drive device concerning embodiment of this invention. It is a wave form diagram for demonstrating the motor drive device concerning embodiment of this invention. It is a figure for demonstrating the relationship between VCTL and offset voltage V0. It is a time chart for demonstrating PWM control operation | movement of the motor drive device of this invention. It is a flowchart for demonstrating the PWM control operation | movement of the motor drive device of this invention. It is a figure for demonstrating operation | movement at the time of applying the motor drive device of this invention to a single phase motor. It is a figure for demonstrating the relationship between a drive voltage and a counter electromotive voltage. It is a figure for demonstrating switching of normal rotation logic and reverse rotation logic. It is a figure for demonstrating the output structure of a three-phase motor. It is a figure which shows the change of the voltage of the X point by PWM control.

Explanation of symbols

2 U-phase coil 4 V-phase coil 6 W-phase coil 8, 10, 12, 14, 16, 18 NMOS
26 Mask circuit 28 Synthesis circuit 30 Multiplication circuit 40 Sensorless logic circuit 50 Voltage detection resistor 52, 54 Amplifier 56 Comparator 60, 64, 66 DFF circuit 62 Inverter V0 Offset voltage D1, D2, D3, D4, D5, D6 Regenerative diode

Claims (4)

A first source-side transistor that discharges drive current in one direction of the coil;
A first sink-side transistor that sucks a drive current flowing in one direction of the coil;
A second source-side transistor that discharges a drive current in the other direction of the coil;
A second sink-side transistor that sucks a drive current flowing in the other direction of the coil;
A regenerative diode that regenerates a current flowing through the coil when the first source side transistor, the first sink side transistor, the second source side transistor, and the second sink side transistor are selectively turned off;
Outputs a drive signal for selectively driving the first source side transistor and the first sink side transistor, or the second source side transistor and the second sink side transistor, and the magnitude of the drive current. A control circuit that varies the magnitude of the drive signal according to an instruction signal that defines
PWM that outputs a PWM control signal for selectively PWM driving one of the first source side transistor and the first sink side transistor, or one of the second source side transistor and the second sink side transistor. A control circuit;
In the motor drive device having
A comparator for comparing a first voltage corresponding to the instruction signal and a second voltage corresponding to a voltage generated in a voltage detection resistor through which the drive current flows, wherein the instruction signal is a magnitude of the drive current; A determination circuit configured to output a determination signal of a predetermined level when the comparator has a predetermined size that cannot be determined;
When the comparator outputs the determination signal of the predetermined level, one of the first source side transistor and the first sink side transistor, or the PWM of one of the second source side transistor and the second sink side transistor. A detection circuit that outputs a detection signal when the off period exceeds a predetermined period;
With
The control circuit is configured to drive the first source side transistor and the first sink side transistor or the second source side transistor and the second sink side transistor on the driven side based on the detection signal. It turns off the transistor, the current flowing before Symbol coil outputs a drive signal for driving the side of a transistor which is not driven to be regenerated, a motor drive device, characterized in that. The detection circuit includes a plurality of stages of flip-flops that take in the determination signal, which becomes one logical value when the instruction signal becomes the predetermined magnitude, with a clock signal for generating the PWM control signal. ,
The motor drive device according to claim 1 , wherein the detection signal is a signal in which an output of the flip-flop at the final stage is changed from one logical value to the other logical value. The PWM control circuit is a single flip-flop that takes in a signal that has one logical value as the clock signal and is reset by the determination signal that has one logical value,
The motor drive device according to claim 2 , wherein the PWM control signal is a signal in which an output of a single flip-flop becomes one of logical values. The comparator includes a first voltage, a second voltage obtained by adding the voltage and the constant voltage generated in the voltage detection resistor, the magnitude relationship between then compared,
If the instruction signal is a predetermined size that can not be determined the magnitude of the drive current, along with said indication signal together with the drive current does not flow is smaller than the constant voltage, said comparator, and it outputs the determination signal as a one logic value, the motor driving apparatus according to claim 2 or 3, characterized in that.

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