JP2006287822A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a synchronizing circuit attaining an improvement in timing margin. <P>SOLUTION: A first conductive type third MOS is provided between a common source for first conductive type first and second MOSs and first potential, second conductive type fourth and fifth MOSs are provided between second potential and drains of the first and second MOSs, and second conductive type sixth and seventh MOSs are provided while cross-connecting their gates and drains in parallel with the fourth and fifth MOSs. An input signal is supplied to a gate of the first MOS, a gate of the second MOS is connected to the drain of the first MOS, a clock is supplied to a gate of the third MOS , a clock of the same phase as the clocks are supplied to gates of the fourth and fifth MOSs, and first and second signals are outputted from the drains of the first and second MOSs and transported to an RS flip-flop circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a synchronization circuit that captures an asynchronous signal with a synchronous clock.

Japanese Patent Laid-Open No. 05-152904 discloses a register circuit that prevents metastable. In this publication, as a problem of the conventional register, since a metastable state occurs and a logic failure occurs, the range in which the metastable state occurs is narrowed. Japanese Patent Application Laid-Open No. 11-150458 discloses a register circuit that generates a complementary signal from a single layer signal. The prototype of the pulsing circuit used in the present invention uses a synchronous logic circuit described in Japanese Patent Laid-Open No. 10-150358.
JP 05-152904 A JP-A-11-150458 JP-A-10-150358

  FIG. 8 shows a conventional circuit shown in Patent Document 1. FIG. 9 shows the characteristics obtained by simulating the circuit of FIG. 5 by the inventor of the present application. The vertical axis in FIG. 9 indicates the delay time from the clock, and the horizontal axis indicates the difference between the input (IN) and the clock (CKT). It can be seen that the delay time of the circuit becomes extremely large when the clock and the input time are close to each other. This indicates that a metastable has occurred. Further, the vicinity of the horizontal axis 0 is not operating, and the smaller this non-operational range, the better the setup and hold characteristics.

  Japanese Patent Application Laid-Open No. 2004-228561 proposes a method of suppressing the occurrence of the metastable state, but this is being solved by delaying the clock of the slave flip-flop circuit with respect to the master latch clock. However, delaying the clock of the slave flip-flop circuit increases the delay time from the clock to the output of the slave flip-flop circuit, and detracts from the timing of the circuits after the slave flip-flop circuit. Or a problem such as a decrease in timing margin occurs.

  Patent Document 2 proposes a register circuit that generates a complementary signal from a single-layer signal. However, when the setup time is sufficient, the register circuit operates without any problem. However, if there is no room in the setup time, the complementary output signals Q, / A delay time difference corresponding to the inverter is generated in Q, which does not become a complementary signal, causing a problem in the timing margin of the subsequent circuit.

  An object of the present invention is to provide a semiconductor device including a synchronization circuit that improves the setup / hold characteristics and timing margin of an input signal. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. In other words, a first conductivity type third MOSFET is provided between a first potential and a first source of the first conductivity type first and second MOSFETs, and a second potential different from the first potential and the first and second potentials. 2nd conductivity type 4th and 5th MOSFETs are provided between the drains of 2MOSFETs, and 6th and 7th MOSFETs of 2nd conductivity type in which the gate and drain are cross-connected are provided in parallel with the 4th and 5th MOSFETs. . An input signal is supplied to the gate of the first MOSFET, the gate of the second MOSFET is connected to the drain of the first MOSFET, a clock is supplied to the gate of the third MOSFET, and the clock is supplied to the gates of the fourth and fifth MOSFETs. An in-phase clock is supplied, and first and second signals are output from the drains of the first and second MOSFETs and transmitted to the RS flip-flop circuit.

  With the above configuration, it is possible to improve the setup / hold characteristics and timing margin of the input signal.

  FIG. 1 is a block diagram showing one embodiment of a master-slave flip-flop circuit according to the present invention. The master-slave flip-flop circuit 1 of this embodiment includes a clock terminal CK, an input terminal D, and output terminals Q and / Q. The master-slave flip-flop circuit 1 includes a master flip-flop circuit 2, a slave flip-flop circuit 3, and a clock timing adjustment unit 8.

  The master flip-flop circuit 2 is composed of a D-flip-flop circuit 5 although not particularly limited. The slave flip-flop circuit 3 includes a pulsing circuit 6 that receives the output signal Q of the D-flip flop circuit 5 and a -flip flop circuit 7. The circuit format of the master flip-flop circuit 2 need not be specified. However, in order to configure a register with a short setup time, it is desirable to employ the D-flip-flop circuit 5 composed of a through latch circuit with a small signal system delay time.

  In this embodiment, only one external clock CK having a positive polarity (true signal) or a negative polarity (bar signal) is supplied to the master-slave flip-flop circuit 1. The clock timing adjustment unit 8 receives the external clock CK and generates an inverted clock signal using an inverter or the like. The timing of the internal positive polarity clock and the negative polarity clock generated by the clock timing adjustment unit 8 is made smaller than the delay time of a normal one-stage inverter as will be described later. By doing so, a region where the flip-flop circuit does not determine the input signal as a high level or a low level is reduced. That is, the range in which the setup time and hold time are not fixed is reduced.

  FIG. 2 is a circuit diagram showing one embodiment of a master-slave flip-flop circuit according to the present invention. The master flip-flop circuit 2 (5) is composed of a through latch circuit. That is, the input signal IN is supplied to the input of the CMOS inverter circuit N4 through a CMOS switch composed of an N-channel MOSFETc and a P-channel MOSFETd. The output signal of the inverter circuit N4 is fed back to the input of the inverter circuit N4 through a clocked inverter as an inverting feedback circuit composed of MOSFETs e to h.

  The pulse generation circuit 6 included in the slave flip-flop circuit 3 includes a differential N-channel MOSFET i, j, an N-channel MOSFET k for controlling the operation thereof, and MOSFETs 1 to o constituting a load circuit. The output signal MB of the master flip-flop circuit 2 is supplied to the gate of the differential MOSFET i. The gate of the differential MOSFET j is connected to the drain of the differential MOSFET i. The MOSFET k is provided between the commonly connected source of the differential MOSFETs i, j and the ground potential, and allows an operating current to flow through the differential MOSFETs i, j in response to the internal clock CLKT. The P-channel MOSFETs l and m constituting the load circuit are provided between the drains of the differential MOSFETs i and j and the power supply voltage VDD. Further, the P-channel MOSFETs n and o constituting the load circuit have a source-drain path connected in parallel to the MOSFETs 1 and m, and a gate and a drain are cross-connected to form a latch. Output signals OT and OB are output from the drains of the differential MOSFETs i, j.

  The flip-flop circuit 7 included in the slave flip-flop circuit 3 includes an input circuit and a CMOS latch circuit. The source of the P-channel MOSFETs p and q constituting the input circuit is supplied with the power supply voltage VDD, and the output signal OT of the pulsing circuit 6 is supplied to the gate. The source of the P channel MOSFETs t, u constituting the input circuit is supplied with the power supply voltage VDD, and the output signal OB of the pulsing circuit 6 is supplied to the gate. An N-channel MOSFETr having the drain of the MOSFETq and the ground potential of the circuit is provided, and the signal OT is supplied to the gate. An N-channel MOSFET v having the drain of the MOSFET u and the ground potential of the circuit is provided, and the signal OB is supplied to the gate. N-channel MOSFETs are provided between the drain of the MOSFETp and the circuit ground potential, and the drain outputs of the MOSFETs u and v are supplied to the gates. An N-channel MOSFET w is provided between the drain of the MOSFET t and the ground potential of the circuit, and the drain output of the MOSFETs q and r is supplied to the gate.

  The CMOS latch circuit is configured by cross-connecting the input and output of a CMOS inverter circuit composed of an N-channel MOSFETx and a P-channel MOSFETy and a CMOS inverter circuit composed of an N-channel MOSFETz and a P-channel MOSFETa '. These cross-connected input / output nodes carry the output signal of the input circuit. That is, the drain output signal of the MOSFETs t and w is supplied to the input of the CMOS inverter circuit (x, y), and the drain output signal of the MOSFETs p and s is input to the input of the CMOS inverter circuit (z, a ′). Supplied. The output signal / Q is output from the CMOS inverter circuit (x, y), and the output signal Q is output from the CMOS inverter circuit (z, a ').

  The timing clock adjustment unit is supplied with a positive external clock CKT. The clock CKT is delayed on the one hand through the inverter circuits N1 and N2, and becomes a positive internal clock CLKT. This clock CLKT is supplied to the gates of the P-channel MOSFETd constituting the CMOS switch of the master flip-flop circuit 2 (5), the N-channel MOSFETe constituting the inverting feedback circuit, and the N-channel MOSFETk of the pulsing circuit 6. On the other hand, the clock CKT is converted into a positive internal clock signal CLKT0 through a parallel circuit of an N channel MOSFETa and a P channel MOSFETb as delay means, and further delayed through an inverter circuit N3 to be a negative internal clock CLKB. The internal clock CLKT0 is supplied to the gates of the P-channel MOSFETs l and m of the pulse circuit 6. The internal clock CLKB is supplied to the gates of an N-channel MOSFET c that constitutes a CMOS switch of the master flip-flop circuit 2 (5) and a P-channel MOSFET h that constitutes an inverting feedback circuit.

  In order to take advantage of the feature of the slave flip-flop circuit 3 that the delay time hardly changes with respect to the input level change on the low level side (or high level side) of the input signal, the output of the master flip-flop circuit 2 is high level ( Alternatively, the logic threshold of the inverter unit is set high so that a low level is easily generated.

  The pulsing circuit 6 which is one of the components of the slave flip-flop circuit 3 is normally (when the input clock level is low level, the two output signals OT and OB are fixed at high level, and the clock CLKT is high). This is a circuit that outputs a low level to the output signal OT or OB according to the input signal MB when it reaches a level, which is characterized in that the output delay time increases when the high level decreases, but the low level is about 2 of the power supply potential. This means that the output delay time does not increase even if it rises by a factor of 1. This occurs because the circuit is differential and the other input is connected to the inverting output.

  The faster the clock CLK supplied to this circuit, the faster the delay time until output and the better the characteristics of the register consisting of a master-slave flip-flop circuit, etc., but metastability is likely to occur. It may be necessary to adjust the timing. The subsequent stage of the slave flip-flop circuit 3 is constituted by an RS-flip flop circuit 7. The circuit 7 is a normal RS flip-flop circuit, for example, a circuit in which two NAND gates are cross-coupled. However, in this embodiment, from the clock input to the output signals Q and / Q. By constructing a high-speed RS flip-flop circuit that can align the delay time, the rise delay time of the output, and the delay time of the fall, the inverted signal / Q and the delay time from the clock to the output are matched. A complementary signal of the non-inverted signal Q can be generated without a time difference.

  In this embodiment, as described above, the external input clock CKT is positive, the internal positive clock CLKT is generated in two stages of inverters N1 and N2, and the internal negative clock CLKB is formed of MOSFETs a and b as delay elements. The time difference is set to be equal to or less than one stage of the normal inverter (the logic threshold is VDD / 2). As a result, in the pulsing circuit 6, the MOSFETs l and m that fix the output signals OT and OB at the high level are turned off in advance, and then the MOSFET k is turned on and input by the differential MOSFETs i and j. The operation of setting either the output signal OT or OB to the low level corresponding to the signal MB can be performed at high speed.

  FIG. 3 is a circuit diagram showing another embodiment of the master-slave flip-flop circuit according to the present invention. In this embodiment, when the external input clock CKB is negative, the internal negative clock CLKB is formed by two stages of inverters N5 and N3, and the internal positive clock CLKT is formed by one stage of the inverter N1. The clock CLKT0 obtained from the output of the inverter N4 is supplied to the gates of the MOSFETs l and m of the pulsing circuit 6. Other configurations are the same as those of the embodiment of FIG. In this embodiment, the time difference between the clocks CLKB and CLKT corresponds to the delay time for one stage of the inverter. However, by shifting the logic threshold voltage of the inverter circuit N5 from VDD / 2, the time difference is made equal to or less than one stage of a normal inverter only when the external clock CKB falls. As a result, the rising timing of the clock CLKT0 obtained from the output of the inverter N5 is made earlier than the rising timing of the internal positive clock CLKT as in the embodiment of FIG.

  FIG. 4 is a circuit diagram showing another embodiment of the master-slave flip-flop circuit according to the present invention. In this embodiment, as in the embodiment of FIG. 2, the external input clock CKT is positive and is supplied as it is to the gates of the MOSFETs k, l, m of the pulsing circuit 6 as the internal positive clock CLKT. The internal negative clock CLKB is formed by one stage of the inverter N3. Also in this embodiment, the logic threshold of the inverter N4 of the master flip-flop circuit 2 is similarly shifted from VDD / 2. Other configurations are the same as those in the above embodiment.

  The pulsing circuit 6 uses a synchronous logic circuit disclosed in Patent Document 3 (Japanese Patent Laid-Open No. 10-150358). In this embodiment, in the synchronous logic circuit, when the input signal MB is high level when the clock CLKT is applied at high level, only the output signal OB is low level. When the input signal MB is low level, only the output signal OT is low level. It is used as a pulsing circuit. The inventor of the present application has found that the pulsing circuit 6 has characteristics such as the input level Vin and the output delay time tPD shown in FIG. 5, and uses them to set up / hold characteristics and timing margins. A flip-flop circuit that improves the above is configured.

  In other words, the slave flip-flop circuit 3 increases the delay time when the amplitude becomes small with respect to the high level of the input signal Vin in the same manner as a normal inverter, but has almost dependency on the low level of the input signal Vin. There is a characteristic that the delay time does not increase even when the voltage rises to VDD / 2. Therefore, the increase in the low level of the input signal Vin does not need to be taken care of, and it is indicated that the design should be made so as to keep the high level as much as possible. That is, the slave flip-flop circuit 3 has a characteristic that the input signal Vin has a large low level margin. Therefore, for example, it is useful as an input circuit that takes in an input signal Vin in which a relatively large noise is placed on the low level side in synchronization with the clock CLKT.

  2 and FIG. 3, the positive logic clock CLKT0 applied to the gates of the pull-up P-channel MOSFETs 1 and m is used at a location different from the clock CLKT applied to the gate of the N-channel MOSFET k. However, this reduces the load on the clock of the N-channel MOSFET k and further speeds up the pulsing circuit 6 by using a clock faster than CLKT as described above.

  In the RS-flip-flop circuit 7 of FIGS. 2, 3 and 4, the two signals OT and OB are normally kept at a high level, but when the signal OT is lowered to a low level, the output signal Q is at a low level. Signal / Q goes high. When the signal OB falls to the low level, the output signal / Q becomes the low level and the output signal Q becomes the high level. Even if the signals OT and OB return to the high level, the above state is held by the CMOS latch circuit. The RS flip-flop circuit 7 of this embodiment is an RS flip-flop circuit that can be set so that the delay times of the output signals Q and / Q, and the rising delay time and the falling delay time are equal.

  FIG. 6 is a characteristic diagram for explaining the operation of the master-slave flip-flop circuit according to the present invention. This figure shows the result of computer simulation of the embodiment circuit of FIG. 2 under the same conditions as the circuit of FIG. As shown in the figure, the occurrence of metastable is suppressed as much as possible, the set-up time / hold time is improved, and the time difference between Q and / Q of the output signal and the difference between the rise delay time and the fall delay time are also It can also be seen that the delay time is faster.

  In this embodiment, the time difference between the internal positive clock CLKT (fast side) and the internal negative clock CLKB (slow side) is made smaller than the delay time of the normal inverter, thereby reducing the setup time + hold time, that is, the dead zone. I can do it. Then, the slave flip-flop circuit 3 determines the delay time of the input signal low level (or high level) and the delay time of the output signals Q and / Q, the rise delay time, and the fall delay time. By configuring with the combined RS-flip flop circuit 7, high-speed inverted output / Q and non-inverted output Q can be obtained. Then, due to the input characteristics of the slave flip-flop circuit 3, the logic threshold of the internal inverter N4 is set higher than VDD / 2 so that the output of the master flip-flop circuit 2 can easily obtain a high level as much as possible. The occurrence of metastable can be suppressed. Even if metastable occurs, the output MB of the master-slave flip-flop circuit 2 can suppress the occurrence of metastable.

  FIG. 7 is a circuit diagram showing still another embodiment of the master-slave flip-flop circuit according to the present invention. In this embodiment, the conductivity type of the MOSFET constituting the circuit is reversed from that of the previous embodiment. That is, as shown in the pulsing circuit 6, the differential MOSFET is constituted by a P-channel MOSFET unlike the above-described FIGS. Corresponding to this, a MOSFET for supplying an operating current to the differential MOSFET is constituted by a P-channel MOSFET, a MOSFET for pulling down the outputs OT and OB, and a latch-type MOSFET are constituted by N-channel MOSFETs. Further, the timing adjustment unit 8 is configured by a two-stage inverter circuit unlike the above-described embodiment, and the gate of the P-channel MOSFET for flowing an operating current to the differential MOSFET of the pulsing circuit 6 and the gate of the N-channel MOSFET for performing pull-down, The same internal negative clock is supplied. In the pulse circuit 6 of this embodiment, a large level margin is provided on the high level side, contrary to the previous embodiment.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the RS flip-flop circuit 7 constituting the slave flip-flop circuit 3 may be an RS flip-flop circuit using a NAND circuit as described above. The master flip-flop circuit 2 may be any circuit that forms the input signal MB by taking advantage of the characteristics shown in FIG. 6 of the pulse circuit 6 as described above. The present invention can be widely used in semiconductor devices including a synchronization circuit that captures an input signal in synchronization with a clock.

1 is a block diagram showing an embodiment of a master-slave flip-flop circuit according to the present invention. FIG. 1 is a circuit diagram showing one embodiment of a master-slave flip-flop circuit according to the present invention. FIG. It is a circuit diagram which shows another Example of the master slave flip-flop circuit based on this invention. It is a circuit diagram which shows another Example of the master slave flip-flop circuit based on this invention. It is a characteristic view for demonstrating operation | movement of the pulsing circuit used for this invention. It is a characteristic view for demonstrating operation | movement of the master slave flip-flop circuit based on this invention. It is a circuit diagram which shows another Example of the master slave flip-flop circuit based on this invention. It is a circuit diagram which shows an example of a prior art. FIG. 9 is a simulation characteristic diagram of the circuit of FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Master-slave flip-flop circuit, 2 ... Master flip-flop circuit, 3 ... Slave flip-flop circuit, 4 ... D-flip flop circuit, 6 ... Pulse circuit, 7 ... RS-flip flop circuit, 8 ... Clock timing adjustment part , A to z, a ′... MOSFET, N1 to N5.

Claims (6)

A synchronization circuit that receives a clock and an asynchronous signal; and
An RS-flip-flop circuit that receives the first and second complementary signals formed by the synchronization circuit;
The synchronization circuit is
First and second MOSFETs of a first conductivity type;
A third MOSFET of a first conductivity type, provided between a commonly connected source of the first and second MOSFETs and a first potential;
A second conductivity type fourth and fifth MOSFET provided between a second potential different from the first potential and the drains of the first and second MOSFETs;
The fourth and fifth MOSFETs and the sixth and seventh MOSFETs of the second conductivity type in which the source-drain paths are arranged in parallel, and the gates and drains are cross-connected,
An input signal is supplied to the gate of the first MOSFET,
The gate of the second MOSFET is connected to the drain of the first MOSFET;
An internal clock corresponding to the clock is supplied to the gate of the third MOSFET,
An internal clock in phase with the internal clock is supplied to the gates of the fourth and fifth MOSFETs,
A semiconductor device, wherein the first signal is output from a drain of the first MOSFET, and the second signal is output from a drain of the second MOSFET. In claim 1,
The RS flip-flop circuit is
The second conductivity type eighth and ninth MOSFETs, wherein the first signal is supplied to the gate and the second potential is applied to the source;
A second conductivity type tenth and eleventh MOSFET in which the second signal is supplied to the gate and the second potential is applied to the source;
A first conductivity type twelfth MOSFET provided between the drain of the ninth MOSFET and a first potential, the first signal being supplied to the gate;
A first conductivity type thirteenth MOSFET provided between the drain of the eleventh MOSFET and a first potential, the second signal being supplied to the gate;
Drain outputs of the eleventh and thirteenth MOSFETs are supplied to the gates, and a fourteenth MOSFET of the first conductivity type provided between the drain of the eighth MOSFET and the first potential;
A drain output of the ninth MOSFET and the eleventh MOSFET is supplied to the gate, and a fifteenth conductivity type fifteen MOSFET provided between the drain of the tenth MOSFET and the first potential;
A latch circuit composed of a pair of CMOS inverter circuits whose inputs and outputs are cross-connected,
The drain output of the eighth MOSFET and the fourteenth MOSFET and the drain output of the tenth MOSFET and the fifteen MOSFET are connected to the pair of cross-connected input / output nodes of the latch circuit. In claim 1,
The semiconductor device characterized in that the internal clock supplied to the gates of the fourth and fifth MOSFETs is faster than the internal clock supplied to the gate of the third MOSFET or can be changed at the same time. In claim 3,
Switch means for transmitting an input signal to the input of the CMOS inverter circuit corresponding to the first timing signal, and an inverting feedback circuit for feeding back the output signal of the CMOS inverter circuit to the input of the CMOS inverter circuit corresponding to the second timing signal A through latch circuit comprising: and the first and second timing adjustment units,
The through latch circuit is a master flip-flop circuit,
The output signal of the master flip-flop circuit is the input signal of the synchronization circuit, the synchronization circuit and the RS-flip-flop circuit are slave flip-flop circuits,
The semiconductor device according to claim 1, wherein the timing adjustment unit receives the clock and generates the first and second timing signals and the internal clock supplied to the master flip-flop circuit. In claim 4,
2. The semiconductor device according to claim 1, wherein the CMOS inverter circuit is set to a logical threshold voltage in a direction in which the delay characteristic dependency of input characteristics in the synchronization circuit is reduced. In claim 5,
The semiconductor device characterized in that the internal clock supplied to the gates of the fourth and fifth MOSFETs is faster than the internal clock supplied to the gate of the third MOSFET or can be changed at the same time.

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