JP2006287006A - Semiconductor substrate, semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device controlled in crystallinity and strain and having low costs, high withstand voltage, and low channel conductance by reducing the thickness of an SiGe layer from which a strain Si layer is obtained, the strain Si layer being formed taking a strain relaxation SiGe layer formed on an Si substrate as a virtual substrate. <P>SOLUTION: The semiconductor substrate includes a first semiconductor laminate structure where an SiGe layer and an Si layer are laminated on the entire surface of a principal surface of a first conductivity type Si substrate or an SOI or on a part of the same, and has dislocation on an interface between the Si substrate and the SiGe layer. A start point of the dislocation line and the end point of the same are existent on the side surface of the substrate, and the start point and the end point are substantially not existent on a principal surface of strain Si, so that the SiGe layer is subjected partly or completely to strain relaxation. The strain Si layer of tension strain is formed on the SiGe layer. Further, a principal surface of the substrate that does not contain the first semiconductor laminated structure can include an compression strain Si region. Furthermore, at least two kinds of field effect transistors can be formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate and a semiconductor device using the semiconductor substrate, in particular, a field effect transistor device and a manufacturing method thereof.

  High speed and low power consumption for large-scale integrated circuits (LSIs) used in digital home appliance microcomputers and personal computers, and analog high-frequency electronic components used in mobile communication terminals (for example, transmission amplifiers and reception integrated circuits) There is a need for more power and functionality. Electronic devices that make up circuits, such as silicon (Si) field effect transistors (FETs), have so far been made more efficient by using lithography technology, mainly by shortening the gate length. Improvement in driving force and reduction in power consumption) have been realized.

  However, in a miniaturization technique with a minimum processing dimension of 100 nm or less, the drift velocity of carriers in the channel is saturated due to a short channel effect in a MOS (Metal-Oxide-Semiconductor) transistor. That is, with the miniaturization, there has been a problem that the on-current of the transistor becomes small. In addition, since the breakdown voltage of the transistor is lowered, a problem arises when applied to an analog circuit. Further, with respect to the miniaturization technique, there has been a problem that equipment and manufacturing costs increase.

  Therefore, it is expected to improve the performance of the electronic devices by developing materials without relying only on miniaturization technology. Among them, strained Si, which can improve the mobility of materials while taking advantage of the advantages of Si materials, has attracted attention. Strained Si changes its electronic state due to a decrease in symmetry of the Si crystal, and the mobility of electrons increases when in-plane tension is applied to the Si crystal, and the mobility of holes increases when compressive stress is applied in the plane. Have

  As a method for imparting strain to Si, for example, (1) “method by local strain” to be introduced into the device manufacturing process, and (2) a virtual substrate (a substrate in which a strain relaxation SiGe layer or the like is formed on a Si substrate) is used. A method using global distortion is known.

  Examples of the method using local strain include the paper Tech. Dig. Int. Electron Devices Meet. 2003, P11.6.1. (Non-patent Document 1). In this method, Si in the PMOS source and drain regions is etched to form a recess, and SiGe is epitaxially grown so as to fill the recess. As a result, a uniaxial compressive strain is applied to the channel region sandwiched between the source and drain, and the hole mobility in the channel increases by 50% or more. In the case of NMOS, a SiN cap layer is formed on the gate upper layer to transmit tensile strain to the channel region. As a result, the saturation drain current increases by 10%.

  The concept of the global strain method is to use a virtual substrate on which a thin film material having a different lattice constant from that of the substrate is epitaxially grown on a Si substrate. The Si film is distorted by epitaxially growing Si on the virtual substrate surface. If the lattice constant of the virtual substrate is larger than the lattice constant of Si, a tensile strained Si film is formed. If the lattice constant of the virtual substrate is smaller than the lattice constant of Si, a compressive strained Si film is formed.

Many methods are known as a technique for forming a virtual substrate. As a representative example, a virtual substrate is known in which a strained SiGe (Si _1-x Ge _x ) mixed crystal layer is grown on a Si substrate. The desirable form is that the SiGe layer is completely strain-relaxed and crystal defects (such as threading dislocations) do not exist on the surface.

When SiGe is grown on the Si substrate, in the initial stage, it is lattice-matched with Si. Therefore, compressive strain is included in the SiGe film. When the film thickness is increased and the critical film thickness _hc is exceeded, misfit dislocations are formed at the SiGe / Si substrate interface to release the internal strain of SiGe. However, at this stage, SiGe stays in partial lattice relaxation only near the dislocation lines. Therefore, increasing the thickness of the SiGe, to form a SiGe layer with a thickness of more than 4h _c, proliferation of misfit dislocations occurs. As a result, the SiGe layer is sufficiently relaxed. For example, according to R. Beanland's paper “ultiplication of misfit dislocations in epitaxial layers” AJ. Appl. Phys., 72 (1992) 4031, the proliferation of dislocations at this time is due to the Frank-Read mechanism (Non-patent Document 4). . This dislocation growth mechanism is due to the fact that misfit dislocation lines formed at the SiGe / Si substrate interface decompose through threading dislocations that have escaped to the thin film surface. That is, when the tension acting on threading dislocation exceeds a certain film thickness value, the film slips and moves so as to draw an arc in the thin film cross section. And when this arc reaches the surface, the dislocation line is cut. As a result, dislocation lines proliferate. In other words, this mechanism uses threading dislocations, and the tension acting on threading dislocation lines accompanying the increase in film thickness is the driving force for dislocation growth.

On the other hand, as seen in, for example, a paper by W. Hagen et al., 鄭 New Type of Source Generating Misfit Dislocations 煤 AAppl. Phys., 17 (1978) 85, Hagen-Strunk as a transposition growth mechanism other than Frank-Read mechanism. There is a mechanism (Non-Patent Document 5). This means that when two misfit dislocation lines that have the same Burgers vector and are perpendicular to each other in the interface intersect, one dislocation line breaks and grows. According to the energy calculation by Y. Obayashi et al., “Is the Hagen-Strunk multiplication mechanism of misfit dislocations in heteroepitaxial layers probable?” Phil. Mag. Lett., 76 (1997) 1, dislocation multiplication by Hagen-Strunk mechanism. In order to achieve this, the translocation growth critical film thickness h _hs or less must be maintained (Non-patent Document 6). However, in the case of the SiGe / Si system, the critical film thickness h _c at which misfit dislocations are formed is larger than h _hs , and it is considered that dislocation growth by the Hagen-Strunk mechanism does not occur.

  Now, threading dislocations cause crystal defects on the surface of the virtual substrate, which adversely affects the crystallinity of strained Si. However, dislocation growth using threading dislocations is necessary for strain relaxation of SiGe as described above. For this reason, in the virtual substrate formation technology, it is necessary to achieve both strain relaxation of the SiGe layer and reduction of threading dislocations. A method of growing strain relaxed SiGe with few threading dislocations on a Si substrate is disclosed in US Pat. No. 5,221,413 (Patent Document 1) or Appl. Phys. Lett, 59 (1991) 811 (Non-Patent Document 2). It is disclosed. According to Patent Document 1, SiGe is grown on a Si substrate at a growth temperature exceeding 850 degrees Celsius under a condition where the Ge composition is increased to a target composition in an inclined manner (increase rate of about 25% or less per micron). When the buffer layer is formed, a strain-relieved SiGe layer with few threading dislocations is formed.

  Other than the method using the Ge composition gradient buffer layer, a method of relaxing the SiGe layer without using dislocation growth is disclosed. For example, Appl. Phys. Lett., 76 (2000) 3552 (Non-Patent Document 3) describes that when a SiGe layer is formed on a Si substrate, hydrogen ion implantation is performed, and then annealing is performed at 800 degrees Celsius. Small cracks and dislocation loops are formed in the vicinity of the / Si substrate interface, resulting in strain relaxation of SiGe. Japanese Patent Laid-Open No. 2003-273017 (Patent Document 2) uses Si molecules to efficiently relax the strain of SiGe.

  According to Japanese Patent Laid-Open No. 2003-282463 (Patent Document 3), the Si substrate surface is converted to porous by an anodic oxidation method, and then the pores are oxidized to give tensile stress to the Si lattice. In addition, it is disclosed that when SiGe is deposited, the strain of SiGe is relaxed.

  In Japanese Patent Laid-Open No. 2003-23160 (Patent Document 4), when an island-shaped SiGe formed on an insulating layer using a SOI (Silicon on Insulator) substrate is thermally oxidized, the Ge concentration increases, and the end of the SiGe layer is changed. As a starting point, a method is disclosed in which slip occurs at the interface between the SiGe layer and the base insulating layer, and as a result, the strain of SiGe is relaxed.

US Patent USP52221413 (1993.6.22) JP 2003-273017 A JP 2003-282463 A JP2003-23160 T. Ghani, et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, Tech. Dig. Int. Electron Devices Meet. 2003, P11.6.1. E .. A. Fitzgerald et al., “Totally relaxed GexSi1-x layers with low threading dislocation yields grown on Si substrates”, Appl. Phys. Lett, 59 (1991) 811. H. Trinkaus et al. “Strain relaxation mechanism for hydrogen-implanted Si1-xGex / Si (100) heterostructures”, Appl. Phys. Lett., 76 (2000) 3552. R. Beanland, “Multiplication of misfit dislocations in epitaxial layers”, J. Appl. Phys., 72 (1992) 4031 W. Hagen and H. Strunk, “A New Type of Source Generating Misfit Dislocations”, Appl. Phys., 17 (1978) 85 Y. Obayashi and K. Shintani, "Is the Hagen-Strunk multiplication mechanism of misfit dislocations in heteroepitaxial layers probable?", Phil. Mag. Lett., 76 (1997) 1

  The prior art aimed at improving carrier mobility by applying tensile and compressive strain to Si has the following difficulties.

  In the method using local strain, a SiN cap film is formed on the upper portion of the MOSFET gate to transmit tensile stress to the channel portion. For this reason, it is difficult to give a large strain to the Si film, and in the NMOS, the current improvement is only 10%. That is, the tensile strain required for the NMOS is not sufficient, and the quantitative control of the strain is not sufficient.

  The method using global strain can give a sufficient amount of strain to the Si film through the virtual substrate surface, but the strain is uniform over the entire surface of the Si film. Therefore, when tensile strain is applied to the Si film, the performance of the NMOS is improved, but the performance of the PMOS is lowered, and vice versa. That is, it is difficult to improve the performance of CMOS (Complementary Metal-Oxide-Semiconductor) because the performance of both NMOS and PMOS cannot be improved.

  In the method using the Ge composition graded buffer layer, since the SiGe layer is as thick as several microns, it is extremely difficult to pattern the SiGe layer and partially give strain. Therefore, this method is limited to depositing SiGe on the entire surface of the substrate.

  In the method using the Ge composition gradient buffer layer, the material cost such as the source gas and the utility cost increase, so that there is a problem that the unit price of the substrate increases. For example, in a tilted SiGe buffer layer, a SiGe layer having a thickness of several microns must be formed, and therefore, film formation using a normal CVD method requires several hours.

In the method using the Ge composition gradient buffer layer, crystal defects such as misfit dislocations and dislocation loops must be introduced in order to relax the strain of the SiGe layer. Dislocation lines must form loops within the crystal or otherwise penetrate through the side of the wafer film or through the surface as threading dislocations. For this reason, crystal defects also accompany the SiGe film surface. Typically, the threading dislocation density is 10 ³ -10 ⁶ cm ^-2 .

  In the method using the Ge composition gradient buffer layer, since SiGe has lower thermal conductivity than Si, there is a problem that heat dissipation is reduced by the thick SiGe layer and the temperature of the device is increased.

  That is, the fundamental cause of the problem of the method using the Ge composition gradient buffer layer is that the film thickness of the strain relaxation SiGe layer becomes as thick as several microns.

  Other methods also require anodization and ion implantation processes, which complicates the virtual substrate manufacturing process and increases manufacturing costs.

In addition, the method without using SiGe makes it difficult to quantitatively control the amount of strain. Therefore, the object of the present invention is to use the advantages of SiGe to compensate for the disadvantages, that is, the film thickness of SiGe. Is to reduce the threading dislocation, and to suppress threading dislocations. As an effect, the present invention provides strained Si excellent in crystallinity that can be manufactured at a low cost and whose strain direction and magnitude are quantitatively controlled. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the gist of representative ones will be described as follows. The basic structure of the strained Si laminated structure of the semiconductor substrate of the present invention is that the first semiconductor in which the SiGe layer and the Si layer are sequentially laminated on the whole or part of the main surface of the first conductivity type Si substrate or SOI substrate. It has a laminated structure. The interface between the SiGe layer having the first semiconductor stacked structure and the substrate contains a large amount of dislocations. The start point and end point of the dislocation line exist on the side surface of the substrate, and the start point or end point of the dislocation line hardly exists on the main surface of the strained Si. For this reason, the SiGe layer is partially or completely strain relaxed. More preferably, the thickness of the SiGe layer is about 100 nm or less. Below this film thickness, a sufficient strain relaxation SiGe layer can be realized. The present invention is remarkably thinner than the prior art, and the strain of the strained Si is tensile in the plane.

  A part of the region not including the first semiconductor multilayer structure may have a second semiconductor multilayer structure including a Si region sandwiched between SiGe on the substrate surface. This Si region is subjected to compressive strain in the plane.

  Further, the SiGe layer formed on the substrate can be composed of a plurality of layers. In this case, the interface between the first SiGe layer and the substrate and the interface between the nth SiGe layer and the (n−1) th SiGe layer contain dislocations, and the first SiGe layer and the first The n SiGe layer is partially or completely strain relaxed, and the Si layer is a first strained Si layer having tensile strain in the plane. This form is extremely useful when obtaining a strain-relaxed SiGe layer having a Ge concentration of 20% or more, as will be described later. The number n of the plurality of SiGe layers is practically about 10 or less.

  The first field effect semiconductor device according to the present invention has a gate electrode on the main surface of the first semiconductor multilayer structure with a gate insulating film interposed therebetween, and serves as a channel formation region under the gate electrode. An insulated gate field effect transistor is configured to sandwich the Si layer. In this case, typically, a source region and a drain region of the second conductivity type are formed in the strained Si layer and the SiGe layer.

  The second field-effect semiconductor device of the present invention has a gate electrode on the main surface of the second semiconductor multilayer structure with a gate insulating film interposed therebetween, and serves as a channel formation region under the gate electrode. An insulated gate field effect transistor is configured to sandwich the Si layer. In this case, typically, a source region and a drain region of the second conductivity type are formed in the strained Si layer and the SiGe layer.

  In the field effect semiconductor device, generally, the source region and drain region of the first field effect semiconductor device are N-type, and the source region and drain region of the second field effect semiconductor device are P-type. The

  Further, the first field effect semiconductor device and the second field effect semiconductor device are adjacent to each other, and a CMOS can be freely configured.

  A typical example of manufacturing the semiconductor substrate of the present invention includes the following steps. That is, a step of depositing a SiGe layer having a critical film thickness or more on a Si substrate or SOI substrate on the entire surface or a part of the substrate, the film thickness of which is 10 nm. A step of reducing the film thickness to a degree below, a step of performing a heat treatment to partially or completely relieve strain of the SiGe layer, and a step of forming a Si layer on the SiGe layer. Here, it is important to make the thickness of the SiGe layer thin enough to cause dislocation growth by the Hagen-Strank mechanism. This thickness depends on the Ge content of the SiGe layer, but is generally 10 nm or less, preferably 5 nm or less.

  According to the first aspect of the present invention, a semiconductor substrate having an Si film having excellent crystallinity and controlled strain can be obtained. In addition, a method for manufacturing such a semiconductor substrate is provided.

  According to the second aspect of the present invention, the performance of an electronic device such as a field effect transistor can be improved.

Prior to describing specific embodiments, the background of the inventor's inventing the above-described means will be described. The inventor can solve the above-mentioned problems in the SiGe virtual substrate if a technology is realized in which the strain relaxation SiGe layer is made much thinner than the conventional thickness of several microns and threading dislocations are not formed. Thought. For this purpose, we have been conducting experimental research on SiGe film formation and crystal defect evaluation, considering how to grow misfit dislocations necessary for strain relaxation. In the study process, forming a SiGe film exceeds the critical film thickness h _c indicated by 10 in FIG. 2 on the Si substrate, then, after that thin SiGe film, when heated at about 900 degrees Celsius, SiGe It was discovered that misfit dislocations formed in the film and Si substrate proliferate. FIG. 2 is a graph showing the relationship between the Ge concentration in the SiGe film and the critical film thickness of the SiGe film in which misfit dislocations are formed when the SiGe film is formed on the Si substrate. The horizontal axis represents the Ge concentration (number of atoms) in the SiGe film, and the vertical axis represents the critical film thickness (nm). Curve 10 is the critical film thickness.

FIG. 3 is a planar TEM image of the SiGe film formed on the Si substrate. In the example of FIG. 3, the film thickness of SiGe is above the critical thickness h _c, lattice form misfit dislocations (e.g. 11) have been observed.

Next, this sample was thermally oxidized, the oxide film was removed, and heat treatment was performed. Then, as shown in FIG. 4, proliferation of misfit dislocations (for example, 12) is observed. FIG. 4 is a planar TEM image of the SiGe film after the heat treatment. Furthermore, when threading dislocations were evaluated by the etch pit method, it was also found that the threading dislocation density of the SiGe film was extremely small, 10 ³ / cm ² or less, despite misfit dislocations growing. This dislocation growth occurs at the SiGe / Si interface and is due to the Hagen-Strunk mechanism, which has not been observed in the past, or a similar mechanism. Here, the example of FIG. 4 is an early stage of dislocation growth, and the photograph of dislocation growth when the strain is actually completely relaxed covers the entire surface with dislocation lines.

  Therefore, dislocation growth at the SiGe / Si interface occurred by this means, and as a result, the SiGe layer was relaxed. The film thickness of this strain relaxation SiGe layer is 100 nm or less. In the present invention, since the Si layer is grown on the SiGe layer to form the strained Si layer, the SiGe layer receives stress from the upper Si layer. It is not preferable that the SiGe layer is distorted by the Si layer. Therefore, the SiGe layer needs a certain thickness. Although depending on the thickness of the Si layer formed on the upper part, the thickness of the SiGe layer is preferably in the range of 100 nm to 20 nm.

  Further, it was found that when the Ge concentration of the SiGe film is less than 20%, misfit dislocations formed in the initial stage are 60 ° dislocations. In this case, misfit dislocations are easy to move, and most of the dislocation lines pass to the side of the wafer. Therefore, there are almost no threading dislocations where dislocation lines pass through the wafer surface. It was also discovered that dislocation lines tend to be confined at the SiGe / Si interface without penetrating the substrate surface even in the process of dislocation growth by thinning and heat treatment.

  When the Ge concentration of the SiGe film is 20% or more, misfit dislocations tend to exist in a mixture of 90 degree dislocations and 60 degree dislocations. Since the 90-degree dislocation restricts the movement of the dislocation, the dislocation line becomes a relatively short line segment, and both ends of the dislocation line pass through to the surface to form threading dislocations. Therefore, when a SiGe layer having a Ge concentration of 20% or more is directly formed on a Si substrate, a strain relaxation layer having poor crystallinity (a lot of threading dislocations) is formed. Therefore, when it is desired to form a SiGe layer having a Ge concentration of 20% or more, first, the first strain relaxation SiGe layer is formed by the above method at a Ge concentration of less than 0.2, and the Ge concentration is the Ge of the first layer. A second strain relaxation SiGe layer is formed by depositing SiGe having a concentration twice or less and repeating the above method. What is necessary is just to form the 3rd, 4th strain relaxation SiGe layer according to required Ge density | concentration.

  Although the strain relaxation SiGe layer of the thin film can be formed by the above method, when SiGe is thinner than 50 nm, SiGe is distorted by the stress of the Si film when Si is deposited on SiGe. Therefore, after forming the strain relaxation SiGe layer, it is necessary to continuously form a SiGe buffer layer having the same Ge concentration as the strain relaxation SiGe layer. The required film thickness of the SiGe buffer layer depends on the film thickness of the Si layer, but may be about 100 nm. Here, the thickness of the strained Si layer depends on the requirements of the device formed here. In general, the range from 20 nm to 100 nm is frequently used and practical.

  Further, since the SiGe layer can be thinned, SiGe can be patterned by photolithography, and Si can be formed thereon and flattened so that tensile strained Si regions can be formed separately. Furthermore, after forming recesses on both sides of the unstrained Si region and growing it so as to embed SiGe, if the surface is oxidized, the Ge concentration of SiGe increases, so that the volume expands and Si sandwiched between SiGe Is distorted by compressibility. Accordingly, unstrained, tensile, and compressive strained Si can be separately produced on the same substrate surface.

<Example 1>
In this embodiment, a strained Si substrate having a strain relaxation SiGe layer using a low temperature thermal oxidation method and a method for manufacturing the same are illustrated using FIGS. 5A to 5F and FIGS. 8A to 8B. The film thickness of the strain relaxation SiGe layer is an example of about 100 nm.

After the Si substrate or SOI (Silicon on Insulator) substrate 20 is chemically cleaned (FIG. 5A), it is introduced into a low pressure chemical vapor deposition (LPCVD) apparatus to grow a first SiGe layer 22 on the substrate 20 (FIG. 5B). . The source gas is SiH ₄ and GeH ₄ diluted with H ₂ gas, and the growth temperature is 650 degrees Celsius. The Ge concentration was 15%. If the Ge concentration is less than 20%, the threading dislocations are few and the crystallinity is good. At this time, the film thickness of the first SiGe layer 22 must have a Ge concentration larger than the critical film thickness hc shown in FIG. Here, a 30 nm film was formed. At this stage, misfit dislocations 21 are formed at the interface between the first SiGe layer and the Si substrate 20. However, since the misfit dislocation density is not sufficient to release the strain of SiGe, compressive strain is included in the SiGe layer 22.

Next, the SiGe-formed substrate is introduced into an oxidation furnace, and SiGe is thermally oxidized at a relatively low temperature (for example, 750 degrees Celsius) to form a SiO ₂ layer and a GeO ₂ layer 23 (FIG. 5C). . The unoxidized SiGe layer was oxidized until the film thickness reached 5 nm. Here, the film thickness of the SiGe layer 22 was measured using spectroscopic ellipsometry. Next, the SiO ₂ layer 23 is etched with a 5% HF aqueous solution. Here, since GeO ₂ is water-soluble, it is etched together with SiO ₂ . The etched substrate is introduced into an electric furnace and heated in a nitrogen atmosphere at 900 degrees Celsius for 30 minutes. At this time, misfit dislocations 21 grow at the SiGe / Si substrate interface, and the SiGe layer 24 relaxes the strain (FIG. 5D).

After the substrate thus prepared is chemically cleaned, it is again introduced into the LPCVD apparatus to grow the SiGe buffer layer 24a. The source gas is SiH ₄ and GeH ₄ diluted with H ₂ gas, and the growth temperature is 650 degrees. The Ge concentration was the same as that of the first SiGe layer, 15%, and the film thickness was 95 nm. The film thickness of the SiGe layer 24a at this stage is 100 nm (FIG. 5E). In FIG. 5E, since the strain relaxation SiGe layer 24 and the buffer layer 24a are integrated, they are illustrated as the SiGe layer 24a.

  The heat treatment for strain relaxation has an influence of Ge diffusion if the temperature is too high, and is about 800 to 1000 degrees Celsius below the device process maximum temperature.

  Subsequently, the GeH 4 gas is stopped and a first Si layer 25 having a thickness of 20 nm is grown (FIG. 5F).

  Here, there are two reasons for growing the SiGe buffer layer 24a. First, when an electronic device such as a field effect transistor is formed in a strained Si layer, if a large number of misfit dislocations formed at the interface between the first SiGe and the Si substrate are present at the PN junction interface, leakage current may be generated. Because it becomes. Therefore, it is necessary to separate the misfit dislocation position from the strained Si layer 25. Another reason is that the thickness of the strain-relieved first SiGe layer 21 is as thin as 5 nm. For this reason, when the Si layer 25 having a thickness of 20 nm is grown on the SiGe layer 21, the SiGe layer 21 loses the stress from the Si layer 25, and the SiGe layer 21 undergoes compressive strain again without being distorted. End up. SiGe strain relaxation and strain amount of strained Si can be confirmed using Raman spectroscopy or X-ray diffraction. Here, strain relaxation was confirmed using micro-Raman spectroscopy using an argon ion laser with a beam diameter of 1 μmφ as probe light. The film thicknesses of the strained Si layer 25 and the SiGe layer 24a (the first Si layer and the SiGe buffer layer are integrated) can be evaluated using spectroscopic ellipsometry. Moreover, when cross-sectional observation using transmission electron microscopy is used, it can be confirmed that a large amount of misfit dislocations are formed at the interface between the SiGe layer 24a and the Si substrate 20.

The crystallinity of the SiGe layer and strained Si formed in this example is extremely high. The verification can be confirmed by evaluating the epipit density by a seco etching method using a differential interference microscope. In this example, the crystallinity was so excellent that the threading dislocations in the strained Si layer and the SiGe layer could not be confirmed. In this example, the threading dislocation density was 10 ³ cm ⁻² in the worst case. The cause of threading dislocations depends on the cleanliness of the growth apparatus and the substrate cleaning environment.

  As described above, the Ge concentration is desirably less than 20% in order to form a strain-relaxed SiGe layer having excellent crystallinity. However, when it is desired to produce a strain relaxation SiGe layer having a Ge concentration of 20% or more, there are methods shown in FIGS. 8A and 8B. First, the first strain relaxation SiGe layer 30a is formed on the Si substrate or SOI (Silicon on Insulator) substrate 20 at a Ge concentration of less than 20% by the method described above, and then on the first strain relaxation SiGe layer 30a. Then, a second strain relaxation SiGe layer 30b having a Ge concentration of not more than twice the Ge concentration of the first strain relaxation SiGe layer is formed. Then, as described above, the second strain relaxation SiGe layer 30b is formed by repeating the above-described methods of oxidation, etching, and heating. A large amount of misfit dislocations 21b is formed at the interface between the second strain relaxation SiGe layer 30b and the first strain relaxation SiGe layer 30a. Subsequently, as described above, the first Si layer 25 having a thickness of 20 nm is grown on the second strain relaxation SiGe layer 30b (FIG. 8A).

  Further, the third strain relaxation SiGe layer 30c and the like may be repeatedly formed according to the required Ge concentration. Here, a buffer layer is formed on the uppermost strain relaxation SiGe layer. Subsequently, as described above, the first Si layer 25 having a thickness of 20 nm is grown on the third strain relaxation SiGe layer 30c and the like (FIG. 8B).

<Example 2>
In this embodiment, a strained Si substrate having a strain relaxation SiGe layer with a film thickness of about 100 nm by a high temperature thermal oxidation method and a method for manufacturing the same are illustrated using FIGS. 6A to 6F and FIGS. 8A to 8B.

After the Si substrate or SOI substrate is chemically cleaned (FIG. 6A), it is introduced into a low pressure chemical vapor deposition (LPCVD) apparatus to grow the first SiGe layer 32 (FIG. 6B). The source gas is SiH ₄ and GeH ₄ diluted with H ₂ gas, and the growth temperature is 650 degrees Celsius. As will be described later, the final first SiGe layer 35 has a Ge concentration of 15% and a film thickness of 5 nm. Here, if the final Ge concentration of the SiGe layer 35 is less than 20%, the threading dislocations in the SiGe film are extremely reduced and the crystallinity is excellent. The final film thickness of the first SiGe layer 35 must be larger than the critical film thickness hc shown in FIG. 2 for the final Ge concentration. In order to obtain the final Ge concentration and film thickness of the first SiGe layer 35, the SiGe film to be formed, that is, the initial Ge concentration of the first SiGe layer 32 was 3%, and the film thickness was 25 nm. Next, when SiGe 32 is thermally oxidized at 850 degrees Celsius, a SiO ₂ layer 33 is formed on the surface (FIG. 6C), and Ge diffuses into the SiGe layer 34. If the temperature is further raised, care must be taken because Ge diffuses to the substrate 20 side. The thermal oxidation method may be performed by an RTA (Rapid Thermal Annealing) apparatus or a flash lamp apparatus in addition to the case of performing the thermal oxidation in a thermal oxidation furnace. That is, as the thickness of the SiO ₂ layer increases, the concentration of Ge in the SiGe layer 32 increases. Thermal oxidation was stopped when the thickness of the SiGe layer 34 reached 5 nm. At this stage, the Ge concentration of the SiGe layer 34 is about 15%. Here, the film thickness of the SiGe layer 34 was measured using spectroscopic ellipsometry, and the Ge concentration was measured by Raman spectroscopy.

Next, the SiO ₂ film 33 is etched with a 5% HF aqueous solution. Thereafter, the substrate on which the first SiGe film 32 is formed is introduced into an electric furnace and heated at 900 degrees Celsius for 30 minutes in a nitrogen gas atmosphere. At this time, misfit dislocations 21 grow at the interface between the SiGe film 35 and the Si substrate 20, and the SiGe layer 35 relaxes strain (FIG. 6D). Next, after chemically cleaning the substrate, it is again introduced into the LPCVD apparatus to grow a SiGe buffer layer. The source gas is SiH ₄ and GeH ₄ diluted with H ₂ gas, and the growth temperature is 650 degrees Celsius. The Ge concentration was the same as that of the first SiGe layer 35, 15%, and the film thickness was 95 nm. At this stage, the thickness of the strain relaxation SiGe layer 35a is 100 nm. Subsequently, the GeH ₄ gas is stopped and a first Si layer 36 having a thickness of 20 nm is grown.

SiGe strain relaxation and strain amount of strained Si can be confirmed using Raman spectroscopy or X-ray diffraction. Here, strain relaxation was confirmed using micro-Raman spectroscopy using an argon ion laser with a beam diameter of 1 μmφ as probe light. The film thicknesses of the strained Si layer 36 and the SiGe layer 35a (as in the previous example, the first SiGe layer 32 and the SiGe buffer layer are integrated) can be evaluated using spectroscopic ellipsometry. When cross-sectional observation using transmission electron microscopy is used, it can be confirmed that a large amount of misfit dislocations are formed at the interface between the SiGe layer 35a and the substrate 20. In this example, the crystallinity was so excellent that the threading dislocations in the strained Si layer 36 and the SiGe layer 35a could not be confirmed. In the worst case in this example, the threading dislocation density was 10 ³ cm ⁻² . The cause of threading dislocations depends on the cleanliness of the growth apparatus and the substrate cleaning environment.

  As described above, in order to form the strain relaxation SiGe layer 35a having excellent crystallinity, the Ge concentration is desirably less than 20%. However, a case where a strain relaxation SiGe layer having a Ge concentration of 20% or more is to be manufactured will be described with reference to FIGS. 8A and 8B. First, on the Si substrate or SOI (Silicon on Insulator) substrate 20, the first strain relaxation SiGe layer 30a is formed by the above method with a Ge concentration of less than 20%. Next, on the first strain relaxation SiGe layer 30a, a second strain relaxation SiGe layer 30b having a Ge concentration equal to or less than twice the Ge concentration of the first strain relaxation SiGe layer is formed. Then, as described above, the second strain relaxation SiGe layer is formed by repeating the above-described methods of oxidation, etching, and heating. A large amount of misfit dislocations 21b is formed at the interface between the second strain relaxation SiGe layer and the first strain relaxation SiGe layer. Subsequently, as described above, the first Si layer 25 having a thickness of 20 nm is grown on the second strain relaxation SiGe layer 30b and the like (FIG. 8A).

  Further, the third strain relaxation SiGe layer 30c and the like may be repeatedly formed according to the required Ge concentration. Here, a buffer layer is formed on the uppermost strain relaxation SiGe layer. Subsequently, as described above, the first Si layer 25 having a thickness of 20 nm is grown on the third strain relaxation SiGe layer 30c (FIG. 8B).

  Since the present embodiment performs thermal oxidation at a higher temperature than the first embodiment, the oxidation time can be shortened. However, since Ge is diffused also to the substrate side by oxidation, it is necessary to control the Ge concentration more strictly.

<Example 3>
In this embodiment, a strained Si substrate having a strain relaxation SiGe layer with a thickness of about 100 nm and a manufacturing method thereof are illustrated by using dry etching with reference to FIGS. 7A to 7F and FIGS. 8A to 8B.

After the Si substrate or SOI substrate 20 is chemically cleaned (FIG. 7A), it is introduced into a low pressure chemical vapor deposition (LPCVD) apparatus to grow the first SiGe layer 22 (FIG. 7B). The source gas is SiH ₄ and GeH ₄ diluted with H ₂ gas, and the growth temperature is 650 degrees Celsius. The Ge concentration was 15%. If the Ge concentration is less than 20%, the threading dislocations are few and the crystallinity is good. The film thickness of the first SiGe layer 22 must be larger than the critical film thickness hc as shown in FIG. Here, a 30 nm film was formed. At this stage, misfit dislocations 21 are formed at the interface between the first SiGe layer 22 and the substrate 20. However, since the misfit dislocation density is not sufficient to release the strain of the SiGe layer 22, compressive strain is included in the SiGe layer 22.

Next, the substrate is introduced into a dry etching apparatus, and is etched using CF ₄ gas so that the film thickness of the first SiGe layer 22 becomes 5 nm, thereby obtaining a state indicated by reference numeral 22b (FIG. 7C). Here, the film thickness of the SiGe layer 22b was measured using spectroscopic ellipsometry, and the etching conditions were calibrated. Thereafter, the substrate is taken out from the dry etching apparatus and subjected to chemical cleaning, and then the substrate is introduced into an electric furnace and heated in a nitrogen gas atmosphere at 900 degrees Celsius for 30 minutes. At this time, misfit dislocations propagate at the interface between the SiGe layer 22c and the substrate 20, and the SiGe layer 22c relaxes strain.

Next, after chemically cleaning the substrate, the substrate is again introduced into the LPCVD apparatus to grow a SiGe buffer layer (FIG. 7E). The source gas is SiH ₄ and GeH ₄ diluted with H ₂ gas, and the growth temperature is 650 degrees Celsius. The Ge concentration was the same as that of the first SiGe layer 22, 15%, and the film thickness was 95 nm. At this time, the film thickness of the SiGe layer 22d is 100 nm. Subsequently, the GeH ₄ gas is stopped and a first strained Si layer having a thickness of 20 nm is grown. SiGe strain relaxation and strain amount of strained Si can be confirmed using Raman spectroscopy or X-ray diffraction. Here, strain relaxation was confirmed using micro-Raman spectroscopy using an argon ion laser with a beam diameter of 1 μmφ as probe light. The film thicknesses of the strained Si layer 25 and the SiGe layer 22d (as described above, the first SiGe layer 22 and the SiGe buffer layer are integrated) can be evaluated using spectroscopic ellipsometry. Moreover, when cross-sectional observation using transmission electron microscopy is used, it can be confirmed that a large amount of misfit dislocations are formed at the interface between the SiGe layer 20d and the Si substrate 20. The crystallinity of the SiGe layer and strained Si formed in this example is extremely high. The verification can be confirmed by evaluating the epipit density by a seco etching method using a differential interference microscope. The threading dislocations in the strained Si layer and SiGe layer could not be confirmed. In the worst case, the threading dislocation density was 10 ³ cm ^-2 . The cause of threading dislocations depends on the cleanliness of the growth apparatus and the substrate cleaning environment.

As described above, in order to form the strain relaxation SiGe layer 22a having excellent crystallinity, the Ge concentration is desirably less than 20%. However, an example in which a strain relaxation SiGe layer having a Ge concentration of 20% or more is to be manufactured will be described with reference to FIGS. 8A and 8B. First, when the Ge concentration is less than 20 atomic%, the first strain relaxation SiGe layer 30a is formed by the above-described method, and the Ge concentration is 2 on the first strain relaxation SiGe layer 30a, which is 2 of the Ge concentration of the first strain relaxation SiGe layer 30a. A second strain relaxation SiGe layer 30b that is twice or less is formed. Then, the second strain relaxation SiGe layer 30b is formed by repeating the above-described methods of oxidation, etching, and heating. A large amount of misfit dislocations 21b is formed at the interface between the second strain relaxation SiGe layer 30b and the first strain relaxation SiGe layer 30a. Subsequently, as described above, the first Si layer 25 having a thickness of 20 nm is grown on the second strain relaxation SiGe layer 30b (FIG. 8A).
Further, the third strain relaxation SiGe layer 30c and the like may be repeatedly formed according to the required Ge concentration. Here, a buffer layer is formed on the uppermost strain relaxation SiGe layer. Subsequently, as described above, the first Si layer 25 having a thickness of 20 nm is grown on the third strain relaxation SiGe layer 30c integrated with the buffer layer (FIG. 8B).

  The feature of this embodiment is that the SiGe layer can be directly etched because dry etching is used. In addition, by introducing a chlorine-based gas into the growth apparatus, it is possible to consistently perform SiGe layer growth, SiGe etching, dislocation growth annealing, and strained Si layer growth.

<Example 4>
In the present embodiment, a substrate including compressive strain Si and a method of manufacturing the same are illustrated. In this method, the strain relaxation SiGe layer formed by using any one of the methods exemplified in Example 1, Example 2, or Example 3 is patterned by lithography, and further epitaxial growth of the Si layer and the SiGe layer is performed. And thermal oxidation. This will be described below with reference to cross-sectional views of FIGS. 9A to 9B and FIGS. 10A to 10B.

  A strain relaxation SiGe layer 24a having a thickness of about 100 nm is formed on the Si substrate or SOI substrate 20 (FIG. 9A). As described above, any one of the methods exemplified in Example 1, Example 2, or Example 3 is sufficient as the manufacturing method. The strain relaxation SiGe layer 24a is patterned by lithography to form the groove 40 (FIG. 9B). In order to form the groove 40, the etching depth of the SiGe layer 24a must reach the Si substrate 20. After chemical cleaning, the substrate is introduced into an LPCVD apparatus, and a Si layer 41 is grown so as to fill the groove 40 (FIG. 9C). The Si layer 41 grows epitaxially on the Si substrate surface so as to coincide with the Si lattice, and on the SiGe layer surface, it grows strain so as to coincide with the SiGe lattice. At the stage where the Si layer has grown as shown in FIG. 9C, misfit dislocations 21m are formed at the interface between the SiGe layer 24a and the Si layer 41. Therefore, the Si layer 41 is planarized using CMP (Chemical Mechanical Polishing) until it reaches the surface of the SiGe 24a. Therefore, the misfit dislocation 21m disappears. After chemically cleaning the substrate, the substrate is introduced into an LPCVD apparatus, and a Si layer 44 having a thickness of 20 nm is epitaxially grown (FIG. 9E). As a result, the Si film surface 44 is given tensile strain, and the Si film surface 43 is not strained.

  Next, a method for forming compressive strain Si will be illustrated using the cross-sectional views of FIGS. 10A to 10C. The tensile strained Si layer 44 and the unstrained Si layer 43 are formed separately by the method described above (FIG. 10A). A pair of grooves 50 is formed on a part of the surface of the unstrained Si layer 43 using lithography (FIG. 10B). Thereafter, the substrate is introduced into an LPCVD apparatus, a SiGe film is grown, and the trench 50 is filled with SiGe51. Next, when the RTA apparatus is used to oxidize at about 900 degrees Celsius and the oxide film is removed with a 5% HF aqueous solution, a compressive strained Si layer 52 is formed in a region sandwiched between SiGe51. In this way, the tensile strained Si layer 44, the compressive strained Si layer 52, and the unstrained Si layer 43 could be formed separately on the same substrate surface.

  The reason why the strained Si layer is formed separately as in this example is that, as described in the background art section, when forming the NMOS in the region of the tensile strained Si layer and forming the PMOS in the region of the compressive strained Si layer, Channel conductance is improved for both NMOS and PMOS. As a result, it is possible to improve the performance of a CMOS configured using these field effect transistors. Here, even in the prior art, it is possible to make a tensile and compressive strained Si layer and an unstrained Si layer separately, but in the form of the substrate as shown in this embodiment and on the same substrate surface. Is extremely difficult within the prior art. For example, when compressive strain is formed on the substrate surface, tensile strain, on the other hand, has to take a method of forming a tensile material, for example, a SiN layer on the gate in the manufacturing stage of a specific device. However, with conventional techniques, it is practically difficult to create two types of strains, tensile strain and compression strain, in the substrate. The present invention overcomes these difficulties.

<Example 5>
This example illustrates a field effect semiconductor device using a strained Si substrate, specifically, an NMOS. The strained Si substrate may be formed by any of the methods described in the first, second, or third embodiments. The manufacture of the MOS transistor itself is sufficient according to the conventional manufacturing method. A SiGe layer 24 a and a tensile strained Si layer 44 are formed on the substrate 20. An NMOS is formed on the thus prepared semiconductor substrate by a usual method. FIG. 11 is a cross-sectional view of the NMOS transistor of this example. A source region 62 and a drain region 61 are formed with a tensile strained Si layer 44 serving as a channel region interposed therebetween. A gate insulating film 66 is formed thereon, and a gate electrode 63 is disposed in a region facing the channel region. Reference numerals 64 and 65 denote a drain electrode and a source electrode, respectively. Reference numeral 70 denotes an interlayer insulating layer. The source region 62 and the drain region 61 should not contain misfit dislocations 21. For element isolation, STI (Shallow Trench Isolation) 60 was used.

<Example 6>
This example illustrates a field effect semiconductor device using a strained Si substrate, specifically, a CMOS. The strained Si substrate followed the method shown in Example 4 above. The manufacture of the CMOS transistor itself is sufficient according to the conventional manufacturing method.

  FIG. 12 is a cross-sectional view of a strained Si substrate for CMOS, and FIG. 13 is a cross-sectional view of the main part of the CMOS of this example. A strained Si substrate for CMOS is manufactured by the method described so far. A tensile strain Si 44 and a compressive strain SiGe 52 are separately formed on the Si substrate 20. SiGe layers 51 are embedded on both sides of the compressive strained SiGe 52. Reference numeral 21 denotes a misfit dislocation.

  The Si layer 44 is a tensile strained Si layer, and an NMOS is formed in this region. That is, as seen in FIG. 13, the source region 62 and the drain region 61 are doped with N type such as As. On the other hand, the Si layer 52 is compression strained Si, and a PMOS is formed in this region. That is, the source region 62a and the drain region 61a are doped with P type such as B. As a manufacturing method, a normal CMOS manufacturing process was used. STI (Shallow Trench Isolation) 60 was used for element isolation. In FIG. 13, reference numeral 66 denotes a gate insulating film, 65 and 65a denote source electrodes, 64 and 64a denote drain electrodes, 63 and 63a denote gate electrodes, and 70 denotes an interlayer insulating layer.

Hereinafter, since the present application is diverse, the main modes of the present invention are listed.
(1) A first form is a semiconductor substrate having a strained Si layer to which tensile strain is applied,
A first semiconductor stacked structure in which a first SiGe layer and a Si layer are sequentially stacked on the entire main surface or a part of a first conductivity type Si substrate or SOI substrate is provided, and an interface between the first SiGe layer and the substrate is The semiconductor substrate contains a large amount of dislocations, the SiGe layer is partially or completely strain relaxed, and the strain of the Si is tensile in the plane.
(2) The second form is a semiconductor substrate according to item (1), wherein the first SiGe layer has a thickness of 100 nm or less.
(3) The semiconductor device according to (1), wherein the Ge concentration of the first SiGe layer is less than 20%.
(4) A fourth embodiment is a semiconductor substrate having a strained Si layer to which tensile strain is applied,
A first semiconductor stacked structure in which a first SiGe layer, a second SiGe layer,..., An nSiGe layer and a Si layer are sequentially stacked on the entire main surface or a part of a first conductivity type Si substrate or SOI substrate; The interface between the first SiGe layer and the substrate and the nSiGe layer and the (n−1) th SiGe contain a large amount of dislocations, and the first SiGe layer, the second SiGe layer,. The semiconductor substrate is partially or completely strain relaxed, and the strain of Si is a semiconductor substrate that is pulled in the plane.
(5) A fifth embodiment is a semiconductor substrate in which the Ge concentration of the nSiGe layer is not more than twice the Ge concentration of the (n-1) SiGe layer in the semiconductor substrate of the preceding item (4).
(6) A sixth embodiment is a method for manufacturing a semiconductor substrate according to any one of (1), (2), (3), (4), and (5) above, on a Si or SOI substrate After depositing a SiGe layer having a critical film thickness or more, which is a film thickness causing misfit dislocations, on the entire surface or part of the substrate, the SiGe layer is thinned until the film thickness reaches about 5 nm, and then heat treatment is performed. This is a method for manufacturing a semiconductor substrate in which Si is formed on the entire surface or a part of the SiGe, including a method of partially or completely relieving the strain of the SiGe layer.
(7) A seventh embodiment is a semiconductor device having Si subjected to tensile strain, and the semiconductor substrate according to any one of (1), (2), (3), (4), and (5) A gate electrode is provided on the main surface of the second conductive type in the strained Si layer and the SiGe layer so as to sandwich a Si layer serving as a channel formation region under the gate electrode. A semiconductor device in which a source region and a drain region are formed.
(8) The eighth embodiment is a semiconductor substrate having a tensile strain Si region and a compressive strain Si region, and any one of the preceding items (1), (2), (3), (4), and (5) A main surface of the semiconductor substrate includes a second semiconductor multilayer structure including a Si region sandwiched between SiGes on a part of the surface of the region not including the first semiconductor multilayer structure, and the Si region is in-plane. It is a semiconductor substrate that has been subjected to compression strain.
(9) A ninth embodiment is a semiconductor device having Si subjected to tensile strain and Si subjected to compressive strain, wherein the main structure of the first semiconductor multilayer structure is formed on the main surface of the semiconductor substrate described in (8). A source electrode of a second conductivity type in the strained Si layer and the SiGe layer so as to sandwich a Si layer serving as a channel formation region under the gate electrode, and having a gate electrode on the surface via a gate insulating film; The strain is formed such that a drain region is formed, a gate electrode is provided on a main surface of the second semiconductor multilayer structure via a gate insulating film, and a Si layer serving as a channel formation region under the gate electrode is sandwiched. The semiconductor device is characterized in that a source region and a drain region of the second conductivity type are formed in the Si layer and the SiGe layer.
(10) In a tenth aspect, in the semiconductor device according to item (9), the source region and the drain region of the first field effect semiconductor device are N type, and the source region and the drain region of the second field effect semiconductor device are Is a P-type semiconductor device.
(11) An eleventh aspect is a semiconductor device which is a CMOS element in the semiconductor device according to (10), wherein the first field effect semiconductor device and the second field effect semiconductor device are adjacent to each other.

  The present invention has been described in detail using several embodiments. According to the present invention, a substrate on which a Si film having excellent crystallinity and controlled strain is formed can be manufactured at low cost, and the performance of an electronic element such as a field effect transistor can be improved.

  In addition, although SiGe is used to give strain to Si, there is no problem of an increase in device temperature due to the thin film.

  The above effects include not only improving the performance of a single transistor but also realizing a high-speed, high withstand voltage, low power consumption electronic device suitable for an analog-digital mixed circuit, for example.

FIG. 1 is a cross-sectional view of a substrate on which tensile, compressed, and unstrained Si related to Example 4 of the present invention are separately formed. FIG. 2 is a graph showing the Ge concentration dependence of the critical film thickness of Si. FIG. 3 is a model diagram showing an example of misfit dislocations. FIG. 4 is a model diagram showing an example of dislocation growth. FIG. 5A is a cross-sectional view of a substrate for explaining, in the order of steps, a method for producing a strain relaxation SiGe layer by a low temperature thermal oxidation method according to Example 1 of the present invention. FIG. 5B is a cross-sectional view of the substrate for explaining the manufacturing method of the strain relaxation SiGe layer by the low temperature thermal oxidation method according to the first embodiment of the present invention in the order of steps. FIG. 5C is a cross-sectional view of the substrate for explaining the manufacturing method of the strain relaxation SiGe layer by the low temperature thermal oxidation method according to the first embodiment of the present invention in the order of steps. FIG. 5D is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer by a low temperature thermal oxidation method according to the first embodiment of the present invention in the order of steps. FIG. 5E is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer by low-temperature thermal oxidation according to Example 1 of the present invention in the order of steps. FIG. 5F is a cross-sectional view of the substrate for explaining the manufacturing method of the strain relaxation SiGe layer by the low temperature thermal oxidation method according to the first embodiment of the present invention in the order of steps. 6A is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer by a thermal oxidation method according to a second embodiment of the present invention in the order of steps. FIG. 6B is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer by a thermal oxidation method according to a second embodiment of the present invention in the order of steps. FIG. 6C is a cross-sectional view of the substrate for explaining the method of manufacturing the strain relaxation SiGe layer by the thermal oxidation method in order of processes according to the second embodiment of the present invention. FIG. 6D is a cross-sectional view of the substrate for explaining the method of manufacturing the strain relaxation SiGe layer by the thermal oxidation method in order of processes according to the second embodiment of the present invention. FIG. 6E is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer by a thermal oxidation method according to Example 2 of the present invention in the order of steps. FIG. 6F is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer by a thermal oxidation method according to Example 2 of the present invention in the order of steps. FIG. 7A is a cross-sectional view of a substrate for explaining, in the order of steps, a method for producing a strain relaxation SiGe layer by a dry etching method, according to Example 3 of the present invention. FIG. 7B is a cross-sectional view of the substrate for explaining the manufacturing method of the strain relaxation SiGe layer by the dry etching method according to the third embodiment of the present invention in the order of steps. FIG. 7C is a cross-sectional view of the substrate for explaining the manufacturing method of the strain relaxation SiGe layer by the dry etching method according to the third embodiment of the present invention in the order of steps. FIG. 7D is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer by a dry etching method in order of processes according to the third embodiment of the present invention. FIG. 7E is a cross-sectional view of the substrate for explaining the manufacturing method of the strain relaxation SiGe layer by the dry etching method in order of processes according to the third embodiment of the present invention. FIG. 7F is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer by a dry etching method in order of processes according to the third embodiment of the present invention. FIG. 8 is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer having a Ge concentration of 20% or more in the order of steps. FIG. 8B is a cross-sectional view of a substrate for explaining a method of manufacturing a strain relaxation SiGe layer having a Ge concentration of 20% or more in the order of steps. FIG. 9A is a cross-sectional view of a substrate for explaining a manufacturing method according to Example 4 of the present invention in which a tensile strained Si region is separately formed in the order of steps. FIG. 9B is a cross-sectional view of the substrate for explaining a manufacturing method according to the fourth embodiment of the present invention in which the tensile strained Si region is separately formed in the order of steps. FIG. 9C is a cross-sectional view of a substrate for explaining a manufacturing method according to the fourth embodiment of the present invention in which a tensile strained Si region is separately formed in the order of steps. FIG. 9D is a cross-sectional view of the substrate for explaining a manufacturing method in order of forming a tensile strained Si region according to the fourth embodiment of the present invention. FIG. 9E is a cross-sectional view of a substrate for explaining, in the order of steps, a manufacturing method for separately producing tensile strained Si regions according to Example 4 of the present invention. FIG. 10A is a cross-sectional view of a substrate for explaining a manufacturing method according to the fourth embodiment of the present invention, in which the tensile strain Si, compression strain Si, and unstrained Si regions are separately formed in the order of steps. FIG. 10B is a cross-sectional view of a substrate for explaining a manufacturing method in order of steps for separately producing tensile strained Si, compressive strained Si, and unstrained Si regions according to Example 4 of the present invention. FIG. 10C is a cross-sectional view of a substrate for explaining a manufacturing method in order of steps for separately producing tensile strained Si, compressive strained Si, and unstrained Si regions according to Example 4 of the present invention. FIG. 11 is a cross-sectional view of an NMOS using tensile strained Si related to Example 5 of the present invention. FIG. 12 is a sectional view of a CMOS substrate according to the sixth embodiment of the present invention. FIG. 13 is a sectional view of a CMOS according to the sixth embodiment of the present invention.

Explanation of symbols

1: Si substrate, 2: SiO ₂ layer, 3: Si layer, 4: Misfit dislocation, 5: SiGe layer, 6: Compression strained Si layer, 7: SiGe layer, 8: Tensile strained Si layer, 10: Critical film Thick curve, 11: misfit dislocation, 12: misfit dislocation, 20: substrate, 21: misfit dislocation, 21: misfit dislocation, 21a: misfit dislocation, 21b: misfit dislocation, 21c: misfit dislocation, 22 : SiGe layer, 22b: SiGe layer, 22c: SiGe layer, 22d: SiGe layer, 23: oxide film, 24: misfit dislocation, 24a: SiGe layer, 25: tensile strained Si layer, 30a: SiGe layer, 30b: SiGe Layer, 30c: SiGe layer, 32: SiGe layer, 33: SiO ₂ layer, 35: SiGe layer, 35a: SiGe layer, 36: tensile strained Si layer, 40: groove, 41: Si layer, 42: unstrained Si layer Surface: 43: Unstrained Si layer, 44: Tensile strained Si layer, 50: Groove, 51: SiGe layer, 52: Compression strained Si Layer, 60: STI, 61: drain region, 62: source region, 63: gate electrode, 64: drain electrode, 65: source electrode, 61a: drain region, 62a: source region, 63a: gate electrode, 64a: drain electrode 65a: source electrode, 66: gate insulating film, and 70: interlayer insulating film.

Claims (20)

A first conductivity type Si substrate or SOI substrate;
A first semiconductor stacked structure in which a first SiGe layer and a Si layer are sequentially stacked over the entire or part of the main surface of the substrate;
The interface between the first SiGe layer and the substrate contains dislocations;
The semiconductor substrate, wherein the first SiGe layer is partially or completely strain-relieved, and the Si layer is a first strained Si layer having a tensile strain in a plane.   The semiconductor substrate according to claim 1, wherein the first SiGe layer has a thickness of 100 nm or less.   2. The semiconductor substrate according to claim 1, wherein the Ge concentration of the first SiGe layer is less than 20% in terms of the number of atoms. A plurality of SiGe layers of nth SiGe layer (n is a natural number of 2 or more) from the first SiGe layer, and a Si layer over the whole or part of the main surface of the first conductivity type Si substrate or SOI substrate; Comprising a first semiconductor stacked structure in which are sequentially stacked,
The interface between the first SiGe layer and the substrate and the interface between the nth SiGe layer and the (n-1) th SiGe layer contain dislocations,
The first SiGe layer and the n-th SiGe layer are partially or completely strain-relieved, and the Si layer is a first strained Si layer having a tensile strain in a plane. The semiconductor substrate according to claim 1.   5. The semiconductor substrate according to claim 4, wherein a Ge concentration of the n-th SiGe layer is not more than twice a Ge concentration of the (n−1) -th SiGe layer. A part of the surface of the region not including the first semiconductor multilayer structure includes a second semiconductor multilayer structure including a Si region sandwiched between SiGe layers,
The semiconductor substrate according to claim 1, wherein the Si region is subjected to a compressive strain in a plane. A part of the surface of the region not including the first semiconductor multilayer structure includes a second semiconductor multilayer structure including a Si region sandwiched between SiGe layers,
The semiconductor substrate according to claim 2, wherein the Si region is subjected to a compressive strain in a plane. A part of the surface of the region not including the first semiconductor multilayer structure includes a second semiconductor multilayer structure including a Si region sandwiched between SiGe layers,
The semiconductor substrate according to claim 3, wherein the Si region is subjected to a compressive strain in a plane. A part of the surface of the region not including the first semiconductor multilayer structure includes a second semiconductor multilayer structure including a Si region sandwiched between SiGe layers,
The semiconductor substrate according to claim 4, wherein the Si region is subjected to a compressive strain in a plane. A part of the surface of the region not including the first semiconductor multilayer structure includes a second semiconductor multilayer structure including a Si region sandwiched between SiGe layers,
The semiconductor substrate according to claim 5, wherein the Si region is in a state of being subjected to compressive strain in a plane. A first conductivity type Si substrate or SOI substrate;
A first semiconductor stacked structure in which a first SiGe layer and a Si layer are sequentially stacked over the entire or part of the main surface of the substrate;
The interface between the first SiGe layer and the substrate contains dislocations;
The first SiGe layer is partially or fully strain relaxed;
The Si layer is a semiconductor substrate that is a first strained Si layer having a strain in a tensile state in the plane;
A first field effect transistor having a gate electrode on the first strained Si layer with a gate insulating film interposed therebetween, and having the first strained Si layer under the gate electrode as a channel formation region; A semiconductor device including at least the semiconductor device.   The semiconductor device according to claim 11, wherein a film thickness of the first SiGe layer is 100 nm or less.   The semiconductor device according to claim 11, wherein the Ge concentration of the first SiGe layer is less than 20% in terms of atomic percentage. A plurality of SiGe layers of a first SiGe layer (n is a natural number greater than or equal to 2) from the first SiGe layer on the whole or part of the main surface of the first conductivity type Si substrate or SOI substrate; Comprising a first semiconductor stacked structure in which are sequentially stacked,
The interface between the first SiGe layer and the Si substrate or the SOI substrate and the nth SiGe layer and the (n-1) th SiGe layer contain dislocations,
A semiconductor substrate in which the n-th SiGe layer is partially or completely strain-relieved from the first SiGe layer, and the Si is a first strained Si layer having tensile strain in-plane;
A first field effect transistor having a gate electrode on the first strained Si layer with a gate insulating film interposed therebetween, and having the first strained Si layer under the gate electrode as a channel formation region; The semiconductor device according to claim 11, comprising at least the semiconductor device.   The semiconductor device according to claim 14, wherein a Ge concentration of the n-th SiGe layer is not more than twice a Ge concentration of the (n−1) -th SiGe layer. The first semiconductor multilayer structure;
At least a second semiconductor multilayer structure having a Si region sandwiched between SiGe layers in at least a part of a region not having the first semiconductor multilayer structure on the main surface of the substrate;
In the first semiconductor multilayer structure, a first strained Si layer region that has undergone tensile strain in the plane is used, and in the second semiconductor multilayer structure, a second strained Si region that has undergone compressive strain in the plane. Have
The first strained Si layer region under the first gate electrode having a first gate electrode via a gate insulating film on the first strained Si layer region of the first semiconductor stacked structure. A first field effect transistor having a channel formation region in
A second gate electrode is provided on the second strained Si layer region of the second semiconductor multilayer structure via a gate insulating film, and the second strained Si layer region under the second gate electrode. The semiconductor device according to claim 11, further comprising at least a second field effect transistor having a channel formation region.   The source region and drain region of the first field effect transistor are N-type, and the source region and drain region of the second field effect transistor are P-type. Semiconductor device.   18. The semiconductor device according to claim 17, wherein the first field-effect transistor and the second field-effect transistor have a region constituting a COMS.   18. The semiconductor device according to claim 17, wherein the first SiGe layer has a thickness of 100 nm or less. Depositing a SiGe layer having a thickness greater than or equal to a critical thickness, which is a thickness at which misfit dislocations are generated, on a Si substrate or an SOI substrate;
A step of reducing the thickness of the deposited SiGe layer to a thickness that causes dislocation growth, and a step of performing a heat treatment to partially or completely relieve strain of the SiGe layer,
Forming a Si layer on the SiGe layer. A method of manufacturing a semiconductor substrate, comprising:

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