JP2006285683A - Information processing apparatus, arithmetic processing device and memory access control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To streamline the operation of a CPU by predicting traffic on a bus connecting the CPU and an MMU. <P>SOLUTION: An instruction decoder 13 decodes an instruction into an operation code and sends it to a scalar request count calculation part 42. The scalar request count calculation part 42 calculates an expected value of issued memory request count and sends it to an arithmetic unit 48 via a registration-based calculation control part 46 and the like. When data reading from a main storage part 21 is completed, a completion-based calculation control part 47 calculates an executed memory request count and sends it to the arithmetic unit 48. The arithmetic unit 48 adds up a value retained in a request counter 49 and the values sent from the registration-based calculation control part 46 and completion-based calculation control part 47 and stores the result in the request counter 49. According to the value stored in the request counter 49, control parts 51 to 54 in an operation control part 50 output various control signals for optimizing the operation of memory access. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, an arithmetic processing apparatus, and a memory access control method, and more particularly, an information processing apparatus including a pipeline processing type arithmetic processing apparatus including a cache memory, a pipeline processing type arithmetic processing apparatus, and a memory access. It relates to a control method.

  In general, the pipeline processing method is roughly divided into an instruction fetch stage, an instruction decode stage, a data read stage, an instruction execution stage, and a write stage, and the stages proceed in this order.

  The instruction fetch stage reads the instruction, the instruction decode stage decodes the instruction, the data read stage prepares the data required for the instruction operation, the instruction execution stage performs the actual operation, and the write stage displays the operation result. Writing is executed.

  If the instruction or data does not exist in the cache memory, it is necessary to read the instruction or data from the main memory. If the state in which instructions and data are read from the main memory continues, the processing capability of the arithmetic processing unit is reduced.

As one method for effectively utilizing the processing power of the arithmetic processing unit, Patent Literature 1 estimates a statistical value of the memory system interaction characteristic between contexts in a computer system, and uses this to optimize instruction scheduling and instruction / data arrangement. It is disclosed to apply to
Japanese Patent Laid-Open No. 11-353231

  However, in the method disclosed in Patent Document 1, the estimated statistical value of the memory system interaction characteristic is merely effectively used for the processing capability of the arithmetic processing unit in units of programs. For this reason, it is not possible to efficiently perform arithmetic operations on various programs using a general-purpose arithmetic processing device.

  In addition, the situation in which the speed of improving the memory access operating speed cannot keep up with the speed of improving the operating frequency of the arithmetic processing unit continues. Therefore, the number of pipeline stages increases, and the time from the decode stage located upstream of the pipeline to the stage where the memory request is actually output tends to increase. There is a need to make effective use of this increasingly long time.

  The present invention has been made in view of the above problems, and predicts the number of memory requests to be issued based on the operand of an instruction obtained at the time of instruction decoding, and uses this calculated value to make it more efficient than in the past. It is an object of the present invention to provide an information processing apparatus, an arithmetic processing apparatus, and a memory access control method that operate on the Internet.

An arithmetic processing apparatus according to the first aspect of the present invention provides:
A control unit;
An information processing apparatus comprising a memory,
The controller is
An instruction decoder that extracts an opcode and an operand from the instruction;
Instruction type determining means for determining whether or not the operand fetched by the instruction decoder is an operand of an instruction that accesses the memory;
Addition value calculating means for calculating an expected value of the number of requests issued when accessing the memory by this instruction when the instruction type determining means determines that the operand is an operand of an instruction accessing the memory When,
Integrating means for integrating the values calculated by the added value calculating means;
It comprises.

  According to the present invention, the expected value of the number of memory requests exchanged for memory access between the arithmetic processing unit and the memory is calculated, and the calculated expected value is integrated. Using this integrated value, the information processing apparatus can be operated so that data can be exchanged smoothly between the arithmetic processing unit and the memory.

In the above arithmetic processing unit,
The control unit preferably includes subtraction value calculation means for calculating the expected value calculated by the addition value calculation means as a subtraction value for the instruction that is the basis of the access after the access to the memory is completed. .
In this case, the integration means integrates the value calculated by the addition value calculation means and the subtraction value calculation means.

In the above arithmetic processing unit,
The memory is a memory that refreshes stored contents at a predetermined interval or shorter than the predetermined interval in order to keep storing information.
In this case, the control unit
Integrated value determining means for determining whether or not the value calculated by the integrating means is 0;
When the integrated value determining means determines that the value calculated by the integrating means is 0, a refresh instruction signal for refreshing the stored contents of the memory is output to the memory, and the value calculated by the integrating means is 0. Refresh instruction means for outputting a refresh instruction signal to the memory at the predetermined interval when it is determined that the stored contents of the memory are not,
It is desirable to comprise.

  In this case, when it is predicted that no memory request will occur, the refresh instruction means outputs an instruction to refresh the stored contents of the memory, and the stored contents of the memory are refreshed. As a result, it is possible to reduce the memory access waiting time caused by refreshing the stored contents of the memory.

The information processing apparatus may operate in synchronization with a clock signal.
In this case, when the integrated value determining unit determines that the value calculated by the integrating unit is 0, the control unit outputs a clock control signal for increasing the frequency of the clock signal from a basic frequency, and It is desirable to provide a clock control means for outputting a clock control signal for returning the frequency of the clock signal to the fundamental frequency when it is determined that the value calculated by the integrating means is not zero.

In the information processing apparatus,
The memory may operate in synchronization with a memory clock signal.
In this case, when the integrated value determining unit determines that the value calculated by the integrating unit is 0, the control unit outputs a memory clock control signal that reduces the frequency of the clock signal from the basic frequency, It is desirable to provide memory clock control means for outputting a memory clock control signal for returning the frequency of the clock signal to the fundamental frequency when it is determined that the value calculated by the integrating means is not zero.

In the information processing apparatus,
The control unit may include request control means for changing a maximum number of memory access requests that can be transmitted and received between the control unit and the memory at the same time in accordance with the integrated value calculated by the integrated value calculating means.

  According to the present invention, for example, when the number of memory access requests is large, the maximum number of memory access requests transmitted / received between the control unit and the memory is reduced to suppress the issuance of memory access requests and the number of memory access requests is small. In some cases, it is possible to increase the maximum number of issued memory access requests transmitted and received between the control unit and the memory so as not to limit the issuance of memory access requests.

In the information processing apparatus,
The information processing apparatus preferably includes a cache memory.
In this case, the control unit includes a miss rate calculation means for calculating a cache miss rate of the cache memory,
The instruction type determining means is further means for determining whether or not the operand fetched by the instruction decoder is a scalar type instruction,
The addition value calculation means calculates the expected value according to the cache miss ratio calculated by the miss rate calculation means when the instruction type determination means determines that the operand is an operand of a scalar type instruction.

In the information processing apparatus,
When the integrated value determining unit determines that the value calculated by the integrating unit is 0, the control unit performs readjustment of a delay lock loop of a memory bus connecting the control unit and the memory. A DLL control unit that outputs a DLL control signal to output the DLL signal at a predetermined interval when readjustment of the delay lock loop of the memory bus is performed when it is determined that the value calculated by the integration unit is not 0. You may have.

According to the arithmetic processing apparatus according to the second aspect of the present invention,
An arithmetic processing unit that exchanges data with a memory via a memory bus,
An instruction decoder that extracts an opcode and an operand from the instruction;
Instruction type determining means for determining whether or not the operand fetched by the instruction decoder is an operand of an instruction that accesses the memory via the memory bus;
Addition value calculating means for calculating an expected value of the number of requests issued when accessing the memory by this instruction when the instruction type determining means determines that the operand is an operand of an instruction accessing the memory When,
Integrating means for integrating the values calculated by the added value calculating means;
It comprises.

A memory access control method according to a third aspect of the present invention includes:
An arithmetic processing unit that exchanges data with the memory via the memory bus
A decoding step for extracting an opcode and an operand from the instruction;
A determination step of determining whether or not the operand fetched in the decoding step is an operand of an instruction that accesses the memory via the memory bus;
An addition value calculating step of calculating an expected value of the number of requests issued when accessing the memory with this instruction when the determining step determines that the operand is an operand of the instruction accessing the memory;
An integration step of integrating the values calculated by the addition value calculation step;
A control step of optimizing the memory access of the arithmetic processing unit according to the value integrated in the integration step;
Is provided.

  According to the present invention, the number of memory access requests issued by the arithmetic processing unit when data is read from or written to the memory is predicted according to the result of decoding at the decoding stage, and the operation of the subsequent stage is efficiently performed according to the predicted value. Can be controlled.

Embodiments according to the present invention will be described below with reference to the drawings.
In the present embodiment, instructions that need to exchange data between the arithmetic processing unit and the memory are a load instruction and a store instruction. The load instruction and the store instruction can be classified into a scalar instruction related to only a single register and a vector instruction related to a plurality of registers. Each instruction including a load instruction and a store instruction is composed of one opcode and zero or more (three or less) operands. Depending on the opcode, some operands are implicitly specified. Furthermore, memory access is performed in the order of instruction execution.
In the following description, when the address is simply used, it means a main memory address.

FIG. 1 is a block diagram showing the configuration of an arithmetic processing unit and its peripheral devices according to an embodiment of the present invention. The arithmetic processing unit and its peripheral devices are components of an information processing apparatus such as a main frame and a personal computer.
Note that a line in which the arrowhead is a straight line (hereinafter referred to as a data line) is a signal line through which operation data (command or data in a normal sense) passes, and a line in which the arrowhead is a triangle ( (Hereinafter referred to as a control signal line) is a signal line through which various control signals in the arithmetic processing unit 1 pass. Also, the graphic and external input / output related elements that are not directly related to the present invention are omitted.

  The arithmetic processing apparatus 1 according to the present embodiment includes a logic circuit and a sequential circuit mounted on silicon. The arithmetic processing unit 1 interprets and executes an instruction sequence stored in the main storage unit 21, data stored in the main storage unit 21, or data input from input device data (not shown) in synchronization with a clock signal. Then, predetermined processing is executed, and the processing result is written in the main storage unit 21 or output to an output device (not shown). A part of the contents stored in the main storage unit 21 is temporarily stored in the cache memory 23. The arithmetic processing unit 1 actually reads and writes instruction sequences and data stored in the cache memory 23 instead of directly reading and writing instruction sequences and data from the main storage unit 21.

  As shown in FIG. 1, the arithmetic processing device 1 includes an instruction fetch unit 11, an instruction decoder 13, a read stage 15, an arithmetic unit 17, a write stage 19, a register group 29, and a cache miss rate calculation unit 41. A scalar request number calculation unit 42, a reply reception unit 43, a set value storage unit 44, a registration time calculation control unit 46, an end time calculation control unit 47, a calculator 48, a request counter 49, an operation A control unit 50, a table management unit 121, and a memory request management table 127 are provided. Each of these elements is configured by combining a logic circuit and a sequential circuit. In addition, there are an operation clock signal generator 60 and a memory clock signal generator 61 as peripheral devices.

  The instruction fetch unit 11 reads an instruction stored at an address specified by a program counter (not shown) from the cache memory 23 and transfers it to the instruction decoder 13.

  The instruction decoder 13 uses which data is stored in which register or in which address from the operand, which operation is requested from the instruction opcode, and the register or in which address the operation result of the arithmetic unit 17 is stored. Whether it is stored or not is determined. If it is determined from the operand whether or not there is a “possibility” that access (read / write) to the main storage unit 21 occurs, and it is determined that access to the main storage unit 21 may occur, The operation code obtained as a result of decoding is recorded in the memory request management table 127 as request management information. As a result, even if the access to the cache memory 23 is completed, the determination condition is satisfied. The instruction decoder 13 transmits the operation code obtained as a decoding result to the scalar request number calculation unit 42, the registration time calculation control unit 46, and the table management unit 121 as operation code information.

  The read stage 15 reads and prepares data necessary for the subsequent execution stage from the register or address specified by the operand from the cache memory 23, the main storage unit 21, and the register group 29. When data is read from the cache memory 23 and the main storage unit 21, the data is requested to be read via the memory management unit 25.

  The arithmetic unit 17 is in charge of an execution stage that executes an operation specified by an operation code such as addition, subtraction, and condition determination. Then, the calculation result is transmitted to the writing stage 19.

  The write stage 19 writes the operation result to one register in the register group 29 designated by the operand or a designated address in the main storage unit 21.

  The register group 29 includes a plurality of registers that temporarily hold the calculation results of the calculator 17.

  The cache miss rate calculation unit 41 receives cache hit and cache miss information from the memory management unit 25, calculates the cache miss rate at a predetermined number of cache determinations (for example, 1000 times), and sends it to the scalar request number calculation unit 42. Send. The cache miss rate calculation unit 41 repeatedly calculates the cache miss rate.

  The scalar request number calculation unit 42 determines whether or not the opcode information transmitted from the instruction decoder 13 is data indicating a load instruction (scalar instruction). When it is determined that the data indicates a load instruction (scalar instruction), the scalar request number calculation unit 42 obtains the cache miss rate transmitted from the cache miss rate calculation unit 41 by multiplying the number of memory requests issued when the cache is read. The obtained value is transmitted to the table management unit 121. When it is determined that the data does not indicate a load instruction (scalar instruction), the scalar request number calculation unit 42 transmits a value 0 to the table management unit 121.

  The reply receiving unit 43 receives a completion signal that is output when the memory management unit 25 reads data stored in the main storage unit 21 to the cache memory 23, and transmits it to the table management unit 121.

  The set value storage unit 44 stores, for each opcode, the number of memory requests that may be issued when the vector type store / load instruction is executed.

  The table management unit 121 controls registration and deletion of entries in the memory request management table 127. When the table management unit 121 receives the operation code information from the instruction decoder 13, if the instruction indicated by the operation code information is a scalar type load / store instruction, the expected value of the number of memory requests issued from the scalar request number calculation unit 42 Is registered in the memory request management table 127 in association with the opcode information. When the instruction indicated by the opcode information is a vector type load / store instruction, the number of memory requests issued by the instruction is retrieved from the set value storage unit 44 and registered in the memory request management table 127 associated with the opcode information. Further, when the completion signal is received from the reply receiving unit 43, the table management unit 121 records that the data is read from the main storage unit 21 or the cache memory 23 for the entry corresponding to the completion signal.

  The memory request management table 127 associates instructions that may issue a memory request when the processor 1 reads / writes data from / to the main storage unit 21 or the cache memory 23, and the number of memory requests issued by the instruction. Are sequentially recorded as request management information. The memory request management table 127 is used cyclically. That is, when request management information is registered in the last entry, the next registration moves to the first entry. Each entry in the memory request management table 127 is returned to the state in which nothing is registered and reused after completion of reading and writing of data corresponding to the registered request management information. The number of entries in the memory request management table 127 (eight in FIG. 2) is set with a margin so that the entries can be reused without destroying the stored contents of the entries in use.

As shown in FIG. 2, each entry of the memory request management table 127 includes “entry number”, “instruction type information”, “in-use information”, “number of requests”, and “reply information”. .
“Entry number” is identification information of each entry in the memory request management table 127.
“Instruction type information” records an operation code that may issue a memory request. In FIG. 2, the instructions are written in a natural language for easy understanding, but are actually recorded in binary numbers. Further, “empty” (entry number 7) indicates that the entry is unused, and stores, for example, an undefined opcode or a so-called NOP instruction opcode.
“In-use information” is data indicating whether or not the entry is in use. If it is “1”, it is in use, and if it is “0”, it indicates that it is unused. When “instruction type information” is registered in the entry, it is updated from “0” to “1”.
“Number of requests” is an expected value of the number of memory requests issued by the instruction corresponding to the instruction type information.
“Reply information” is data indicating whether or not the data necessary for processing the instruction corresponding to the instruction type information has been read out from the main storage unit 21 or the cache memory 23. “0” indicates that a request is being made.
When both “in-use information” and “reply information” are “1”, the table management unit 121 returns to the unused state as indicated by the entry number 7 column after a predetermined time has elapsed.

  Returning to FIG. 1, the registration-time calculation control unit 46 calculates a value to be added when request management information is registered in the memory request management table 127 and passes it to the computing unit 48. The value to be added is a value determined by referring to the “number of requests” of the entry number transmitted from the table management unit 121 or according to the opcode information received from the instruction decoder 13.

  The end time calculation control unit 47 calculates a value to be subtracted when the memory access is completed for the instruction registered in the memory request management table 127, converts it to a negative number, and passes it to the computing unit 48. The value to be subtracted is a value registered in the “request count” of the entry in which “reply information” in the memory request management table 127 is changed from “0” to “1”.

  The computing unit 48 is composed of an adder, and the value transmitted from the registration-time calculation control unit 46 and the end-time calculation control unit 47 (considered as a negative number) and the value stored in the request counter 49 are Add and store in request counter 49.

  The request counter 49 is a register that stores the addition result of the computing unit 48. The value stored in the request counter 49 is read by the operation control unit 50.

  The operation control unit 50 generates various control signals for controlling the operation of the arithmetic processing unit 1 or the main storage unit 21 according to the count value of the request counter 49. The operation control unit 50 functionally includes a refresh timing control unit 51, a delay lock loop (DLL) control unit 52, a clock control unit 53, and a prefetch preload control unit 54.

The refresh timing control unit 51 generates and outputs a refresh signal having a meaning of refreshing the stored contents of the main memory unit 21 at least at a predetermined interval (which depends on the time constant of the memory cell in the main memory unit 21). To do. However, when the value read from the request counter 49 is 0, a refresh signal is immediately generated.
While the stored contents of the main storage unit 21 are refreshed, the main storage unit 21 cannot cope with memory access. Therefore, by refreshing the stored contents of the main memory 21 in anticipation of no memory access, the number of memory accesses during the refresh is reduced, and the processing performance of the arithmetic processing unit 1 is improved.

The DLL control unit 52 has at least a predetermined interval (this is the longest time that the operation of each unit can be completed in one clock even if variations occur in various signals due to a change in the operating environment of the arithmetic processing unit 1. It is an experimentally and empirically determined time shorter than the time) and generates and outputs an adjustment signal having a meaning of instructing the readjustment of the DLL. However, when the value read from the request counter 49 is 0, an adjustment signal is immediately generated. Here, the readjustment of DLL means that various signals in the arithmetic processing unit 1 are synchronized with the clock signal by adjusting the delay time in the delay element. Further, the data buses A and B between the arithmetic processing unit 1 and the memory management unit 25 are subject to DLL readjustment.
By re-adjusting the DLL in anticipation of no memory access, an increase in memory access time during DLL re-adjustment is reduced. Thereby, the processing performance of the arithmetic processing device 1 is improved.

The clock control unit 53 outputs a clock control signal for controlling the frequency of the clock signal generated by the operation clock signal generation unit 60 at a voltage level according to the count value of the request counter 49. For example, when the counter value of the request counter 49 is 0, the voltage is set so that the frequency of the clock signal is increased from the reference frequency, and when the counter value of the request counter 49 is 0 or more (other than), the clock frequency is returned to the reference frequency. Adjust the level and output the clock control signal.
Thereby, the power consumption of the arithmetic processing unit 1 can be reduced.
The clock control signal output from the clock controller 53 controls the frequency of the memory clock signal generated by the memory clock signal generator 61 at a voltage level according to the count value of the request counter 49. For example, the clock control unit 53 outputs the clock control signal with the voltage level adjusted as described above, so that when the counter value of the request counter 49 is 0, the frequency of the memory clock signal is lowered from the basic frequency, and the request counter When the count value of 49 is 0 or more, the frequency of the memory clock signal is returned to the basic frequency or increased from the basic frequency. As a result, the memory access turnaround time can be reduced.

  The prefetch preload control unit 54 controls the number of requests issued at the time of prefetching and preloading instruction sequences and data sequences. For example, when 0 ≦ counter value <100, control is performed such that the number of request issuances is 3, when 100 ≦ counter value <1000, the request issuance number is 2, and when 1000 ≦ counter value, the request issuance number is 1.

  The operation clock signal generator 60 generates a clock signal at a frequency corresponding to the voltage of the clock control signal received from the clock controller 53 and supplies the clock signal to each unit of the arithmetic processing unit 1. For this reason, the frequency of the clock signal generated by the operation clock signal generator 60 increases or decreases according to the counter value of the request counter 49. However, the frequency changes only within a predetermined range set in an operation range where an operation error does not occur above and below the reference frequency.

  The memory clock signal generation unit 61 generates a memory clock signal at a frequency corresponding to the voltage of the clock control signal received from the clock control unit 53 and supplies the memory clock signal to the main storage unit 21, the cache memory 23, and the memory management unit 25. To do. For this reason, the frequency of the bus clock signal generated by the memory clock signal generator 61 increases or decreases according to the counter value of the request counter 49. However, the frequency changes only within a predetermined range set in an operation range where an operation error does not occur above and below the reference frequency.

  The main storage unit 21 is composed of, for example, a DRAM (Dynamic Random Access Memory), and stores a program (instruction sequence) executed by the arithmetic processing device 1 and a data sequence necessary for execution of the program. In response to the refresh signal output from the refresh timing control unit 51, the main storage unit 21 refreshes the stored contents each time.

  The cache memory 23 is composed of, for example, an SRAM (Static Random Access Memory), and stores cache data such as an instruction sequence stored in the main storage unit 21. Reading of data into the cache memory 23 is performed in units of cache lines. For example, when the size (length) of the cache line is 64 bytes, the number of memory requests issued at the time of reading is 8 bytes. In the case of a store instruction, the number of memory requests issued according to a scalar type store instruction or a vector type store instruction changes. 1 for a scalar type store instruction, and changes according to the data size to be stored for a vector type store instruction.

  A memory management unit (MMU) 25 is located between the arithmetic processing unit 1, the cache memory 23, and the main storage unit 21, and the data stored in the cache memory 23 is a copy of which part of the main storage unit 21. It is also determined whether or not to overwrite the stored contents of the cache memory 23.

  When reading data, the MMU 25 determines whether or not the data stored at the address specified by the instruction fetch unit 11, the read stage 15, and the write stage 19 is stored in the cache memory 23. If it is determined that the data is stored, the data is read from the cache memory 23. If it is determined that the data is not stored, the data is read from the main storage unit 21 and a copy is stored in the cache memory 23. When data is written to the main storage unit 21, the data is stored in the main storage unit 21. Further, when the data at the designated address is stored in the cache memory 23, the data is also stored in the cache memory 23. When the reading and writing of data is completed, the MMU 25 transmits a completion signal indicating that to the reply receiving unit 43.

  Hereinafter, of the operations of the information processing apparatus 1 and peripheral devices according to the present embodiment with reference to the drawings, a part for estimating the number of memory requests according to the opcode information will be described.

  First, referring to FIG. 3, a scalar request number calculation unit 42, a table management unit 121, a memory request management table 127, and a registration calculation at the time of registration processing for registering request management information in the memory request management table 127. Operations of the control unit 46 and the computing unit 48 will be described.

  First, the registration process is started when the instruction decoder 13 decodes the instruction. The instruction decode 13 transmits the operation code obtained by decoding the instruction as operation code information to the scalar request number calculation unit 42, the table management unit 121, and the registration time calculation control unit 46 (step S101).

  The table management unit 121 determines whether or not an instruction corresponding to the operation code included in the received operation code information is an instruction (load instruction or store instruction) that may access the main storage unit 21 (step S102). . If it is determined that the instruction is an instruction that may access the main storage unit 21 (step S102: YES), the table management unit 121 creates request management information based on the opcode information, and generates a memory request management table. In step S103, the entry number of the registered entry is transmitted to the registration calculation control unit 46. Here, when the opcode corresponds to a scalar type instruction, the value calculated by the scalar request number calculation unit 42 is selected as the “number of requests”, and when it corresponds to a vector type instruction, the value read from the setting value storage unit 44 Select. Then, the “in-use information” of the entry in which the request information is registered is changed to “1” meaning in use. If it is determined that the instruction is not an instruction that may access the main storage unit 21 (step S102: NO), the table management unit 121 does nothing and advances the process to step S104.

  Next, the registration-time calculation control unit 46 reads the number of requests stored in the entry corresponding to the entry number notified from the table management unit 121 from the memory request management table 127 and transmits it to the computing unit 48. Finally, the computing unit 48 adds the stored value of the request counter 49 and the value transmitted from the registration time calculation control unit 46 (step S104), stores it in the request counter 49, and ends the registration process.

  Referring to FIG. 4, reply receiving unit 43, table management unit 121, memory request management table 127, and end time calculation control unit 47 at the time of deletion processing for deleting request management information in memory request management table 127. The operation with the computing unit 48 will be described.

  First, the deletion process is started when a completion signal indicating that the MMU 25 has read the requested data is transmitted from the MMU 25 to the reply receiving unit 43. The table management unit 121 receives a completion signal from the reply receiving unit 43 (step S201). As described above, in this embodiment, the reception order of the opcode information and the reception order of the completion signal are the same. It is possible to determine which entry of which “reply information” should be set to “1”. When the table management unit 121 determines an entry whose “reply information” should be “1”, the table management unit 121 updates the corresponding “reply information” to 1 (step S202). Then, the table management unit 121 transmits the entry number of the entry for which data reading / writing has been completed to the termination control unit 47.

  Next, the end-time calculation control unit 47 reads the number of requests stored in the entry corresponding to the entry number notified from the table management unit 121 from the memory request management table 127 and transmits it to the computing unit 48. Finally, the computing unit 48 subtracts the value transmitted from the registration calculation control unit 46 from the stored value of the request counter 49 (step S203), stores it in the request counter 49, and ends the deletion process.

  Actually, since the registration process and the deletion process are executed in parallel, the computing unit 48 uses a value transmitted from the registration time calculation control unit 46 and a value transmitted from the end time calculation control unit 47 (however, The value is treated as a negative number) and the value stored in the request counter 49 is added and stored in the request counter 49.

  By the registration process and the deletion process described above, it is possible to calculate the number of memory requests going back and forth on the buses A and B connecting the arithmetic processing unit 1 and the MMU 25. The calculated number of memory requests represents a predicted value of the load (congestion degree) of the buses A and B connecting the arithmetic processing unit 1 and the MMU 25. Since the MMU 25 needs to calculate the physical address from the virtual address in order to access the main storage unit 21, there is a time delay between the instruction decode 13 decoding the instruction and the actual request being issued. is there. Therefore, by adopting the configuration shown in the embodiment of the present invention, it is possible to know the number of requests at an earlier stage than counting at the stage where an actual request is issued.

  The control units 51 to 54 in the operation control unit 50 operate as follows according to the hold value of the request counter 49.

  When the refresh timing control unit 51 reads the value stored in the request counter 49 and determines that this value is 0, the refresh timing control unit 51 generates a refresh signal having a meaning of refreshing the stored contents of the main storage unit 21, and To 21. Even if the value read from the request counter 49 is not the predetermined time 0, a refresh signal is generated and output to the main storage unit 21 when a predetermined time has elapsed since the previous refresh.

  The DLL control unit 52 reads the value stored in the request counter 49 and, if it is determined that this value is 0, generates an adjustment signal having a meaning of instructing readjustment of the DLL, and outputs it to the buses A and B. . Even if the value read from the request counter 49 is not the predetermined time 0, an adjustment signal is generated and output to the buses A and B when a predetermined time elapses after a previous DLL readjustment instruction is issued.

  When the clock controller 53 reads the value stored in the request counter 49 and determines that the value is 0, the clock controller 53 adjusts the voltage level to increase the frequency of the clock signal and sends the clock control signal to the operation clock signal generator 60. Output to. When the read value is not 0, the clock control unit 53 adjusts the voltage level so as to return the frequency of the operation clock signal to the basic frequency, and outputs the clock control signal to the operation clock signal generation unit 60. Further, when the read value of the memory clock signal output from the memory clock signal generation unit 61 by the same clock control signal is 0, the frequency of the memory clock signal is lowered from the basic frequency, and when the read value is not 0, Return the frequency of the memory clock signal to the basic frequency or increase it from the basic frequency.

  The prefetch preload control unit 54 reads the value stored in the request counter 49. When this value is 0 or more and less than 100, the number of issued memory requests is 3, and when the value is 100 or more and less than 1000, the number of issued memory requests is 2. When the number is 1000 or more, a control signal is transmitted to the instruction decoder 13, the read stage 15, and the write stage 19 so that the number of issued memory requests is 1.

  As described above, according to the information processing apparatus according to the embodiment of the present invention, the timing of refreshing the main memory unit 21 and the DLL readjustment operation according to the memory access fluctuation to the main memory unit 21 Thus, the memory access efficiency can be improved by controlling the timing of the above, the temporary rise and fall of the operating frequency, and the control of the number of memory requests issued, thereby improving the operating frequency of the arithmetic processing unit 1.

In addition, this invention is not limited to the said embodiment, A various deformation | transformation and application are possible.
For example, in the above-described embodiment, there are two types of instructions that cause a memory access: a load instruction and a store instruction, but the present invention is not limited to these. Furthermore, the above operation may be performed by only one of a vector type instruction and a scalar type instruction. Further, although the external input / output command is not considered in the above embodiment, it can also be considered by applying the method described in the above embodiment.

  Further, although the case where the data writing method to the cache memory 23 is the write-through method has been described as an example, the write-back method may be used. Note that the cache memory 23 may be built in the arithmetic processing unit 1.

  In the above embodiment, a DRAM requiring a refresh operation has been described as an example of the main storage unit 21, but an SRAM (Static RAM) may be used. In this case, the refresh operation is not necessary. In addition, when there are multi-stage cache memories such as a secondary cache, the memory request management table 127 count may be increased or decreased when there is a possibility of memory access between the arithmetic processing unit 1 and the main storage unit 21. You may make it make it.

  In addition, the present invention can be applied in combination with known methods for improving the operating frequency of the arithmetic processing apparatus 1, such as register renaming, cross-flow of calculation results at the execution stage, and the like.

  Further, the set value storage unit 44 may be omitted. In this case, the table management unit 121 generates the number of memory requests that may be issued according to the type of the operation code included in the operation code information.

  In the above embodiment, the determination condition in each of the control units 51 to 54 in the operation control unit 50 is an example, and can be determined by an arbitrary threshold value.

  Further, the request counter 49 may be a register accessible by a privileged instruction or a non-privileged instruction. In this case, the program side can use the result of request number prediction. For example, it can be used for instruction scheduling by a program considering the load on the bus between the arithmetic processing unit 1 and the MMU 25.

  In the above embodiment, the number of request requests issued for a load instruction (scalar) is predicted based on the most recent cache miss rate, but this is calculated in advance per instruction calculated based on experimental trials. The average request request issuance number can be read from the stored memory. In this case, the value stored in the memory may be fixed by factory setting, or may be variable by dip switch input or jumper plug setting.

  Further, by removing the reply receiving unit 43 and the end-time calculation control unit 47 from the above-described embodiment and adopting a configuration in which no subtraction is performed by the computing unit 48, the cumulative number of requests can be calculated.

  Note that the arithmetic processing apparatus 1 according to the embodiment of the present invention can be realized by using a normal computer system without using dedicated hardware. For example, an information processing apparatus that emulates the above-described processing is installed by installing the program in a storage unit from a medium (such as a CD-ROM) that stores the program for executing the above-described processing in a general-purpose computer. can do.

  Further, when the above-described functions are realized by sharing between an OS (Operating System) and an application, or by cooperation between the OS and the application, only a part other than the OS may be stored in the medium.

  It is also possible to superimpose a program on a carrier wave and distribute it via a communication network. For example, the program may be posted on a bulletin board (BBS, Bulletin Board System) on a communication network and distributed through the network. The program may be activated and executed in the same manner as other application programs under the control of the operating system, so that the above-described processing may be executed.

1 is a block diagram of an arithmetic processing device and peripheral devices according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a memory request management table in FIG. 1. It is a flowchart for demonstrating the registration process to the memory request management table which concerns on embodiment of this invention. It is a flowchart for demonstrating the deletion process from the memory request management table which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Arithmetic processing unit 11 Instruction fetch part 13 Instruction decoder 15 Read stage 17 Calculator 19 Write stage 21 Main memory part 23 Cache memory 25 Memory management unit (MMU)
29 Register Group 41 Cache Miss Rate Calculation Unit 42 Scalar Request Number Calculation Unit 43 Reply Reception Unit 46 Registration Time Calculation Control Unit 47 End Time Calculation Control Unit 48 Operation Unit 49 Request Counter 50 Operation Control Unit 51 Refresh Timing Control Unit 52 Delay Lock Loop (DLL) control unit 53 clock control unit 54 prefetch preload control unit 60 operation clock signal generation unit 61 memory clock signal generation unit 121 table management unit 127 memory request management table

Claims (10)

A control unit;
An information processing apparatus comprising a memory,
The controller is
An instruction decoder that extracts an opcode and an operand from the instruction;
Instruction type determining means for determining whether or not the operand fetched by the instruction decoder is an operand of an instruction that accesses the memory;
Addition value calculating means for calculating an expected value of the number of requests issued when accessing the memory by this instruction when the instruction type determining means determines that the operand is an operand of an instruction accessing the memory When,
Integrating means for integrating the values calculated by the added value calculating means;
An information processing apparatus comprising: The controller is
Subtract value calculation means for calculating the expected value calculated by the addition value calculation means as a subtraction value for the instruction that is the basis of this access after the access to the memory is completed,
The integration means integrates the value calculated by the addition value calculation means and the subtraction value calculation means;
The information processing apparatus according to claim 1. The memory is a memory for refreshing stored contents at a predetermined interval or shorter than the predetermined interval in order to continue storing information,
The controller is
Integrated value determining means for determining whether or not the value calculated by the integrating means is 0;
When the integrated value determining means determines that the value calculated by the integrating means is 0, a refresh instruction signal for refreshing the stored contents of the memory is output to the memory, and the value calculated by the integrating means is 0. Refresh instruction means for outputting a refresh instruction signal to the memory at the predetermined interval when it is determined that the stored contents of the memory are not,
Comprising
The information processing apparatus according to claim 1, wherein: The information processing apparatus operates in synchronization with a clock signal,
The control unit outputs a clock control signal for raising the frequency of the clock signal from a basic frequency when the integrated value determining unit determines that the value calculated by the integrating unit is 0, and the integrating unit Clock control means for outputting a clock control signal for returning the frequency of the clock signal to the fundamental frequency when it is determined that the calculated value is not 0;
The information processing apparatus according to claim 1, 2, or 3. The memory operates in synchronization with a memory clock signal,
When the integrated value determining means determines that the value calculated by the integrating means is 0, the control section outputs a memory clock control signal for reducing the frequency of the clock signal from a fundamental frequency, and the integrating means Comprising a memory clock control means for outputting a memory clock control signal for returning the frequency of the clock signal to the fundamental frequency when it is determined that the value calculated in step 1 is not 0;
The information processing apparatus according to claim 1, wherein:   The control unit includes request control means for changing a maximum number of memory access requests that can be simultaneously transmitted and received between the control unit and the memory according to the integrated value calculated by the integrated value calculating means. The information processing apparatus according to any one of claims 1 to 5. The information processing apparatus includes a cache memory,
The control unit comprises a miss rate calculation means for calculating a cache miss rate of the cache memory,
The instruction type determining means is further means for determining whether or not the operand fetched by the instruction decoder is a scalar type instruction,
The addition value calculating means is a means for calculating the expected value according to the cache miss rate calculated by the miss rate calculating unit when the instruction type determining unit determines that the operand is an operand of a scalar type instruction. thing,
The information processing apparatus according to any one of claims 1 to 6.   When the integrated value determining unit determines that the value calculated by the integrating unit is 0, the control unit performs readjustment of a delay lock loop of a memory bus connecting the control unit and the memory. A DLL control unit that outputs a DLL control signal to output the DLL signal at a predetermined interval when readjustment of the delay lock loop of the memory bus is performed when it is determined that the value calculated by the integration unit is not 0. The arithmetic processing apparatus according to claim 1, further comprising: An arithmetic processing unit that exchanges data with a memory via a memory bus,
An instruction decoder that extracts an opcode and an operand from the instruction;
Instruction type determining means for determining whether or not the operand fetched by the instruction decoder is an operand of an instruction that accesses the memory via the memory bus;
Addition value calculating means for calculating an expected value of the number of requests issued when accessing the memory by this instruction when the instruction type determining means determines that the operand is an operand of an instruction accessing the memory When,
Integrating means for integrating the values calculated by the added value calculating means;
An arithmetic processing apparatus comprising: An arithmetic processing unit that exchanges data with the memory via the memory bus
A decoding step for extracting an opcode and an operand from the instruction;
A determination step of determining whether or not the operand fetched in the decoding step is an operand of an instruction that accesses the memory via the memory bus;
An addition value calculating step of calculating an expected value of the number of requests issued when accessing the memory with this instruction when the determining step determines that the operand is an operand of the instruction accessing the memory;
An integration step of integrating the values calculated by the addition value calculation step;
A control step of optimizing the memory access of the arithmetic processing unit according to the value integrated in the integration step;
A memory access control method comprising:

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