JP2006284737A - Electrode driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a latch-type segment electrode drive circuit capable of avoiding malfunctions due to glitches. <P>SOLUTION: The segment electrode driving circuit is constituted of: a register part 52 for storing gradation data expressed by gray codes; a gray code counter 53 for increasing or decreasing a count value expressed by gray codes, in response to a clock signal and outputting the increased/decreased count value; a pulse width modulation circuit 54 for generating a pulse width modulation signal, on the basis of the count value supplied from the gray code counter 53, the gradation data converted into gray codes and stored in the register part 52 and a timing signal supplied from a controller in each one-horizontal period; and a drive circuit 55 for supplying a gradation signal of pulse width, corresponding to the gradation data, on the basis of the pulse-width modulation signal generated from the pulse width modulation circuit 54. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for generating a pulse width modulation signal in a driving circuit that supplies a gradation signal to a display device.

Conventionally, as a method for controlling the gradation (brightness / darkness) of pixels of a display device such as a passive matrix liquid crystal display device, it is applied to the segment electrode (signal electrode) corresponding to the brightness (brightness) to be displayed. There has been proposed a method (pulse width modulation method) for changing the pulse width of a gradation signal to be generated (see, for example, Patent Document 1).
In the pulse width modulation method, the voltage level of the gradation signal is constant. Therefore, the pulse width modulation method is superior to other methods (for example, a method of controlling light and darkness based on the amplitude of a gradation signal) in that it can be realized by a relatively simple circuit.

Various circuits have been proposed as a method for realizing a pulse width modulation type segment electrode driving circuit. For example, a method of decoding gradation data and selecting one signal from a plurality of signals having different pulse widths based on the decoded signal (hereinafter referred to as a decoder method) has been proposed.
Also, the segment electrode drive RS latch circuit is set at a specific timing to supply a signal to the segment electrode and start the counter, and the RS latch circuit is reset when the count value of the counter matches the gradation data Thus, a method of changing the pulse width (hereinafter referred to as a latch method) has been proposed.
FIG. 12 and FIG. 13 show a configuration example when the pulse width modulation circuit (which can set a 4-bit gradation) in the segment electrode driving circuit is realized by a decoder method and a latch method.

  The decoder-type circuit shown in FIG. 12 selects and outputs one signal among input pulses PLT0 to PLT15 having 16 pulse widths supplied from an external controller based on 4-bit gradation data DATA. To do. That is, the output of this circuit is a pulse width modulation signal capable of selecting 16 kinds of pulse widths defined by the gradation data.

  In the latch-type circuit shown in FIG. 13, the RS latch circuit is set to a logic value high by the horizontal synchronization signal. Thereafter, when the count value CNT (4 bits) supplied from the external counter matches the gradation data DATA (4 bits), the coincidence determination circuit resets the RS latch circuit to the logic value low. If the horizontal synchronization signal is supplied at the timing when the count value is 0, the output of the RS latch circuit becomes a pulse width modulation signal capable of selecting 16 kinds of pulse widths defined by the gradation data.

  By adopting such a pulse width modulation circuit, converting the pulse width modulation signal output from the pulse width modulation circuit into a voltage level suitable for driving a liquid crystal panel, and outputting it as a gradation signal, A pulse width modulation type segment electrode driving circuit can be realized.

By the way, in recent years when multi-gradation has progressed in order to improve image quality, it is necessary for the drive circuit to cope with multi-gradation.
When the decoder-type segment electrode drive circuit is multi-graded by 1 bit, the circuit scale of the decoder in FIG. 12 is doubled and the PLT signal is also doubled. For this reason, the circuit scale of the segment electrode drive circuit itself and the external controller increases about twice as much as 1-bit multi-gradation. Furthermore, when the number of gradations is increased, the circuit scale increases dramatically.

On the other hand, when the latch-type segment electrode drive circuit is multi-graded by 1 bit, the coincidence determination circuit in FIG. 13 is increased by 1 bit, and the count value CNT of the external binary counter and the gradation data DATA are changed to 5 bits. That's fine. For this reason, the increase in the circuit scale of the segment electrode drive circuit itself and the external controller is about several tens of gates at most for one-bit multi-gradation.
Thus, when multi-gradation is advanced, the latch-type segment electrode drive circuit is advantageous in that it can prevent an increase in circuit scale.
JP 2003-150121 A

However, in the latch-type segment electrode drive circuit, if each bit of the count value changes at the same time, an unexpected pulse called a glitch may occur in the input signal to the RS latch, resulting in malfunction.
FIG. 14 shows a specific example of a malfunction caused by a glitch when the gradation data is set to [0111 (binary)]. As shown in FIGS. 14B to 14E, when the count value is counted up by the binary code, there is a timing at which a plurality of bits change almost simultaneously. For example, in FIG. 14, at time T30, CNT0 and CNT1 change from logic high to low, and CNT2 changes from logic low to high.

  At this time, as shown in FIG. 14D, when the timing at which CNT2 changes is earlier than the other two bits that should be changed at the same time, the count value instantaneously becomes [0111 (binary)], and the gradation data Matches. For this reason, a pulse having an extremely narrow pulse width (referred to as a glitch) as shown in FIG. The glitch is input to the RS latch circuit and resets the RS latch circuit. As a result, as shown in FIG. 14G, the gradation signal falls at an unintended timing. That is, a gradation signal having an unintended pulse width is output. As a result, the pixels display light and dark colors different from those defined by the gradation data, so that the display quality deteriorates.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a latch-type segment electrode drive circuit capable of avoiding a malfunction due to a glitch.

  A segment electrode drive circuit according to the present invention is a segment electrode drive circuit that supplies a pulse width modulation signal having a pulse width corresponding to gradation data defining the gradation of a pixel of a display device to the segment electrode of the display device. A register unit that holds grayscale data expressed in gray code, a gray code counter that increases or decreases the count value expressed in gray code in response to a clock signal, and the gray code counter A pulse width for generating a pulse width modulation signal based on a supplied count value, grayscale data converted into a gray code held by the register unit, and a timing signal supplied from the controller every horizontal period Based on the pulse width modulation signal output from the modulation section and the pulse width modulation section, the pulse corresponding to the gradation data A drive circuit for supplying a gradation signal consists, characterized in that.

  The segment electrode driving circuit according to the present invention converts grayscale data represented by a binary code supplied from a controller outside the segment electrode into grayscale data represented by a gray code and supplies the grayscale data to the register unit. You may further have a code encoder.

  The pulse width modulation unit is set by a coincidence determination circuit that generates a reset signal when it is detected that the gradation data and the count value coincide with each other, and a timing signal supplied from the controller. You may comprise from the RS latch circuit reset by the reset signal supplied from a circuit.

  The timing signal supplied from the controller is preferably supplied when the count value of the Gray code counter is zero.

  In the segment electrode drive circuit according to the present invention, glitches are not generated by expressing grayscale data and count values with gray codes. For this reason, the segment electrode driving circuit according to the present invention can avoid malfunction due to glitches despite employing the latch system.

A case where the segment electrode driving circuit in the embodiment of the present invention is applied to a liquid crystal display device will be described as an example.
As shown in FIG. 1, the liquid crystal display device 1 of this embodiment includes a liquid crystal panel 2, a controller 3, a common driver 4, and a segment driver 5.

  The liquid crystal panel 2 is composed of a passive matrix type liquid crystal display panel, and has a matrix of transparent electrodes orthogonal to each other on opposing surfaces of two opposing glass plates. That is, one glass plate has a common electrode (scanning electrode) that receives a scanning signal supplied from a common driver (scanning electrode driving circuit) 4, and the other glass plate comes from a segment driver (signal electrode driving circuit) 5. It has a segment electrode (signal electrode) for receiving the supplied gradation signal. Liquid crystal is sealed between the two glass plates. Then, a pixel is formed at a position where the common electrode and the segment electrode intersect. The brightness of the pixel changes depending on the potential difference between the common electrode and the segment electrode. Therefore, a desired image can be displayed by appropriately controlling the potential difference between the common electrodes and the segment electrodes arranged in a matrix.

The controller 3 is a control circuit for controlling the display function of the liquid crystal display device 1. For example, the controller 3 may be composed of a dedicated logic circuit or a microcomputer.
For example, the controller 3 supplies the segment driver 5 with gradation data defining a gradation (brightness / darkness) of each pixel, a clock signal, a horizontal synchronization signal, a vertical synchronization signal, and the like.
Further, the controller 3 supplies the common driver 4 with a horizontal synchronization signal, a vertical synchronization signal, and the like that define the timing for changing the scanning signal.

  The common driver 4 supplies a scanning signal to the common electrode of the liquid crystal panel 2 based on the control of the controller 3. The scanning signal takes a selection voltage and a non-selection voltage. The pixels on the common electrode to which the selection voltage is supplied display light and dark defined by the gradation signal. On the other hand, no change in brightness due to the gradation signal occurs in the pixel on the common electrode supplied with the non-selection voltage. For example, as shown in FIG. 2, the common driver 4 includes a shift register 41, a level shifter 42, a drive circuit 43, and the like.

  In response to the vertical synchronization signal, the shift register 41 sets the logical value high only to the bit corresponding to the first pixel row (first common electrode). Then, in synchronization with the horizontal synchronizing signal, the bits for which the logic value is set are sequentially shifted to the second pixel row, the third pixel row,. A selection voltage is supplied through the level shifter 42 and the drive circuit 43 to the common electrode of the pixel row corresponding to the bit for which the logic value high is set.

Returning to FIG. 1, the segment driver 5 outputs a gradation signal for defining the brightness of the pixel based on the control of the controller 3. The brightness of the pixel can be controlled by both the amplitude of the gradation signal and the pulse width (that is, the application time), but the segment driver 5 controls the display gradation of the pixel by the pulse width.
As shown in FIG. 3, the segment driver 5 includes an input unit 51, a register unit 52, a Gray code counter 53, a pulse width modulation circuit 54, and a drive circuit 55.

As shown in FIG. 3, the input unit 51 includes a receiver circuit 511, a gray code encoder 512, and the like. The input unit 51 receives a clock signal, a horizontal synchronization signal, and the like supplied from the controller 3 and distributes them to each unit in the segment driver 5. Further, the input unit 51 converts the gradation data represented by the binary code supplied from the controller 3 into gradation data represented by the gray code by the gray code encoder 512 according to the truth table shown in FIG. Convert. The conversion method itself is arbitrary. For example, gradation data based on gray code may be stored at a position where the gradation data based on binary code in the memory is an address, the memory is addressed with input data, and the stored data may be read out.
Note that, for example, as shown in FIG. 4, the Gray code encoder 512 receives an input signal weighted by binary numbers, and outputs an exclusive OR of adjacent bits and an input signal of the most significant bit. Realized by a circuit. Only one gray code encoder 512 may be provided in the segment driver 5.

The register unit 52 holds gradation data represented by a Gray code supplied from the input unit 51. As shown in FIG. 3, the register unit 52 includes a first register 521 and a second register 522.
The first register 521 receives gradation data for one pixel row to be displayed in the next horizontal cycle from the controller 3 via the input unit 51 and sequentially stores it during one horizontal cycle. Then, the first register 521 supplies the stored gradation data for one pixel row to the second register 522 in response to the horizontal synchronization signal supplied from the controller 3.
The second register 522 receives the gradation data for one pixel row held by the first register 521 in response to the horizontal synchronization signal supplied from the controller 3 via the input unit 51, and receives the horizontal cycle of the horizontal cycle. Meanwhile, gradation data for one pixel row is supplied to the pulse width modulation circuit 54.

  The gray code counter 53 is a counter that increases a count value in response to a clock signal supplied from the controller 3 via the input unit 51. FIG. 6 is a time chart showing the operation of the 4-bit gray code counter 53. The output signals CNT1 to CNT4 of the gray code counter 53 change logical values in response to the clock signals, respectively, but a plurality of output signals do not change simultaneously. For example, only CNT1 changes at times T1, T5, etc., and only CNT2 changes at times T3, etc.

  Only one gray code counter 53 may be provided in the segment driver 5, and the count value CNT as an output signal may be distributed to the pulse width modulation circuit corresponding to each segment electrode. Thereby, an increase in circuit scale can be prevented.

  The pulse width modulation circuit 541 sets the output signal to a logical high value according to the horizontal synchronization signal, the grayscale data DATA represented by the gray code supplied from the register unit 52, and the count supplied from the gray code counter 53 When the value CNT matches, the output signal is changed to a logic low value. As shown in FIG. 8, when the horizontal synchronization signal is supplied at the timing when the count value CNT is 0, the output signal of the pulse width modulation circuit 54 is a pulse width modulation signal having a pulse width corresponding to the gradation data DATA. Become. The segment driver 5 controls the brightness of the pixels based on the pulse width of the pulse width modulation signal generated by the pulse width modulation circuit 54.

  The pulse width modulation circuit 54 includes, for example, a coincidence determination circuit 541 and an RS latch circuit 542 as shown in FIG.

The coincidence determination circuit 541 compares the gradation data DATA and the count value CNT of the gray code counter 53, and outputs a logical value high when the two coincide. The coincidence determination circuit 541 can be realized, for example, by combining AND circuits as shown in FIG. Only when the gradation data DATA and the count value CNT match for all the bits, the logic value high is output.
As described above, the count value CNT of the Gray code counter 53 does not change a plurality of bits at the same time, so that no glitch appears in the output of the coincidence determination circuit 541.

As shown in FIG. 10A, the RS latch circuit 542 includes two NOR circuits.
The RS latch circuit 542 operates according to the truth table shown in FIG. Specifically, the RS latch circuit 542 has a set terminal and a reset terminal as input terminals. Simultaneously inputting a logical high value to the set terminal and the reset terminal is prohibited. When a logic high is input to the set terminal, the output terminal outputs a logic high. When a logic high value is input to the reset terminal, the output terminal outputs a logic low value. Further, when a logic low is input to the set terminal and the reset terminal, the output terminal holds the previous state.

Hereinafter, the operation of the pulse width modulation circuit 54 will be described with reference to FIG. 8 showing a time chart when the set value of the gradation data is set to [1110] (that is, 11 in decimal) in gray code. explain.
First, the pulse width modulation circuit 54 sets the output to the logic value high when the horizontal synchronization signal is supplied from the controller 3 to the set terminal. It is assumed that the horizontal synchronization signal from the controller 3 is supplied at a timing when the count value CNT is 0.
Next, the coincidence determination circuit supplies the reset signal RST to the reset terminal of the RS latch circuit 542 at the timing when the count value CNT coincides with the gradation data DATA. As a result, the output of the pulse width modulation circuit 54 becomes a logic low value. Therefore, a pulse width modulation signal having a pulse width corresponding to the gradation data is obtained.

  The drive circuit 55 is a driver circuit that outputs a gradation signal supplied to the segment electrode of the liquid crystal panel 2 in response to the output signal of the pulse width modulation circuit 54. Specifically, the drive circuit 55 supplies a predetermined high level voltage to the segment electrode of the liquid crystal panel 2 when the output signal of the pulse width modulation circuit 54 is a logic high value, and the output signal of the pulse width modulation circuit 54 is a logic signal. When the value is low, a predetermined low level voltage is supplied to the segment electrode of the liquid crystal panel 2.

  The operation of the liquid crystal display device 1 configured as described above will be described with reference to a time chart shown in FIG. In FIG. 11, a period from T10 to T20 indicates one vertical cycle for displaying an image of one frame on the screen of the liquid crystal display device. Below, the operation | movement of each part of the liquid crystal display device 1 in 1 vertical period and the change of the screen display corresponding to the operation | movement are demonstrated.

One vertical cycle is started in synchronization with the rising edge (time T10) of the vertical synchronization signal (FIG. 11A).
In response to the vertical synchronizing signal and the horizontal synchronizing signal, the common driver 4 selects the scanning signal COM1 (FIG. 11C) to the common electrode corresponding to the first pixel row of the liquid crystal panel 2 as a selection voltage (in FIG. 11). Display as high level).

  At time T10, in response to the horizontal synchronization signal, the segment driver 5 sets the gradation signal (FIG. 11 (i)) supplied to the segment electrode to a high level voltage. When the count value CNT (FIG. 11 (h)) coincides with the gradation data DATA (FIG. 11 (g)) (time T10 '), the segment driver 5 sets the gradation signal to a low level voltage. That is, a gradation signal having a pulse width corresponding to the gradation data DATA is supplied to the segment electrode of the liquid crystal panel 2.

In FIG. 11, the gradation data DATA (FIG. 11 (g)) and the count value CNT (FIG. 11 (h)) are displayed in decimal numbers for easy understanding. Set or counted by.
In FIG. 11, the gradation data DATA and the gradation signal are only illustrated corresponding to one segment electrode, but actually, the gradation data corresponds to all the segment electrodes. DATA and gradation signals are supplied.

  By such an operation from time T10 to time T11, each pixel on the first pixel row displays light and dark corresponding to the pulse width of the gradation signal. On the other hand, no change in brightness occurs in the pixels other than the first pixel row.

  Next, at time T11, in response to the horizontal synchronization signal, the common driver 4 applies the scanning signal COM1 (FIG. 11C) to the common electrode corresponding to the first pixel row of the liquid crystal panel 2 as a non-selection voltage ( 11, the scanning signal COM <b> 2 (FIG. 11D) to the common electrode corresponding to the second pixel row is set to the selection voltage.

  At time T11, in response to the horizontal synchronization signal, the segment driver 5 sets the gradation signal (FIG. 11 (i)) supplied to the segment electrode to a high level voltage. When the count value CNT coincides with the gradation data DATA (time T11 '), the segment driver 5 sets the gradation signal to a low level voltage. That is, a gradation signal having a pulse width corresponding to the gradation data DATA is supplied to the segment electrode of the liquid crystal panel 2.

  By such an operation from time T11 to time T12, each pixel on the second pixel row displays light and dark corresponding to the pulse width of the gradation signal. On the other hand, no change in brightness occurs in pixels other than the second pixel row.

In the same manner, the desired brightness and darkness are sequentially displayed in the third pixel row, the fourth pixel row,. Then, at the time T1n, when the display of the nth pixel row, which is the last pixel row, is finished, a period during which display is not performed for a while (return line period) is entered.
Then, at time T20, when the vertical synchronization signal is supplied again, the horizontal cycle ends and the next horizontal cycle starts.

  As described above, the liquid crystal display device 1 displays an image of one frame by sequentially performing the display from the first pixel row to the Nth pixel row. And it becomes possible to display a desired image | video by updating an image for every horizontal period.

  The segment electrode drive circuit according to the present embodiment employs the Gray code counter 53 and the Gray code encoder 512, thereby avoiding the occurrence of glitches by the coincidence determination circuit. For this reason, malfunction caused by glitch does not occur, and as a result, it is possible to cause the display device to display high quality.

  In the above embodiment, the case where the Gray code counter 53 increases the count value in response to the clock signal has been described as an example. However, the Gray code counter 53 in the segment electrode driving circuit of the present invention responds to the clock signal. The count value may be decreased.

  In the above embodiment, the controller supplies gradation data expressed in binary code to the segment electrode driving circuit, and the gradation data is converted into gray code representation by the gray code encoder in the segment electrode driving circuit. Was described as an example. However, the segment electrode driving circuit according to the present invention is not limited to the above-described embodiment, and includes a segment electrode driving circuit having a configuration in which grayscale data represented by a Gray code is supplied from a controller.

  In the above-described embodiment, an example in which a so-called inverted gray code is used as the gray code is shown. However, the gray code is a generic name of a code having a property that only one bit is changed by adding one. The type of gray code is arbitrary.

  In the above embodiment, the case where the segment electrode driving circuit of the present invention is applied to a liquid crystal display device has been described as an example. However, the segment electrode driving circuit of the present invention is not limited to a liquid crystal display device, but an organic EL (electroluminescence). Sense) display and the like.

It is a block diagram which shows the structure of a liquid crystal display device. It is a block diagram which shows the structure of a common driver. It is a block diagram which shows the structure of a segment driver. It is a block diagram which shows the structure of a Gray code encoder. It is a truth table for demonstrating operation | movement of a Gray code encoder. It is a time chart which shows operation | movement of a gray code counter. It is a block diagram which shows the structure of a pulse width modulation circuit. It is a time chart which shows operation | movement of a pulse width modulation circuit. It is a block diagram which shows the structure of a coincidence determination circuit. (A) is a block diagram showing a configuration of an RS latch circuit. (B) is a truth table for explaining the operation of the RS latch circuit. It is a time chart for demonstrating the whole operation | movement of a liquid crystal display device. It is a block diagram which shows the structure of the pulse width modulation circuit of the conventional decoder system. It is a block diagram showing a configuration of a conventional latch-type pulse width modulation circuit. It is a time chart explaining the cause of occurrence of a glitch.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 2 ... Liquid crystal panel, 3 ... Controller, 4 ... Common driver, 5 ... Segment driver

Claims (4)

A segment electrode driving circuit for supplying a pulse width modulation signal having a pulse width corresponding to gradation data defining a gradation of a pixel of a display device to a segment electrode of the display device,
A register unit for holding gradation data expressed in gray code;
A gray code counter that increases or decreases the count value represented by the gray code in response to the clock signal, and
A pulse width modulation signal based on a count value supplied from the gray code counter, grayscale data converted into a gray code held by the register unit, and a timing signal supplied from the controller every horizontal period A pulse width modulation unit for generating
A driving circuit that supplies a gradation signal having a pulse width corresponding to gradation data based on a pulse width modulation signal output from the pulse width modulation unit;
A segment electrode driving circuit. A gray code encoder for converting grayscale data represented by a binary code supplied from an external controller into grayscale data represented by a gray code and supplying the grayscale data to the register unit;
The segment electrode drive circuit according to claim 1. The pulse width modulation unit is set by a coincidence determination circuit that generates a reset signal when it is detected that the gradation data and the count value coincide with each other, and a timing signal supplied from the controller. An RS latch circuit that is reset by a reset signal supplied from the circuit,
The segment electrode drive circuit according to claim 1. The timing signal supplied from the controller is supplied when the count value of the Gray code counter is zero.
The segment electrode drive circuit according to claim 3.

Images