JP2006284565A5 - - Google Patents
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- JP2006284565A5 JP2006284565A5 JP2006058820A JP2006058820A JP2006284565A5 JP 2006284565 A5 JP2006284565 A5 JP 2006284565A5 JP 2006058820 A JP2006058820 A JP 2006058820A JP 2006058820 A JP2006058820 A JP 2006058820A JP 2006284565 A5 JP2006284565 A5 JP 2006284565A5
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- characteristic evaluation
- thin film
- film transistor
- ring oscillator
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Claims (26)
性評価用素子が設けられ、前記閉ループ回路が設けられた領域の表面は絶縁膜で覆われて
いることを特徴とする素子基板。 A characteristic evaluation element having a closed loop circuit in which an antenna coil and a semiconductor element are electrically connected in series is provided, and a surface of the region in which the closed loop circuit is provided is covered with an insulating film. Element substrate to be used.
性評価用素子が設けられ、可撓性を有することを特徴とする素子基板。 An element substrate characterized by having a characteristic evaluation element having a closed loop circuit in which an antenna coil and a semiconductor element are electrically connected in series and having flexibility.
前記半導体素子はダイオード、トランジスタ、発光素子、抵抗素子、容量素子のいずれ
かであることを特徴とする素子基板。 In claim 1 or claim 2,
The element substrate, wherein the semiconductor element is any one of a diode, a transistor, a light emitting element, a resistance element, and a capacitor element.
路を有する特性評価用素子が設けられ、前記閉ループ回路が設けられた領域の表面は絶縁
膜で覆われていることを特徴とする素子基板。 An element for characteristic evaluation having a closed loop circuit in which an antenna coil, a capacitive element, and a semiconductor element are electrically connected in series is provided, and a surface of the region where the closed loop circuit is provided is covered with an insulating film An element substrate.
路を有する特性評価用素子が設けられ、可撓性を有することを特徴とする素子基板。 An element substrate characterized in that a characteristic evaluation element having a closed loop circuit in which an antenna coil, a capacitor element, and a semiconductor element are electrically connected in series is provided and has flexibility.
前記半導体素子はダイオード、トランジスタ、発光素子、抵抗素子のいずれかであるこ
とを特徴とする素子基板。 In claim 4 or claim 5,
The element substrate, wherein the semiconductor element is any one of a diode, a transistor, a light emitting element, and a resistance element.
評価用素子が設けられ、
前記電源回路は前記リングオシレータに電源電圧を供給する機能を有し、
前記アンテナコイルには、前記トランジスタを有し、前記リングオシレータの発振周波数で負荷変調が行われる回路が電気的に接続され、
前記電源回路、前記リングオシレータ、及び、前記トランジスタが設けられた領域の表
面は絶縁膜で覆われていることを特徴とする素子基板。 An element for characteristic evaluation having an antenna coil, a power supply circuit, a ring oscillator, and a transistor is provided.
The power supply circuit has a function of supplying a power supply voltage to the ring oscillator;
The antenna coil has the transistor, and is electrically connected to a circuit that performs load modulation at the oscillation frequency of the ring oscillator,
The element substrate, wherein the surface of the region where the power supply circuit, the ring oscillator, and the transistor are provided is covered with an insulating film.
評価用素子が設けられ、
前記電源回路は前記リングオシレータに電源電圧を供給する機能を有し、
前記アンテナコイルには、前記トランジスタを有し、前記リングオシレータの発振周波数で負荷変調が行われる回路が電気的に接続され、
可撓性を有することを特徴とする素子基板。 An element for characteristic evaluation having an antenna coil, a power supply circuit, a ring oscillator, and a transistor is provided.
The power supply circuit has a function of supplying a power supply voltage to the ring oscillator;
The antenna coil has the transistor, and is electrically connected to a circuit that performs load modulation at the oscillation frequency of the ring oscillator,
An element substrate having flexibility.
源電圧の供給を行う電極パッドとを有する特性評価用素子が設けられ、
前記アンテナコイルは、前記トランジスタを有し、前記リングオシレータの発振周波数で負荷変調が行われる回路が電気的に接続され、
前記電源回路、前記リングオシレータ、及び、前記トランジスタが設けられた領域の表
面は、前記電極パッドが設けられた領域を除いて絶縁膜で覆われていることを特徴とする素子基板。 A characteristic evaluation element having an antenna coil, a ring oscillator, a transistor, and an electrode pad for supplying a power supply voltage to the ring oscillator is provided.
The antenna coil includes the transistor, and a circuit that performs load modulation at an oscillation frequency of the ring oscillator is electrically connected;
The element substrate, wherein the surface of the region where the power supply circuit, the ring oscillator, and the transistor are provided is covered with an insulating film except for the region where the electrode pad is provided .
源電圧の供給を行う電極パッドとを有する特性評価用素子が設けられ、
前記アンテナコイルは、前記トランジスタを有し、前記リングオシレータの発振周波数で負荷変調が行われる回路が電気的に接続され、
可撓性を有することを特徴とする素子基板。 A characteristic evaluation element having an antenna coil, a ring oscillator, a transistor, and an electrode pad for supplying a power supply voltage to the ring oscillator is provided.
The antenna coil includes the transistor, and a circuit that performs load modulation at an oscillation frequency of the ring oscillator is electrically connected;
An element substrate having flexibility.
前記トランジスタは負荷変調を行う機能を有することを特徴とする素子基板。 In any one of Claims 7 to 10,
The element substrate having a function of performing load modulation.
前記素子基板で消費される電力を測定することで前記半導体素子の特性を評価すること
を特徴とする検査方法。 Radiating electromagnetic waves to the element substrate according to any one of claims 1 to 6,
An inspection method characterized by evaluating characteristics of the semiconductor element by measuring electric power consumed by the element substrate.
ることができる測定装置を用いて、前記電磁波を放射し、
前記アンテナに生じる電流又は電圧を測定することで前記半導体素子の特性を評価することを特徴とする検査方法。 The element substrate according to any one of claims 1 to 6, using a measuring device capable to <br/> Rukoto radiate electromagnetic waves from the antenna, and radiate the electromagnetic wave,
An inspection method for evaluating characteristics of the semiconductor element by measuring a current or a voltage generated in the antenna.
能な測定装置を用いて、電磁波を放射するステップと、
磁界プローバにより前記素子基板に吸収される電力を測定するステップと、
により前記半導体素子の特性を評価することを特徴とする検査方法。 The element substrate according to any one of claims 1 to 6, an electromagnetic wave with a release morphism friendly <br/> ability measurement apparatus from the antenna, the steps of emitting an electromagnetic wave,
Measuring power absorbed by the element substrate by a magnetic field prober;
An inspection method characterized by evaluating the characteristics of the semiconductor element.
けられた半導体素子の静特性を非接触で評価することを特徴とする検査方法。 An inspection method, wherein the static characteristics of a semiconductor element provided on the element substrate are evaluated in a non-contact manner using the inspection method according to claim 12.
能な測定装置を用いて、電磁波を放射するステップと、
前記アンテナに生じる電流又は電圧を測定するステップと、
により、前記リングオシレータの特性を評価することを特徴とする検査方法。 The element substrate according to any one of claims 7 to 9, an electromagnetic wave with a release morphism friendly <br/> ability measurement apparatus from the antenna, the steps of emitting an electromagnetic wave,
Measuring the current or voltage generated in the antenna;
An inspection method characterized by evaluating characteristics of the ring oscillator.
能な測定装置を用いて、電磁波を放射するステップと、
磁界プローバにより前記素子基板に吸収される電力を測定するステップと、
により、前記リングオシレータの特性を評価することを特徴とする検査方法。 The element substrate according to any one of claims 7 to 9, an electromagnetic wave with a release morphism friendly <br/> ability measurement apparatus from the antenna, the steps of emitting an electromagnetic wave,
Measuring power absorbed by the element substrate by a magnetic field prober;
An inspection method characterized by evaluating characteristics of the ring oscillator.
能な測定装置を用いて、電磁波を放射するステップと、
前記リングオシレータから放射された電磁波を測定するステップと、
により、前記リングオシレータの特性を評価する検査方法。 The element substrate according to any one of claims 7 to 9, an electromagnetic wave with a release morphism friendly <br/> ability measurement apparatus from the antenna, the steps of emitting an electromagnetic wave,
Measuring a morphism electromagnetic wave release from the ring oscillator,
An inspection method for evaluating characteristics of the ring oscillator.
けられた半導体素子の動特性を非接触で評価することを特徴とする検査方法。 19. An inspection method using the inspection method according to claim 16, wherein the dynamic characteristics of the semiconductor element provided on the element substrate is evaluated in a non-contact manner.
接触で検査する方法を有することを特徴とする半導体装置の作製方法。 A method for manufacturing a semiconductor device, comprising: a method for inspecting the element substrate in a non-contact manner using the inspection method according to claim 12.
膜トランジスタを形成し、
前記特性評価用素子に対して接触式で検査を行い、
前記第１の基板から前記特性評価用素子及び前記薄膜トランジスタを剥離し、
前記特性評価用素子及び前記薄膜トランジスタを第２の基板上に転置し、
前記第２の基板上に転置された特性評価用素子に対して非接触式で検査を行うことによ
って前記薄膜トランジスタの特性を評価し、
前記薄膜トランジスタの特性が許容範囲を満たした前記第２の基板を切断することを特
徴とする半導体装置の作製方法。 Forming a characteristic evaluation element having a first semiconductor layer and a thin film transistor having a second semiconductor layer on a first substrate;
Perform contact inspection on the element for characteristic evaluation,
Peeling the element for characteristic evaluation and the thin film transistor from the first substrate;
Transferring the element for characteristic evaluation and the thin film transistor on a second substrate;
Evaluating the characteristics of the thin film transistor by performing a non-contact type inspection on the element for characteristic evaluation transferred on the second substrate;
A method for manufacturing a semiconductor device, comprising cutting the second substrate in which characteristics of the thin film transistor satisfy an allowable range.
膜トランジスタを形成し、
前記特性評価用素子に対して接触式で検査を行い、
前記第１の基板から前記特性評価用素子及び前記薄膜トランジスタを剥離し、
前記特性評価用素子及び前記薄膜トランジスタを第２の基板上に転置し、
前記第２の基板上に転置された特性評価用素子に対して非接触式で検査を行うことによ
って前記薄膜トランジスタの特性を評価し、
前記薄膜トランジスタの特性が許容範囲を満たした前記第２の基板を切断し、
前記切断された第２の基板上の薄膜トランジスタを検査することを特徴とする半導体装
置の作製方法。 Forming a characteristic evaluation element having a first semiconductor layer and a thin film transistor having a second semiconductor layer on a first substrate;
Perform contact inspection on the element for characteristic evaluation,
Peeling the element for characteristic evaluation and the thin film transistor from the first substrate;
Transferring the element for characteristic evaluation and the thin film transistor on a second substrate;
Evaluating the characteristics of the thin film transistor by performing a non-contact type inspection on the element for characteristic evaluation transferred on the second substrate;
Cutting the second substrate in which the characteristics of the thin film transistor satisfy an allowable range;
A method for manufacturing a semiconductor device, comprising: inspecting a thin film transistor on the cut second substrate.
膜トランジスタを形成し、
前記特性評価用素子に対して接触式で検査を行い、
前記接触式の検査によって、前記特性評価用素子の電圧−電流特性を求め、
前記第１の基板から前記特性評価用素子及び前記薄膜トランジスタを剥離し、
前記特性評価用素子及び前記薄膜トランジスタを第２の基板上に転置し、
前記第２の基板上に転置された特性評価用素子に対して非接触式で検査を行うことによ
って前記薄膜トランジスタの特性を評価し、
前記薄膜トランジスタの特性が、前記電圧−電流特性の許容範囲を満たした前記第２の
基板を切断することを特徴とする半導体装置の作製方法。 Forming a characteristic evaluation element having a first semiconductor layer and a thin film transistor having a second semiconductor layer on a first substrate;
Perform contact inspection on the element for characteristic evaluation,
By the contact type inspection, the voltage-current characteristic of the element for characteristic evaluation is obtained,
Peeling the element for characteristic evaluation and the thin film transistor from the first substrate;
Transferring the element for characteristic evaluation and the thin film transistor on a second substrate;
Evaluating the characteristics of the thin film transistor by performing a non-contact type inspection on the element for characteristic evaluation transferred on the second substrate;
A method for manufacturing a semiconductor device, comprising: cutting the second substrate in which characteristics of the thin film transistor satisfy an allowable range of the voltage-current characteristics.
膜トランジスタを形成し、
前記特性評価用素子に対して接触式で検査を行い、
前記接触式の検査によって、前記特性評価用素子の電圧−電流特性を求め、
前記第１の基板から前記特性評価用素子及び前記薄膜トランジスタを剥離し、
前記特性評価用素子及び前記薄膜トランジスタを第２の基板上に転置し、
前記第２の基板上に転置された特性評価用素子に対して非接触式で検査を行うことによ
って前記薄膜トランジスタの特性を評価し、
前記薄膜トランジスタの特性が、前記電圧−電流特性の許容範囲を満たした前記第２の
基板を切断し、
前記切断された第２の基板上の薄膜トランジスタを検査することを特徴とする半導体装
置の作製方法。 Forming a characteristic evaluation element having a first semiconductor layer and a thin film transistor having a second semiconductor layer on a first substrate;
Perform contact inspection on the element for characteristic evaluation,
By the contact type inspection, the voltage-current characteristic of the element for characteristic evaluation is obtained,
Peeling the element for characteristic evaluation and the thin film transistor from the first substrate;
Transferring the element for characteristic evaluation and the thin film transistor on a second substrate;
Evaluating the characteristics of the thin film transistor by performing a non-contact type inspection on the element for characteristic evaluation transferred on the second substrate;
Cutting the second substrate where the characteristics of the thin film transistor satisfy the allowable range of the voltage-current characteristics;
A method for manufacturing a semiconductor device, comprising: inspecting a thin film transistor on the cut second substrate.
前記第１の半導体層と、前記第２の半導体層とは同一工程で前記第１の基板上に形成す
ることを特徴とする半導体装置の作製方法。 In any one of Claims 21 to 24,
The method for manufacturing a semiconductor device, wherein the first semiconductor layer and the second semiconductor layer are formed over the first substrate in the same step.
前記第２の基板は可撓性を有することを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the second substrate is flexible.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006058820A JP4883679B2 (en) | 2005-03-07 | 2006-03-06 | Element substrate, inspection method, and manufacturing method of semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005061717 | 2005-03-07 | ||
| JP2005061717 | 2005-03-07 | ||
| JP2006058820A JP4883679B2 (en) | 2005-03-07 | 2006-03-06 | Element substrate, inspection method, and manufacturing method of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006284565A JP2006284565A (en) | 2006-10-19 |
| JP2006284565A5 true JP2006284565A5 (en) | 2009-04-16 |
| JP4883679B2 JP4883679B2 (en) | 2012-02-22 |
Family
ID=37406628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006058820A Expired - Fee Related JP4883679B2 (en) | 2005-03-07 | 2006-03-06 | Element substrate, inspection method, and manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4883679B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7808253B2 (en) | 2005-12-02 | 2010-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Test method of microstructure body and micromachine |
| JP2007175861A (en) * | 2005-12-02 | 2007-07-12 | Semiconductor Energy Lab Co Ltd | Inspection method for micro-structure and micro-machine |
| JP2016180673A (en) * | 2015-03-24 | 2016-10-13 | 株式会社デンソー | Semiconductor integrated circuit and test system therefor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08334541A (en) * | 1995-06-05 | 1996-12-17 | Mitsubishi Electric Corp | Current detector and method for detecting contact part at printed-wiring board utilizing it |
| CA2308820A1 (en) * | 2000-05-15 | 2001-11-15 | The Governors Of The University Of Alberta | Wireless radio frequency technique design and method for testing of integrated circuits and wafers |
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2006
- 2006-03-06 JP JP2006058820A patent/JP4883679B2/en not_active Expired - Fee Related
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