JP2006279647A - Timing signal transfer error correcting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing signal transfer error correcting method capable of inspecting a received count value, so as not to use the erroneous count value for the timing signal. <P>SOLUTION: The count value (a) received at present is compared with an inner count value (c) which is derived from the count value received in the past and expected to be received at present by the timing signal transfer error correcting method (S13, S14). When both the count values are not the same in the comparison result, it is regarded that the received count value is changed into an incorrect count value by receiving the influence of a noise, etc., in transferring, so that the inner count value is used in place of the received count value till the inner count value continuous usage limit times (d) is reached since the inner count value indicates the appropriate count value (S21-S24). Thus, even when an error occurs in transferring the timing signal due to the temporary noise, etc., in transferring, correction can be performed. Consequently, the correct timing signal transferring is performed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a timing signal transfer error correction method, and more particularly, to a timing signal transfer error correction method on the receiving side of a timing signal transfer system that uses a count value incremented at a constant time interval to obtain a timing signal.

  A timing signal is used between each card or various functional units used in a radio base station apparatus or the like in order to synchronize timing of various processing operations. For example, in the timing signal transfer system of FIG. 3, the counter unit 111 of the timing signal transmission device 110 outputs a count value (for example, 10 bits = 0 to 1023) incremented at a constant time interval, and the transmission unit 112 Transfer this. The receiving unit 121 of the timing signal receiving device 120 receives the transferred count value and sends it to each subsequent unit.

  In this case, as shown in FIG. 4, the receiving unit 121 includes an AND circuit AND, a shift register including flip-flops F0 to F9, and an output circuit RG. The operation of the receiving unit 121 is illustrated in FIG. Yes. That is, since the AND circuit AND receives the transfer clock signal CL and the transfer enable signal EN, the flip-flops F0 to F9 transfer data serially transferred in order from the MSB (D9) in synchronization with these signals. DT is taken in and shifted and output from the output circuit RG as 10-bit data.

  As described above, when 10-bit data is normally output from the output circuit RG, the 10-bit data D9 to D0 are sequentially arranged as in DTA of FIG. Under the influence, it may become like DTB of FIG. In other words, noise enters when D5 (the sixth bit from the lower 10 bits) is transferred, and D5 is input twice, and data D9 is finally pushed out of the shift register, so that a correct timing signal cannot be obtained.

  However, in the conventional timing signal transfer system described above, the received count value is not verified, and therefore there is a problem in that a correct timing signal cannot be obtained if it is affected by noise or the like during transfer of the count value. .

  The present invention has been made to solve the above-described problems, and even if a wrong count value is temporarily received due to the influence of noise or the like during transfer of the count value, the received count value is It is an object of the present invention to provide a timing signal transfer error correction method that can avoid using an incorrect count value for a timing signal by verifying the above.

  In order to solve the above-described problems, a timing signal transfer error correction method according to the present invention is a timing signal transfer error on the receiving side of a timing signal transfer system that receives and receives a count value incremented at a constant time interval to obtain a timing signal. A correction method, in which the currently received count value is compared with the internal count value expected to be received currently derived from the previously received count value, and as a result of the comparison, the count values are not the same Until the preset internal count value is reached, the internal count value is used as a timing signal instead of the reception count value.

  According to such a configuration, when a new count value is received, a comparison is made between the currently received count value and the internal count value expected to be received currently derived from the previously received count value. If both are the same as a result of the comparison, the received count value is used as a timing signal, and the internal count value continuous use limit number is reset. If the comparison shows that the two are not the same, it is assumed that the received count value has changed to an incorrect count value due to the effects of noise during transfer, and the internal count value is received from the past count value. Since the count value is supposed to be the count value, the internal count value is used instead of the reception count value until the internal count value continuous use limit number is reached. However, when the internal count value continuous use limit number is reached, the reception count value is considered to be correct, and the timing signal is adjusted to the reception count value.

  As described in detail above, according to the present invention, when a count value is newly received, the currently received count value and the internal count value expected to be received currently derived from the count value received in the past, Compare. If the comparison shows that the two are not the same, it is assumed that the received count value has changed to an incorrect count value due to the effects of noise during transfer, and the internal count value is received from the past count value. Since the count value that should be as the count value is shown, by using the internal count value instead of the reception count value until the internal count value continuous use limit number is reached, due to temporary noise during transfer, etc. Even if a timing signal transfer error occurs, correction is possible, and therefore correct timing signal transfer can be performed.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a timing signal transfer system to which the timing signal transfer error correction method of the present invention is applied, and FIG. 2 is for explaining each step of the embodiment of the timing signal transfer error correction method of the present invention. It is a flowchart of. A count value incremented at a constant time interval is transferred as a timing signal between each card or various functional units used in a radio base station apparatus or the like.

  In the timing signal transmitter 10, the counter unit 11 increments the count value at a constant time interval. The transmission unit 12 outputs the incremented count value of the counter unit 11 as a timing signal. In the timing signal receiving device 20, the receiving unit 21 receives the timing signal output from the timing signal transmitting device 10. The count value verification unit 22 verifies whether or not there is an error in the count value of the timing signal received by the reception unit 21, corrects if there is an error, and sends a timing signal based on the correct count value to each subsequent unit. provide.

  Next, the operation of the timing signal receiving apparatus 20 will be described with reference to FIG. The receiving unit 21 of the timing signal receiving apparatus 20 receives a timing signal including a count value (for example, 10 bits = 0 to 1023) from the timing signal transmitting apparatus 10. The count value verification unit 22 receives the timing signal from the reception unit 21 (S11), and detects the current reception count value a (S12). A count value difference b = a−e between the current reception count value a and the previous count value e after the previous verification is calculated, and it is determined whether or not b <0. If b <0 is not satisfied, 1024 is added to b if b <0 (b = b + 1024) (S13).

  After the process of step S13 is completed, it is determined whether or not b = 1 (S14). If it is determined in step S14 that b = 1, the count value difference b is normal and the sent count value is normally incremented by “1”. What is necessary is just to use as a timing signal. Therefore, without using the count value of the internal counter (internal count value c), the continuous count d of the internal count value is reset to d = 0 (S15). Therefore, the current reception count value a is stored in the output register and output as a timing signal, and the current reception count value a is replaced with the previous count value e to be used next time (S16), and the current count value verification is terminated.

  If it is determined in step S14 that b is not 1, the current received value count value a is regarded as incorrect, and 1 is added to the previous count value e to obtain the internal count value c (c = e + 1). In this case, when the internal count value c is c ≧ 1024, the count value c is set to c = c−1024 (S21). Next, the internal count value continuous use count d is incremented to set d = d + 1, and it is determined whether the incremented d is “4”. If it is “4”, it is replaced with “3” (S22). .

  It is determined whether d <3 for the internal count value continuous use count d (S23). If d <3, the current reception count value a is replaced with the internal count value c (S24), and the process proceeds to step S16. Therefore, in this case, in step S16, the internal count value c is regarded as the current count value a and is set as the previous count value e. If d <3 is not satisfied in step S23, the current reception count value a is regarded as incorrect in step S21, and the number of times the internal count value has been used has reached the internal count value continuous use limit number (three times). Therefore, the current reception count value a is more correct than the internal count value, and the process proceeds to step S16. The current reception count value a is set to be the previous count value e in the next verification. The verification process ends and the process proceeds to the next timing signal verification process.

1 is a block diagram showing a timing signal transfer system to which a timing signal transfer error correction method of the present invention is applied. FIG. It is a flowchart for demonstrating each step of embodiment of the timing signal transmission error correction method of this invention. It is a block diagram which shows the prior art example of a timing signal transfer system. It is a circuit diagram for demonstrating the receiving part of FIG. 6 is a timing chart for explaining the operation of the receiving unit in FIG. 4. FIG. 5 is a diagram for explaining a malfunction that occurs in the receiving unit of FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Timing signal transmitter, 11 Counter part, 12 Transmitter, 20 Timing signal receiver, 21 Receiving part, 22 Count value verification part

Claims (1)

A timing signal transfer error correction method on the receiving side of a timing signal transfer system that receives and sends a count value that is incremented at a constant time interval as a timing signal,
A comparison is made between the count value currently received and the internal count value expected to be received currently derived from the count values received in the past, and if the count values are not the same as a result of the comparison, the preset internal count A timing signal transfer error correction method, wherein an internal count value is used as a timing signal instead of a reception count value until the value continuous use limit number is reached.

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