JP2006274355A - Plating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plating method for improving patterning accuracy. <P>SOLUTION: The plating method includes forming a surface active agent layer, a catalyst layer and a metallic layer on at least first and second pattern regions 12 and 14 on the same surface of a substrate 10. The plating method specifically comprises the steps of: forming a pattern of a first surface-active agent layer 20 on the first pattern region 12 by irradiation with light; and forming a pattern of a second surface-active agent layer 60 on the second pattern region 14 by irradiation with light. The light irradiation condition in the step of forming the first surface-active agent layer 10 differs from that in the step of forming the second surface-active agent layer 60. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a plating method.

  As a method for forming an electrode pattern, a subtractive method and an additive method are known. In the subtractive method, a metal layer is formed on the entire surface of the substrate, a photoresist is patterned on the metal layer, and the metal layer is etched using the photoresist as a mask. In the additive method, a photoresist is formed by patterning on a substrate, and a metal layer is deposited by plating on the opening of the photoresist.

According to these methods, since the photoresist is used, not only the manufacturing process becomes complicated, but also the consumption of resources and materials becomes a problem. In addition, the optimum exposure condition may be different between a rough area and a fine area. Even in such a case, patterning with high accuracy is required.
JP-A-8-64934

  One of the objects of the present invention is to provide a plating method capable of improving patterning accuracy.

(1) The plating method according to the present invention comprises:
Forming a surfactant layer, a catalyst layer and a metal layer above at least the first and second pattern regions on the same side of the substrate;
Above the first pattern region, a first surfactant layer is formed by patterning by light irradiation,
Above the second pattern area, a second surfactant layer is formed by patterning by light irradiation,
The light irradiation conditions when forming the first surfactant layer are different from the light irradiation conditions when forming the second surfactant layer. According to the present invention, it is possible to optimize light irradiation conditions for each of the first and second surfactant layers. Therefore, the pattern accuracy can be improved. In the present invention, B is provided above a specific A when B is provided directly on A and when B is provided on A via another member. And. The same applies to the following inventions.
(2) In this plating method,
The light irradiation time when forming the first surfactant layer may be different from the light irradiation time when forming the second surfactant layer.
(3) In this plating method,
The intensity of light when forming the first surfactant layer may be different from the intensity of light when forming the second surfactant layer.
(4) In this plating method,
The first and second surfactant layers may be made of a cationic surfactant.
(5) In this plating method,
The first pattern region may be connected to the second pattern region.
(6) In this plating method,
The first pattern region may be separated from the second pattern region.
(7) In this plating method,
The second pattern area may be a coarser pattern than the first pattern area.
(8) In this plating method,
The minimum line width of the second pattern region may be larger than the maximum line width of the first pattern region.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIGS. 1-9 is a figure which shows the plating method which concerns on the 1st Embodiment of this invention. In the present embodiment, a metal layer (electrode pattern) is formed on the substrate by an electroless plating method.

  (1) As shown in FIG. 1, a substrate 10 is prepared. The substrate 10 may be an organic substrate (for example, a plastic material or a resin substrate) or an inorganic substrate (for example, quartz glass, a silicon wafer, or an oxide layer). Examples of the plastic material include polyimide, polyethylene terephthalate, polycarbonate, polyphenylene sulfide, and polyethylene terephthalate. The substrate 10 includes not only a single layer but also a multilayer substrate in which at least one insulating layer is formed on a base substrate. In this embodiment, a metal layer is formed over the substrate 10. Specifically, a metal layer is formed on at least the first and second pattern regions 12 and 14 on the same surface (outermost surface) of the substrate 10. The first and second pattern areas 12 and 14 are areas arranged in the same layer.

  The first pattern area 12 may have a plurality of independent areas, or may be an integral area. The second pattern region 14 may have a plurality of independent regions, or may be an integrated region. The first pattern region 12 may be connected to the second pattern region 14. Alternatively, the first pattern region 12 may be separated from the second pattern region. The second pattern region 14 has a pattern shape different from that of the first pattern region 12. For example, the second pattern region 14 may be a coarser pattern than the first pattern region 12. A rough pattern means that the line width (the width in the direction intersecting the extending direction when extending in a predetermined direction) and the space (or pitch) between the lines are large. For example, the minimum line width of the second pattern region 14 may be larger than the maximum line width of the first pattern region 12. The minimum width of the line of the second pattern region 14 (or the maximum width of the line of the first pattern region 12) may be, for example, 20 to 100 μm. In this embodiment, it is extremely effective when a fine pattern region (for example, the first region 12) and a rough pattern region (for example, the second region 14) are mixed on the same surface of the substrate 10 as described above. .

  First, the substrate 10 is cleaned. For cleaning the substrate 10, either dry cleaning or wet cleaning may be applied. Specifically, for example, using a vacuum ultraviolet lamp (wavelength 172 nm, output 10 mW, distance between samples 1 mm), irradiation with vacuum ultraviolet rays can be performed for 30 seconds to 900 seconds in a nitrogen atmosphere. The wet cleaning can be performed, for example, by immersing the substrate 10 in ozone water (ozone concentration 10 ppm to 20 ppm) at room temperature for about 5 to 30 minutes. By cleaning the substrate 10, dirt such as oil and fat adhering to the surface of the substrate 10 can be removed. Further, the surface of the substrate 10 can be changed from water-repellent to hydrophilic. Moreover, if the surface potential in the liquid of the substrate 10 is a negative potential, a uniform negative potential surface can be formed by cleaning the substrate 10.

  (2) Next, as shown in FIGS. 2 and 3, the first surfactant layer 20 is formed by patterning on the first pattern region 12 of the substrate 10. For example, the first surfactant layer 20 can be formed on the first pattern region 12 by patterning by light irradiation.

  Specifically, for example, the substrate 10 is immersed in a surfactant solution containing a surfactant component, and the first surfactant layer 20a is formed on the entire surface of the substrate 10 as shown in FIG. As the first surfactant layer 20, for example, a cationic surfactant (cationic surfactant and one having properties equivalent thereto) can be used. According to this, when the surface potential in the liquid of the substrate 10 is a negative potential, a cationic system showing a positive potential can be used to clarify the potential contrast and selectively adsorb a catalyst layer described later. it can. Examples of the surfactant solution include a solution of a water-soluble surfactant containing an aminosilane-based component (FPD conditioner manufactured by Technique Japan Co., Ltd.), an alkylammonium-based solution (for example, cetyltrimethylammonium chloride, etc.), and the like. Can be used. The immersion time can be set to about 1 minute to 3 minutes, for example.

  Next, the substrate 10 is taken out from the surfactant solution and washed with ultrapure water. Thereafter, the substrate 10 is naturally dried at room temperature, for example, or sprayed with compressed air to remove water droplets, and then left in an oven at 90 ° C. to 120 ° C. for about 3 hours to dry.

  Then, as shown in FIG. 3, the first surfactant layer 20 a is patterned to form the first surfactant layer 20 on the first pattern region 12. In other words, the surfactant layer 20a on the region other than the first pattern region 12 of the substrate 10 is photolyzed and removed by patterning.

  As the light 30, for example, vacuum ultraviolet (VUV) can be used. By setting the wavelength of the light 30 to 170 nm to 260 nm, for example, an interatomic bond (for example, C—C, C═C, C—H, C—F, C—Cl, C—O, C—N, C = O, O = O, OH, HF, H-Cl, NH, etc.). Thereby, the 1st surfactant layer 20a can be photodegraded. Further, by using the light 30 in this wavelength band, a facility such as a yellow room becomes unnecessary, and a series of steps according to the present embodiment can be performed under a white lamp, for example.

  Specifically, the irradiation with the light 30 can be performed, for example, using a vacuum ultraviolet lamp (wavelength 172 nm, output 10 mW, distance between samples 1 mm) as the light source 32 in a nitrogen atmosphere for 5 minutes to 30 minutes. The light source 32 may be, for example, an excimer lamp in which Xe gas is sealed. The wavelength of the light 30 is not particularly limited as long as it can photodecompose the first surfactant layer 20a.

  The light 30 is applied to the substrate 10 through a mask 34 (for example, a photomask). Specifically, a mask 34 is disposed between the light source 32 and the substrate 10, and the light 30 is transmitted through a region other than the light shielding portion 36 (for example, a metal pattern portion such as chromium) of the mask 34. In the present embodiment, since the first surfactant layer 20 is formed on the first pattern region 12, the light 30 is transmitted to regions other than the first pattern region 12. That is, the light shielding portion 36 has a pattern shape that is plane-symmetric with the first pattern region 12. The mask 34 may be disposed in contact with the substrate 10. Further, it is preferable to perform the light irradiation treatment in a nitrogen atmosphere because the light 30 hardly attenuates.

  Thus, the first surfactant layer 20 can be formed by patterning on the first pattern region 12. After forming the first surfactant layer 20, the substrate 10 can be cleaned as necessary. The cleaning method may be wet cleaning (for example, a shower method or an immersion method), or may be dry cleaning. By performing the cleaning process, the residue of the surfactant layer other than the first pattern region 12 can be reliably removed.

  (4) Next, as shown in FIG. 4, a first catalyst layer 40 is formed on the first surfactant layer 20. Specifically, the substrate 10 is immersed in a catalyst solution containing a catalyst component. Thereby, the catalyst can be selectively adsorbed only on the first surfactant layer 20, and the first catalyst layer 40 can be formed only on the first surfactant layer 20.

  When a cationic type is used as the first surfactant layer 20, a catalyst having a negative potential in liquid can be selected as the catalyst. The first catalyst layer 40 induces the deposition of the first metal layer 50 in the electroless plating solution, and can be made of, for example, palladium. When the amount of the catalyst adsorbed on the first surfactant layer 20 is increased, the amount of the first metal layer 50 deposited on the first catalyst layer 40 is increased (the deposition speed is increased). The thickness of the first metal layer 50 can be controlled by adjusting the amount. Examples of the catalyst solution include a tin-palladium colloid catalyst solution, but the catalyst solution is not limited thereto, and can be freely selected according to the material of the first metal layer 50. In addition, when the board | substrate 10 is immersed in the tin- palladium colloid catalyst liquid, the board | substrate 10 can be immersed in borofluoric-acid aqueous solution for catalyst activation. In this way, the colloidal tin particles can be removed and only palladium can be adsorbed on the first surfactant layer 20.

  (5) Next, as shown in FIG. 5, a first metal layer 50 is deposited on the first catalyst layer 40. As described above, since the first catalyst layer 40 is formed only in the first pattern region 12, the first metal layer 50 can be formed only in the first pattern region 12. The thickness of the first metal layer 50 may be about 50% to 80% of the final thickness.

  Specifically, the first metal layer 50 can be deposited on the first catalyst layer 40 by immersing the substrate 10 in an electroless plating solution. The case where a nickel layer is deposited as the first metal layer 50 will be described. As an electroless plating solution, nickel sulfate hexahydrate is mainly used and sodium hypophosphite is included as a reducing agent. Can do. For example, a nickel layer having a thickness of 0.05 μm to 0.08 μm can be formed by immersing the substrate 10 in such an electroless plating solution (temperature 80 ° C.) for about 1 minute. Alternatively, an electroless plating solution containing nickel chloride hexahydrate as a main component and sodium hypophosphite as a reducing agent can be used. For example, a nickel layer having a thickness of 0.05 μm to 0.08 μm can be formed by immersing the substrate 10 in such an electroless plating solution (temperature 60 ° C.) for about 1 minute. The material of the first metal layer 50 is not limited, and can be formed from, for example, platinum (Pt), copper (Cu), gold (Au), or the like.

  In this way, the first metal layer 50 can be formed on the first pattern region 12 of the substrate 10.

  (6) Next, as shown in FIGS. 6 and 7, a second surfactant layer 60 is formed by patterning on the second pattern region 14 of the substrate 10. For example, the second surfactant layer 60 can be formed on the second pattern region 14 by patterning by light irradiation. By patterning, the surfactant layer 60a on the region other than the second pattern region 14 of the substrate 10 (including on the first surfactant layer 20) is photolyzed and removed.

  The details of the patterning method and material of the second surfactant layer 60 can be applied to the contents of the first surfactant layer 20. For example, the substrate 10 is immersed in a surfactant solution containing a surfactant component, and the second surfactant layer 60a is formed on the entire surface of the substrate 10 (including on the first metal layer 50) (see FIG. 6). ), Patterning is performed by irradiating the light 31 from the light source 33 through the mask 35 (see FIG. 7). The light-shielding portion 37 of the mask 35 has a pattern shape that is plane-symmetric with the second pattern region 14, whereby the light 31 can be transmitted to a region other than the second region 14. The mask 35 may be disposed in contact with the substrate 10. Further, it is preferable to perform the light irradiation treatment in a nitrogen atmosphere because the light 31 hardly attenuates. Note that the second surfactant layer 60 may be a cationic surfactant similar to the first surfactant layer 20, or the same material may be used.

  The light irradiation conditions when forming the second surfactant layer 60 are different from the light irradiation conditions when forming the first surfactant layer 20. According to this, it is possible to optimize the light irradiation condition for each of the first and second surfactant layers 20 and 60, and the first and second surfactant layers 20 and 60 ( That is, the pattern accuracy of the metal layer) can be stabilized and the production margin can be improved. The light irradiation conditions are irradiation time, light intensity (energy of light passing per unit time per unit area), and the like. The intensity of light is determined according to the magnitude of light energy (wavelength), set temperature, irradiation distance to the object, and the like. For example, when the first pattern region 12 is a fine pattern region and the second pattern region 14 is a rough pattern region, the irradiation time of the light 31 of the second surfactant layer 60 is the first interface region. It may be shorter than the irradiation time of the light 30 of the activator layer 20. Alternatively, the intensity of the light 31 of the second surfactant layer 60 may be lower than the intensity of the light 30 of the first surfactant layer 20. Thereby, the reaction of photolysis can be appropriately advanced according to each pattern accuracy.

  (7) Next, as shown in FIG. 8, a second catalyst layer 70 is formed on the second surfactant layer 60. Specifically, the substrate 10 is immersed in a catalyst solution containing a catalyst component, whereby the catalyst is selectively adsorbed only on the second surfactant layer 60 and only on the second surfactant layer 60. In addition, the second catalyst layer 70 can be formed. The details of the formation method and materials of the second catalyst layer 70 can be applied to the contents of the first catalyst layer 40.

  (8) Then, as shown in FIG. 9, the second metal layers 80 and 82 are deposited by, for example, immersing the substrate 10 in an electroless plating solution. As a result, the second metal layer 80 is deposited on the second catalyst layer 70, and the second metal layer 82 is further deposited on the first metal layer 50. Since the plating reaction is proportional to the area of the pattern region, if the first pattern region 12 is a fine pattern and the second pattern region 14 is a rough pattern, the second metal layer 80 on the second catalyst layer 70 is used. Is formed thick, and the second metal layer 82 on the first metal layer 50 is formed thin. Therefore, according to the above-described example, the total thickness of the first and second metal layers 50 and 82 on the first pattern region 12 and the thickness of the second metal layer 80 on the second pattern region 14. Can be made uniform. That is, the difference which arises in the same surface of the metal layer on the board | substrate 10 can be suppressed as much as possible.

  The second metal layers 80 and 82 may be made of the same material as that of the first metal layer 50, or the first metal layer may be used if the plating reaction proceeds on the first metal layer 50. A material different from 50 may be used.

  According to the plating method according to the present embodiment, the plating process is performed on the first pattern region 12 and then the plating process is performed on the second pattern region 14. In the plating process performed on the second pattern region 14, the second metal layers 80 and 82 are replaced with the second catalyst layer 70 in the second pattern region 14 and the first metal layer in the first pattern region 12. 50. Thereby, for example, even if the first pattern region 12 is less likely to proceed with the plating reaction than the second pattern region 14, the thickness of the metal layer provided in the first and second pattern regions 12, 14, for example. Can be made uniform.

  FIG. 10 is a diagram illustrating a method for manufacturing the electronic device according to the present embodiment. The electrode pattern can be formed in the first and second pattern regions 12 and 14 on the substrate 10 by the plating method described above. The electrode pattern may be a so-called wiring pattern for electrically connecting electronic components. In that case, the substrate 10 is a wiring substrate. That is, a wiring board can be manufactured by the plating method described above. In the example shown in FIG. 10, an integrated circuit chip 90 is electrically connected to the substrate 10, and one end of the substrate 10 is electrically connected to another substrate 92 (for example, a display panel). The electronic device 1000 may be a display device such as a liquid crystal display device, a plasma display device, or an EL (Electroluminescence) display device. According to the present embodiment, the thickness of the metal layer (electrode pattern) provided in the first and second pattern regions 12 and 14 can be made uniform, so that the signal characteristics of the electronic device can be stabilized. be able to.

  In the example described above, an example in which the same surface of the substrate 10 is divided into two regions and the plating process is performed is shown. However, the present invention is not limited to this, and the same surface of the substrate 10 is divided into three or more regions. It can also be divided and plated. In that case, in the predetermined number of plating processes, the above-described surfactant layer and catalyst layer are formed in a predetermined pattern region, and the subsequent metal layer is formed of the metal layer already formed in the catalyst layer and other pattern regions. It can be deposited on both.

  As a modification, the same surface of the substrate 10 can be divided into three or more regions, and a patterning process by light irradiation of the surfactant layer can be performed. In that case, the patterning accuracy can be further improved by optimizing the light irradiation conditions.

  As a modification, the first and second surfactant layers 20 and 60 are formed by patterning by light irradiation, respectively, and then the catalyst is integrally formed on the first and second surfactant layers 20 and 60. A method of forming a layer and depositing a metal layer integrally on the catalyst layer can also be applied.

(Second Embodiment)
11 to 14 are diagrams for explaining a method of manufacturing an electronic device according to the second embodiment of the invention. Specifically, FIG. 11 is a plan view of the element structure of the electronic device, FIG. 12 is a partially enlarged view thereof, and FIG. 13 is a partial cross-sectional view of FIG.

  The method for manufacturing an electronic device includes the plating method described above. The electronic device is, for example, an organic EL display device. In the case of an active matrix drive type electronic device (display device), a switching element is provided in each of a plurality of pixel portions (not shown). The pixel portion includes a pixel electrode pattern 120, a common electrode pattern (not shown), and a functional element (not shown) provided therebetween. In the case of an organic EL display device, the functional element includes at least a light emitting layer (for example, a polymer organic layer). In the case of the organic EL display device, a switching element (not shown) selected by the scanning line is turned on, and the charge from the signal line passes through the switching element and is stored in a capacitance (not shown). Further, another switching element (thin film transistor 110) is controlled (for example, ON) by the electric charge stored in the capacitance, and a current from the power supply line (wiring 116) passes through the switching element (thin film transistor 110) and enters the pixel portion. It comes to flow.

  The thin film transistor 110 includes a source electrode 112 and a drain electrode 114, a semiconductor layer 130 (for example, an organic semiconductor layer such as a semiconductor polymer bentazen), a gate insulating layer 132, and a gate electrode 134. In the example illustrated in FIG. 13, the source electrode 112 and the drain electrode 114 are formed over the substrate 10, the semiconductor layer 130 is formed over the source electrode 112 and the drain electrode 114, and the gate insulating layer 132 is formed over the semiconductor layer 130. A gate electrode 134 is formed on the gate insulating layer 132. In the example shown in FIG. 12, the source electrode 112 and the drain electrode 114 are arranged on the same surface (same layer) as the pixel electrode pattern 120. Further, the source electrode 112 and the drain electrode 114 are arranged in a comb shape so that each line is alternately arranged. Note that the thin film transistor 110 is not limited to the top gate type described above, and may be a bottom gate type in which each layer is arranged upside down.

  In this embodiment, the electrode pattern (the source electrode 112 and the drain electrode 114) of the thin film transistor 110 is formed over the first pattern region 102 by the above-described plating method. For example, an electrode pattern (for example, the source electrode 112, the drain electrode 114, and the wiring 116) other than the pixel electrode 120 can be formed over the first pattern region 102. The line width of the first pattern region 102 is, for example, 5 μm to 20 μm. Further, the pixel electrode pattern 120 is formed on the second pattern region 104 by the above-described plating method. The line width of the second pattern region 104 is, for example, 0.2 mm to 1.6 mm (for example, 0.2 mm × 0.2 mm to 1.6 mm × 1.6 mm). The details of the plating process for the first and second pattern regions 102 and 104 are as described in the first embodiment. According to this, since the first pattern region 102 is a fine pattern and the second pattern region 104 is a rough pattern, the plating reaction when forming the electrode pattern of the thin film transistor 110 forms the pixel electrode pattern 120. However, according to the present embodiment, the thickness of both metal layers can be made uniform.

  FIG. 14 shows an electronic paper 2000 as an example of the electronic device according to the present embodiment. The other details according to the present embodiment are as described in the first embodiment.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

The figure which shows the plating method which concerns on the 1st Embodiment of this invention. The figure which shows the plating method which concerns on the 1st Embodiment of this invention. The figure which shows the plating method which concerns on the 1st Embodiment of this invention. The figure which shows the plating method which concerns on the 1st Embodiment of this invention. The figure which shows the plating method which concerns on the 1st Embodiment of this invention. The figure which shows the plating method which concerns on the 1st Embodiment of this invention. The figure which shows the plating method which concerns on the 1st Embodiment of this invention. The figure which shows the plating method which concerns on the 1st Embodiment of this invention. The figure which shows the plating method which concerns on the 1st Embodiment of this invention. 1 is a diagram showing an example of an electronic device according to a first embodiment of the present invention. The figure which shows an example of the electronic device which concerns on the 2nd Embodiment of this invention. The figure which shows an example of the electronic device which concerns on the 2nd Embodiment of this invention. The figure which shows an example of the electronic device which concerns on the 2nd Embodiment of this invention. The figure which shows an example of the electronic device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Board | substrate 12 ... 1st pattern area 14 ... 2nd pattern area 20 ... 1st surfactant layer 30, 31 ... Light 40 ... 1st catalyst layer 50 ... 1st metal layer 60 ... 2nd Surfactant layer 70 ... second catalyst layer 80,82 ... second metal layer 102 ... first pattern region 104 ... second pattern region 110 ... thin film transistor 112 ... source electrode 114 ... drain electrode 120 ... pixel electrode pattern

Claims (8)

Forming a surfactant layer, a catalyst layer and a metal layer above at least the first and second pattern regions on the same side of the substrate;
Above the first pattern region, a first surfactant layer is formed by patterning by light irradiation,
Above the second pattern area, a second surfactant layer is formed by patterning by light irradiation,
The plating method, wherein the light irradiation condition when forming the first surfactant layer is different from the light irradiation condition when forming the second surfactant layer. The plating method according to claim 1,
The plating method, wherein the light irradiation time when forming the first surfactant layer is different from the light irradiation time when forming the second surfactant layer. In the plating method according to claim 1 or 2,
The plating method, wherein the light intensity when forming the first surfactant layer is different from the light intensity when forming the second surfactant layer. In the plating method according to any one of claims 1 to 3,
The plating method, wherein the first and second surfactant layers are made of a cationic surfactant. In the plating method according to any one of claims 1 to 4,
The plating method, wherein the first pattern region is connected to the second pattern region. In the plating method according to any one of claims 1 to 4,
The plating method, wherein the first pattern region is separated from the second pattern region. In the plating method according to any one of claims 1 to 6,
The plating method, wherein the second pattern region is a coarser pattern than the first pattern region. In the plating method according to any one of claims 1 to 8,
The plating method, wherein a minimum width of a line in the second pattern region is larger than a maximum width of a line in the first pattern region.

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