JP2006269449A - Semiconductor manufacturing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing system capable of improving productivity. <P>SOLUTION: In a first manufacturing line 1, manufacturing apparatuses 10A-12A, 13, 14A and 15A are laid so that repeating processing units of a wafer process are configured, and one team A of operators takes charge of the first manufacturing line 1 composed of the manufacturing apparatuses 10A-12A, 13, 14A and 15A which are laid in an order of manufacturing processes. A second manufacturing line 2 is configured in a similar way. Further, a manufacturing apparatus 13 is provided as shared by the first and second manufacturing lines 1 and 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing system, and more particularly to a technique effective when applied to a manufacturing line for performing a wafer process (pre-process).

  In the semiconductor device manufacturing technology, for example, in order to improve the productivity of a semiconductor device, a flow shop installation unit and a job shop installation unit are arranged in combination in a clean room (for example, see Patent Document 1) or the same processing. In addition to arranging a flow shop installation unit that repeats a process, there is an arrangement that arranges a flow shop type job shop installation unit in which a plurality of process facilities are centrally arranged around a work transfer route (see, for example, Patent Document 2). is there.

A job shop is a layout method for manufacturing apparatuses that collectively arrange a group of manufacturing apparatuses having the same function, and a flow shop is a layout system that sequentially arranges manufacturing apparatuses corresponding to the order of manufacturing processes.
Japanese Patent Laid-Open No. 11-14502 JP 2002-26106 A

  In a semiconductor manufacturing factory that performs a wafer process (so-called pre-process), a layout of manufacturing equipment often uses a job shop system in which manufacturing device groups having the same type of function are intensively arranged for each manufacturing process element. In this job shop system, teamed workers are assigned to manufacturing apparatus groups arranged for each manufacturing process element. For example, there is an exposure apparatus used in the photolithography process and a CVD (Chemical Vapor Deposition) apparatus used in the film forming process, but in the job shop method, in the apparatus group in which a plurality of exposure apparatuses are intensively arranged, One worker group is assigned, and another worker group is assigned to an apparatus group in which a plurality of CVD apparatuses are intensively arranged. In other words, the workers are divided into teams for each manufacturing process element and share the work (horizontal division of work division structure).

  However, in the case of a horizontal division of work configuration, each worker is only in charge of one process of the semiconductor product manufacturing process, and does not grasp the entire semiconductor product manufacturing process. That is, there is a problem that each worker cannot directly grasp the influence of individual production activity factors on the production volume of semiconductor products in the factory. For this reason, it is complicated to grasp the problem with respect to the macro target value of productivity improvement and to provide feedback for improvement.

  An object of the present invention is to provide a semiconductor manufacturing system capable of improving productivity.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor manufacturing system according to the present invention includes: (a) a first manufacturing line for forming a circuit on a wafer by repeatedly using a first semiconductor manufacturing apparatus group arranged along a repetitive processing unit of a wafer process; (B) a second manufacturing line for forming a circuit on a wafer by repeatedly using a second semiconductor manufacturing apparatus group arranged along a repetitive processing unit of a wafer process, and the first semiconductor The manufacturing apparatus group and the second semiconductor manufacturing apparatus group include semiconductor manufacturing apparatuses that are shared with each other.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the worker can grasp the problem with respect to the macro target value of productivity improvement and feedback to the improvement, the productivity can be improved at the semiconductor device manufacturing factory.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a flowchart showing a wafer process in a manufacturing process of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) which is a representative of a semiconductor device. The manufacturing process of the MISFET will be briefly described with reference to FIG.

  First, an element isolation region for isolating elements is formed on a semiconductor wafer (hereinafter simply referred to as a wafer) (S101). The element isolation region can be formed using, for example, a LOCOS (Local oxidation of silicon) method or an STI (Shallow Trench Isolation) method.

Subsequently, a p-type well is formed in the wafer (S102). The p-type well is formed by introducing a p-type impurity such as boron (B) or boron fluoride (BF ₂ ) into the wafer by using, for example, an ion implantation method.

  Then, after forming a gate insulating film made of, for example, a silicon oxide film on the wafer (S103), a polysilicon film is formed on the gate insulating film using, for example, a CVD apparatus. Subsequently, the polysilicon film is patterned by a photolithography technique using an exposure apparatus or the like to form a gate electrode (S104).

  Subsequently, by introducing an n-type impurity such as phosphorus (P) or arsenic (As) using an ion implantation apparatus, for example, a source region and a drain region are formed in alignment with the gate electrode (S105). Thereafter, an interlayer insulating film made of a silicon oxide film is formed on the wafer using, for example, a CVD apparatus (S106). Then, the surface of the interlayer insulating film is planarized using, for example, CMP (Chemical Mechanical Polishing) (S107). The process so far is a so-called substrate process. By this substrate process, a MISFET can be formed on the wafer.

  Next, contact holes reaching the source region or the drain region are formed in the interlayer insulating film by using a photolithography technique and an etching technique. Then, a plug is formed in this contact hole by embedding a tungsten film using, for example, a CVD apparatus (S108).

  Subsequently, an aluminum film is formed on the interlayer insulating film on which the plug is formed, for example, using a sputtering apparatus. Then, using the photolithography technique and the etching technique, the aluminum film is patterned to form a wiring (S109).

  Next, after forming an interlayer insulating film using, for example, a CVD apparatus (S110), the surface of this interlayer insulating film is planarized using, for example, a CMP apparatus (S111). Thereafter, the same process is repeated to form a multilayer wiring. Then, after forming the multilayer wiring, a passivation film is formed to protect the surface (S112). The passivation film is made of, for example, a silicon nitride film, and can be formed by, for example, a CVD apparatus. The process so far is a so-called wiring process.

  As described above, the circuit including the MISFET and the wiring can be formed on the wafer through the substrate process and the wiring process.

  FIG. 2 is a diagram showing a production line for semiconductor devices according to the first embodiment. In FIG. 2, in the first embodiment, a first production line 1 and a second production line 2 are provided. A semiconductor factory is provided with a plurality of production lines. FIG. 2 shows a first production line 1 and a second production line 2 among them. The first production line 1 and the second production line 2 are separate and independent production lines, and wafer processing (processing for forming a circuit on the wafer) is performed independently of each other.

  The first production line 1 is provided with production apparatuses 10A to 12A, 13, 14A, and 15A (first semiconductor production apparatus group). The manufacturing apparatuses 10A to 12A, 13, 14A, and 15A are used in the manufacturing process shown in FIG. 1, and are, for example, a CVD apparatus, a CMP apparatus, a cleaning apparatus, an exposure apparatus, an alignment inspection apparatus, and an appearance inspection apparatus. , A dimension measuring device, an etching device, an ashing device, a polymer removing device, an annealing device, a sputtering device, an electrolytic plating device, and the like.

  The CVD apparatus is an apparatus that supplies a compound gas consisting of elements constituting a thin film material or a single gas to a wafer and forms a desired thin film by a chemical reaction on the gas phase or the wafer surface. The CMP apparatus is an apparatus that polishes a wafer affixed to a spindle against a polishing pad while flowing a polishing liquid (slurry) on the surface of the wafer, and is used, for example, for flattening an interlayer insulating film. .

  The cleaning device is a device that removes foreign matter on the surface of the wafer by cleaning the wafer. The exposure apparatus is an apparatus that exposes a mask pattern onto a wafer, and the alignment inspection apparatus is an apparatus that inspects alignment of an exposure pattern. The appearance inspection apparatus is an apparatus that inspects a defect such as a mask pattern.

  The dimension measuring apparatus is an apparatus for measuring dimensions of a pattern or the like formed on the wafer, and the etching apparatus is an apparatus for etching and patterning a film formed on the surface of the wafer. The ashing device is a device for ashing and removing the resist film formed on the wafer, and the polymer removing device is a device for peeling an unnecessary polymer film from the wafer.

  The annealing apparatus is an apparatus for heat-treating a thin film formed on the wafer, and the sputtering apparatus is an apparatus for forming a thin film by a sputtering phenomenon. The electroplating apparatus is an apparatus for forming wiring by an electroplating method.

  In the first embodiment, the manufacturing apparatuses 10A to 12A, 13, 14A, and 15A provided in the first manufacturing line 1 are laid out in the order of manufacturing processes so that the wafers are processed along the wafer process shown in FIG. Has been. That is, in the manufacturing apparatuses 10A to 12A, 13, 14A, and 15A, first, when the wafer is processed by the manufacturing apparatus 10A and the processing is completed, the wafer is then processed by the manufacturing apparatus 11A. Further, when the wafer processing is completed in the manufacturing apparatus 11A, the wafer processing is performed in the manufacturing apparatus 12A. In this way, when the wafer processing is completed in the manufacturing apparatus 15A, the wafer processing is performed again in the manufacturing apparatus 10A. By repeating this flow, a circuit is formed on the wafer.

  That is, the manufacturing apparatuses 10A to 12A, 13, 14A, and 15A constitute a repetitive processing unit of the wafer process. By repeating the processes in the manufacturing apparatuses 10A to 12A, 13, 14A, and 15A, along the wafer process. Thus, a circuit is formed on the wafer. The wafers are transported in lot units, and each manufacturing apparatus, for example, takes out the wafers one by one from the lot and processes them.

  Similarly, a second production line 2 is provided as another production line independent of the first production line 1. The second manufacturing line 2 is provided with manufacturing apparatuses 10B to 12B, 13, 14B, and 15B (second semiconductor manufacturing apparatus group), and the manufacturing apparatuses 10B to 12B, 13, 14B, and 15B are also shown in FIG. The wafers are laid out in the order of manufacturing processes so that the wafers are processed along the wafer process.

  One feature of the first embodiment is that, for example, in the first manufacturing line 1, the manufacturing apparatuses 10A to 12A, 13, 14A, and 15A are laid out so as to constitute a repetitive processing unit of the wafer process, and in the order of the manufacturing process. One worker team A is in charge of the first production line 1 including the layout of the manufacturing apparatuses 10A to 12A, 13, 14A, and 15A (team cell production method). That is, the worker team A has responsibility and authority for the progress of products manufactured in the first manufacturing line 1 (vertically integrated business staff). As described above, since the worker team A is in charge of the first production line 1 by one worker team A, the worker team A is consistently in charge from the first process to the final process of the wafer process. It is possible to directly grasp the influence of the production activity of the worker team A on the production volume. Therefore, the problem in the production line can be grasped or feedback for improvement can be clarified, so that the productivity in the factory can be improved.

  Similarly, in the second production line 2, by assigning the worker team B different from the worker team A, the worker team B is also in charge of the wafer process from the first process to the final process. For this reason, the influence of the production activity of the worker team B on the production output of the factory can be directly grasped. That is, by assigning different worker teams to individual production lines arranged along the wafer process, it becomes possible to directly grasp the influence of the production activities of each worker team.

  Further, for example, in the first manufacturing line 1, since the manufacturing apparatuses 10A to 12A, 13, 14A, and 15A are arranged along the repetitive processing unit of the wafer process, the flow of objects is simplified, and leveling production is easy. Become. That is, since logistics is simplified, the in-process amount allocated to each of the manufacturing apparatuses 10A to 12A, 13, 14A, and 15A is easily flattened.

  Further, one feature of the first embodiment is that the first manufacturing line 1 and the second manufacturing line 2 which are different from each other have the manufacturing apparatus 13 shared. By sharing the manufacturing apparatus 13 in this way, for example, it is possible to avoid occupying an apparatus with a large processing capacity on one manufacturing line, and the apparatus can be operated efficiently. In other words, if an apparatus having a large processing capacity is occupied on one production line, the time during which lots are not processed cannot be used effectively, and the operating rate of the apparatus decreases. Therefore, if the apparatus is shared by a plurality of production lines, the time during which lots are not processed can be reduced, and the operating rate of the apparatus can be improved. In addition, since the number of manufacturing apparatuses can be reduced by sharing the manufacturing apparatus among a plurality of manufacturing lines, an effect of reducing costs can also be obtained. In FIG. 2, the manufacturing apparatus 13 is shared by the first manufacturing line 1 and the second manufacturing line 2, but may be shared including other manufacturing lines (not shown). . In FIG. 2, only the manufacturing apparatus 13 is shared, but another manufacturing apparatus may be shared.

  When a manufacturing apparatus is shared by a plurality of manufacturing lines, it is necessary to consider processing when a lot processing request is made from the plurality of manufacturing lines to the shared manufacturing apparatus. Hereinafter, the lot allocation logic will be described.

  FIG. 3 is a diagram showing the configuration of the semiconductor manufacturing system according to the first embodiment. In FIG. 3, for example, the manufacturing apparatuses 10A to 12A, 13, 14A, 15A, 10B to 12B, 14B, and 15B are connected to a MES (Manufacturing Execution System) 20 via a network such as a LAN (Local Area Network). . The MES 20 is a manufacturing execution system, and is configured to control and manage the manufacturing apparatuses 10A to 12A, 13, 14A, 15A, 10B to 12B, 14B, and 15B. The MES 20 controls lot allocation to manufacturing apparatuses shared by a plurality of manufacturing lines. The lot assignment operation will be described below with reference to FIGS. 4 and 5. FIG.

FIG. 4 is a flowchart showing an operation of determining a lot processing allocation frame for each production line. First, a process allocation frame (X _ij ) of each production line (i: natural number) in a shared production apparatus (j: natural number) is determined for a certain period (T) (S201). Subsequently, the process allocation frame (X _ij ) is stored on the MES 20 as the initial allocation distribution frame (Y _ij ) and the remaining allocation distribution frame (Z _ij ) (S202).

When a certain period (T) has elapsed since the remaining allocation allocation frame (Z _ij ) has been initialized (S203), it is determined whether to review the processing allocation frame (X _ij ) (S204). When reviewing the process allocation frame _{(X ij)} is determined anew process allocation frame a _{(X ij)} returns to S201. On the other hand, if the processing allocation frame (X _ij ) is not reviewed, the remaining allocation allocation frame (Z _ij ) is initialized, and the process returns to S203. In this way, the processing distribution frame (X _ij ) for each production line can be determined.

  Furthermore, it demonstrates concretely. First, for example, a certain period is set to one day, and the processing distribution frame of the first manufacturing line 1 in the shared manufacturing apparatus 13 is set to 1000 sheets (the number of wafers) (S201). Subsequently, the 1000 processing allocation frames are stored on the MES 20 as the initial allocation allocation frame 1000 and the remaining allocation allocation frame 1000 (S202). The initial allocation distribution frame indicates the number of wafers initially allocated to the first production line 1, and the remaining allocation distribution frame is a wafer that is processed and remains in the current stage. Indicates the number of sheets. Therefore, when no wafer is processed, the initial allocation distribution frame and the remaining allocation distribution frame are 1000 in the same manner.

  Next, one day has elapsed since the remaining allocation allocation frame was set to 1000 (S203). At this time, in the shared manufacturing apparatus 13, since the wafers of the first manufacturing line 1 are processed, the remaining allocation distribution frame is reduced from 1000 sheets. If 1000 wafers in the first production line 1 are processed, the remaining allocation distribution frame becomes 0 when one day has passed. On the other hand, when 1000 sheets are not processed, the remaining allocation distribution frame is not 0 sheets but remains (for example, 100 sheets).

  Subsequently, it is determined whether or not to review 1000 processing allocation frames of the first production line 1 (S204). That is, it is determined whether to change the processing distribution frame of the first manufacturing line 1 in the shared manufacturing apparatus 13 from 1000 sheets. For example, when the processing allocation frame is changed from 1000 sheets to 1500 sheets, the processing allocation frame of the first production line 1 is changed to 1500 sheets by returning to S201. Then, on the MES 20, the initial allocation distribution frame and the remaining allocation distribution frame are initialized to 1500 sheets. By doing in this way, it sets so that a maximum of 1500 wafers of the 1st production line 1 may be processed for the next one day.

  On the other hand, if the processing distribution frame of the first production line 1 is not changed from 1000 sheets, the processing distribution frame will be 1000 sheets for the next day. Here, since the remaining allocation distribution frame has decreased from 1000 sheets due to the passage of one day, it is initialized again and the remaining allocation distribution frame is set to 1000 sheets. Thereby, it is possible to start from the remaining allocation allocation frame 1000 for the next day. Although the method for determining the process distribution frame for the first production line 1 has been specifically described above, the process distribution frame for other production lines can be determined in the same manner.

  Next, in the shared manufacturing apparatus, when there is a lot processing request from a plurality of manufacturing lines, which manufacturing line lot is processed preferentially will be described. That is, the lot allocation logic will be described.

FIG. 5 is a flowchart illustrating the lot allocation method. In FIG. 5, first, a lot processing request is generated from a plurality of manufacturing lines (i) to a shared manufacturing apparatus (j) (S301). Then, the shared manufacturing apparatus (j) selects and processes one lot requested for processing from the manufacturing line (i) having the highest priority (P _i ) (S302). Here, the priority (P _i ) of the production line (i) is determined by the remaining allocation distribution frame (Z _ij ) / initial allocation distribution frame (Y _ij ).

Next, the number of wafers in the processing lot is subtracted from the remaining allocation distribution frame (Z _ij ) in the manufacturing apparatus (j) of the manufacturing line (i) that has processed the lot (S303). Thereafter, when the lot processing is completed (S304), the same operation as in S301 is repeated again. In this way, when there is a lot processing request from a plurality of manufacturing lines, a lot of a predetermined manufacturing line can be selected and processed by a shared manufacturing apparatus.

  Furthermore, it demonstrates concretely. For example, in the manufacturing apparatus 13 shown in FIG. 2, it is assumed that there is a lot processing request from the first manufacturing line 1 and the second manufacturing line 2 (S301). Here, the processing allocation frame is determined for each of the first production line 1 and the second production line 2 by the method shown in FIG. For example, the process distribution frame of the first production line 1 is 1000 sheets, and the process distribution frame of the second production line 2 is 2000 sheets. In each of the first production line 1 and the second production line 2, a predetermined number of wafers have already been processed. For example, the remaining allocation distribution frame of the first production line 1 is 100, and the remaining allocation of the second production line 2 is It is assumed that the distribution frame is 500 sheets. That is, in the first production line 1, 900 wafers have already been processed in the manufacturing apparatus 13, and in the second production line 2, 1500 wafers have already been processed.

  Next, the priority of the first production line 1 is 100/1000 = 1/10 because the initial allocation distribution frame is 1000 sheets and the remaining allocation distribution frame is 100 sheets. On the other hand, the priority of the second production line 2 is 500/2000 = 1/4 because the initial allocation distribution frame is 2000 and the remaining allocation distribution frame is 500. Accordingly, since the priority (1/4) of the second production line 2 is higher than the priority (1/10) of the first production line 1, the lot of the second production line 2 is processed (S302).

  Subsequently, since the lot requested to be processed from the second production line 2 is processed, the number of processed wafers (for example, 25 sheets) is reduced from the remaining allocation allocation frame 500 of the second production line 2. Thereby, the remaining allocation distribution frame of the second production line 2 is changed from 500 sheets to 475 sheets (S303).

  Thereafter, when the lot processing of the second production line 2 is completed (S304), the above-described operation is repeated. It is assumed that the remaining allocation distribution frame of the second production line 2 becomes 100 sheets by this repetition. Then, the priority of the first production line 1 is 1/10, whereas the priority of the second production line 2 is 100/2000 = 1/20. Therefore, this time, since the priority (1/10) of the first production line 1 becomes higher than the priority (1/20) of the second production line 2, the lot of the first production line 1 is processed. Become.

  In this way, the lot of the first production line 1 or the second production line 2 is processed based on the priority. The priority is given by the remaining allocation distribution frame / initial allocation distribution frame as described above. This priority increases as the remaining allocation distribution frame increases with respect to the initial allocation distribution frame. In other words, the priority is higher in the production line where the lot processing is not progressing with respect to the initial allocation distribution frame. In the first embodiment, lots requested to be processed from a production line with a high priority are preferentially processed. Therefore, lot processing is properly performed between the production lines, and lot processing in the production line is performed. Leveling can be achieved. In addition, even if the amount of work in a certain production line suddenly increases due to a pulsating flow generated in a certain production line, the lot of that production line is not preferentially processed, but the first embodiment Now process lots from production lines with high priority. For this reason, it is possible to prevent the production progress of the production line that has been leveled production from being hindered.

  As described above, according to the first embodiment, a manufacturing line is configured by laying out a manufacturing apparatus along a repetitive processing unit of a manufacturing process (wafer process), and a plurality of such manufacturing lines are provided independently. . And since one worker team is in charge of each production line, the worker team will be in charge from the first process to the final process, and the responsibility and authority for the product volume are clearly transferred. It has become. Therefore, since each worker team performs production activities on a vertically integrated production line, the problem of the production activities can be grasped and feedback for improvement can be clarified, thereby improving productivity.

  Moreover, according to this Embodiment 1, since each manufacturing line is comprised by the flow shop format, distribution is simplified and management of each manufacturing line becomes easy. Furthermore, since the production apparatus common to the plurality of production lines is efficiently used in the above-described allocation logic, leveled production on the production line is promoted. Thereby, the optimal distribution control of the work in progress is performed for each production line, and the shelf turnover rate is improved. That is, it is possible to suppress an increase in owned assets (wafers in progress).

  Furthermore, according to the first embodiment, since a product is manufactured for each independent manufacturing line, for example, a manufacturing trouble that occurs in a product for a customer adversely affects the manufacturing progress of the product for another customer. Can be suppressed. In other words, in the first embodiment, a plurality of production lines that can be carried out independently from the initial process to the final process of the manufacturing process are provided independently. Now it is possible to produce products for other customers. Since the individual production lines are independent, even if a trouble occurs in a certain production line, it is possible to reduce the influence of the trouble on other production lines. Therefore, customer satisfaction can be improved.

  In addition, since a shared manufacturing apparatus is provided in a plurality of manufacturing lines and this manufacturing apparatus is operated by the above-described lot allocation method, a balanced schedule (processing allocation frame) among the manufacturing lines and a lot with less fluctuation Processing is retained. This makes it possible to clearly show to customers that each production line handles products for different customers, and that the production equipment they share is fair and balanced. Can be improved. In addition, since it is necessary to regularly supply a certain amount of lots to the shared manufacturing apparatus, leveled production is performed on the manufacturing line.

  The semiconductor manufacturing system according to the first embodiment takes a form in which the production capacity of a factory is divided into a plurality of manufacturing lines and a small-scale manufacturing line is virtually arranged. Applicable to factories to handle.

  In recent years, the construction cost of a new semiconductor manufacturing factory (pre-process factory) has become enormous, and it has become difficult to bear that cost by a single semiconductor manufacturing company. For this reason, a form in which a plurality of semiconductor manufacturing companies share the construction cost of a new semiconductor manufacturing factory and one semiconductor manufacturing factory is shared by a plurality of semiconductor manufacturing companies is being studied. In such a semiconductor manufacturing factory, it is useful to apply the semiconductor manufacturing system described in the first embodiment. That is, each semiconductor manufacturing company uses each independent manufacturing line, and the lot allocation method using the above-described priority is used for the manufacturing apparatus shared by each manufacturing line. Thereby, each semiconductor manufacturing company can perform fair and well-balanced manufacturing. Here, in the lot allocation method described above, the number of wafers is used as a process distribution frame for each production line. However, it is conceivable to convert the usage rate of the manufacturing apparatus shared by each manufacturing line by the usage time of the apparatus. In this case, the processing allocation frame may be the usage time of the apparatus.

  In the first embodiment, an example of managing and controlling the lot assignment method when there is a production apparatus shared by each production line using the MES has been described. However, the lot assignment method is managed and controlled by the shared production apparatus itself. You may make it do.

  In addition, in FIG. 2, the manufacturing apparatuses 10 </ b> A to 12 </ b> A, 13, 14 </ b> A, and 15 </ b> A are described so as to pass through sequentially, but when these manufacturing apparatuses 10 </ b> A to 12 </ b> A, 13, 14 </ b> A, 15 </ b> A are repeatedly processed, For example, after processing by the manufacturing apparatus 10A, processing without passing through the manufacturing apparatus 11A and passing through some manufacturing apparatuses so as to be processed by the manufacturing apparatus 12A is included.

(Embodiment 2)
In the first embodiment, the example in which the manufacturing line is configured by the manufacturing apparatus group in which the entire wafer process is arranged along one repetitive processing unit has been described. In the second embodiment, a first processing device group arranged along a repetitive processing unit of the substrate process in the wafer process and a second processing device group arranged along the repetitive processing unit of the wiring process in the wafer process. A production line that repeats the above will be described.

  FIG. 6 is a diagram showing the configuration of the semiconductor manufacturing system according to the second embodiment. In FIG. 6, the semiconductor manufacturing system according to the second embodiment has a first manufacturing line 1 and a second manufacturing line 2.

  The first production line 1 includes a first processing device group including manufacturing devices 30A, 31, and 32A and a second processing device group including manufacturing devices 33A, 34, and 35A. The manufacturing apparatuses 30A, 31, and 32A (first processing apparatus group) are arranged along the repetitive processing unit of the substrate process in the wafer process. By repeatedly using the manufacturing apparatuses 30A, 31, and 32A, a substrate process is performed, and a transistor is formed on the wafer.

  In addition, the manufacturing apparatuses 33A, 34, and 35A (second processing apparatus group) are arranged along the repetitive processing unit of the wiring process in the wafer process. By repeatedly using the manufacturing apparatuses 33A, 34, and 35A, a wiring process is performed, and wiring is formed on the wafer.

  Similarly, the second manufacturing line 2 includes a first processing device group including manufacturing devices 30B, 31, and 32B and a second processing device group including manufacturing devices 33B, 34, and 35B. The manufacturing apparatuses 30B, 31, and 32B are arranged along a repetitive processing unit of the substrate process, and the manufacturing apparatuses 33B, 34, and 35B are arranged along a repetitive processing unit of the wiring process.

  The first production line 1 and the second production line 2 have production apparatuses 31 and 34 that are shared with each other.

  Hereinafter, a lot flow in the first production line 1 will be described. First, the wafer is processed in the manufacturing apparatus 30A, and then the wafer is processed in the manufacturing apparatus 31. Since the manufacturing apparatus 31 is an apparatus shared with the second manufacturing line 2, the wafer is processed according to the lot assignment method described in the first embodiment.

  Subsequently, when the process is completed in the manufacturing apparatus 31, it is processed in the manufacturing apparatus 32A, and then returned to the manufacturing apparatus 30A and processed. By repeating this, a transistor is formed on the wafer.

  Next, the wafer that has completed the substrate process is processed by the manufacturing apparatus 33 </ b> A and then processed by the manufacturing apparatus 34. Then, it is processed by the manufacturing apparatus 35A, returned again, and processed by the manufacturing apparatus 33A. By repeating this, multilayer wiring is formed on the wafer. Wafers are transported in lot units, and in each manufacturing apparatus, for example, wafers are taken out from the lot one by one and processed. Thus, a circuit can be formed on a wafer through the substrate process and the wiring process. The same applies to the second production line 2.

  According to the second embodiment, the first processing device group and the second processing device group are provided corresponding to each of the substrate process and the wiring process having different processing processes. The substrate process is performed with a configuration in which the first processing apparatus group is repeatedly used, while the wiring process is performed in a configuration in which the second processing apparatus group is repeatedly used. By separating the first processing device group and the second processing device group from each other in this way, the substrate process and the wiring process having different processing processes are separated, so that efficiency can be improved from the viewpoint of physical distribution. That is, since the distribution of the substrate process and the distribution of the wiring process are different, the distribution can be made more efficient by separating them.

  In the second embodiment, the same effect as in the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is the flowchart which showed the wafer process among the manufacturing processes of MISFET. It is the figure which showed the structure of the semiconductor manufacturing system in Embodiment 1 of this invention. It is the figure which showed the structure of the semiconductor manufacturing system in Embodiment 1 of this invention. It is the flowchart which showed the operation | movement which determines the processing allocation frame of the lot with respect to each manufacturing line. It is the flowchart explaining the lot allocation method. It is the figure which showed the structure of the semiconductor manufacturing system in Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st manufacturing line 2 2nd manufacturing line 10A-12A Manufacturing apparatus 10B-12B Manufacturing apparatus 13 Manufacturing apparatus 14A, 15A Manufacturing apparatus 14B, 15B Manufacturing apparatus 20 MES
30A manufacturing apparatus 30B manufacturing apparatus 31 manufacturing apparatus 32A, 33A manufacturing apparatus 32B, 33B manufacturing apparatus 34 manufacturing apparatus 35A manufacturing apparatus 35B manufacturing apparatus

Claims (5)

(A) a first manufacturing line for forming a circuit on a wafer by repeatedly using a first semiconductor manufacturing apparatus group arranged along a repetitive processing unit of a wafer process;
(B) a second manufacturing line for forming a circuit on the wafer by repeatedly using the second semiconductor manufacturing apparatus group arranged along the repetitive processing unit of the wafer process,
A semiconductor manufacturing system in which the first semiconductor manufacturing device group and the second semiconductor manufacturing device group include semiconductor manufacturing devices shared with each other. (A) a first manufacturing line for forming a circuit on a wafer by repeatedly using a first semiconductor manufacturing apparatus group arranged along a wafer process;
(B) a second production line for forming a circuit on the wafer by repeatedly using the second semiconductor production equipment group arranged along the wafer process,
The first semiconductor manufacturing apparatus group and the second semiconductor manufacturing apparatus group have a semiconductor manufacturing apparatus shared by each other,
The first semiconductor manufacturing apparatus group and the second semiconductor manufacturing apparatus group are respectively a first processing apparatus group disposed along a repetitive processing unit of a substrate process in a wafer process and a repetitive processing unit of a wiring process in a wafer process. And a second processing unit group arranged along the line.   2. The semiconductor manufacturing system according to claim 1, wherein allocation of lots to the semiconductor manufacturing apparatuses shared with each other is determined based on a priority of the first manufacturing line and a priority of the second manufacturing line.   4. The semiconductor manufacturing system according to claim 3, wherein the priority of the first production line and the priority of the second production line are determined by a ratio of a remaining allocation distribution frame to an initial allocation distribution frame allocated in advance.   When the lots of the first production line are processed in the semiconductor manufacturing apparatuses shared with each other, the remaining allocation allocation frame of the first production line is the remaining allocation of the first production line by the number of processed lots. The semiconductor manufacturing system according to claim 4, wherein the allocation frame is reduced.

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