JP2006268651A - Emulation apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that it is difficult for a conventional emulation apparatus to emulate a plurality of user circuits when less number of memories are provided. <P>SOLUTION: The emulation apparatus includes: a plurality of function circuits 103 disposed within an electrically redesignable semiconductor device disposed on an evaluation substrate; a memory 102 which is disposed on the evaluation substrate and may be simultaneously accessed from the plurality of function circuits 103; an access control circuit 104 which performs time division multiple access control if at least two of the plurality of function circuits simultaneously access the memory 102, and outputs a pause signal to be activated while at least one of the plurality of function circuits 103 accesses the memory 102; and a clock control circuit 105 which stops supplying clocks to the plurality of function circuits 103 while the pause signal is in the active state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an emulation apparatus, and more particularly to an emulation apparatus for a system in which a logic circuit accesses a plurality of memories simultaneously.

  In the development of system LSI (Large Scale Integration), if a defect is discovered after the trial production of the system LSI, it requires expensive expenses such as correction of the LSI exposure mask, and a long time is required for the trial production again. It is. In particular, the cost required for the correction is becoming higher as the technology used in the manufacturing process becomes more advanced as the integration of LSIs increases.

  Therefore, in order to prevent problems of the system LSI, actual operation verification in a form close to the system LSI that is the final product is performed before the trial production of the system LSI. As a result, the design of the system LSI can be made highly complete. Therefore, prior to prototyping the system LSI, which is the final product, system LSI operations are emulated (simulated) using a prototype board that uses an electrically redesignable LSI such as an FPGA (Field Programmable Gate Array). Is done.

  A schematic diagram of an FPGA board 300 that performs emulation using the FPGA is shown in FIG. The FPGA board 300 shown in FIG. 3 has one FPGA 301 and one memory 302 connected thereto. The FPGA 301 can realize various circuits inside by an external program.

  When emulation is performed, a plurality of user circuits which are functional circuits may be realized in the FPGA 300, and each user circuit may be a system having a memory. A block diagram of a system 400 having three user circuits and a memory connected to each of them is shown in FIG. The block diagram shown in FIG. 4 includes user circuits 401, 402, and 403, the user circuit 401 and the user circuit 402 are connected, and the user circuit 402 and the user circuit 403 are connected. Each user circuit is connected to a separate memory 404, 405, 406.

  When emulating a system such as the system 400 on the FPGA board 300, it is possible to apply the time division multiple access disclosed in Patent Document 1 to perform time division multiple access to one on-board memory. It is done.

  FIG. 5 shows a block diagram of an FPGA 501 and a memory 502 having a conventional general time division multiple access circuit. The FPGA 501 illustrated in FIG. 5 includes user circuits 1 to 3 and a time division multiple access control circuit 504. The memory 502 includes memories 1 to 3 that are divided in correspondence with the user circuits 1 to 3. The user circuits 1 to 3 are given a low-speed clock from the outside, and the time division multiple access control circuit 504 is given a high-speed clock from the outside. The time division multiple access control circuit 504 receives addresses 1 to 3 from each user circuit, converts them into addresses on the actual memory, and performs communication between each user circuit and the memory.

  FIG. 6 shows an operation timing chart of the FPGA 501 and the memory 502 shown in FIG. The period of timing A shown in FIG. 6 is a case where there are memory accesses (user accesses 1 to 3) from three user circuits, respectively. In this case, the time division multiple access control circuit 504 sequentially performs each access. As a result, each of the three user circuits completes access. Timing B is a case where only the user circuit 2 among the three user circuits performs memory access. In this case, the time division multiple access control circuit 504 performs data access only for the user circuit 2.

  In the conventional general time division multiple access control circuit, it is necessary to complete all memory accesses from a plurality of user circuits within one cycle of the clock of the user circuit. If the clock of the next cycle is input to the user circuit before the memory access of all the user circuits is completed, there is a problem that the user circuit that cannot access the data in the memory malfunctions.

  The conventional general time division multiple access circuit uses the time within one cycle of the user circuit divided by the number of user circuits. For this reason, the length of one cycle of the clock of the user circuit must be longer than the length obtained by the product of the data access time and the number of user circuits.

That is, the clock speed of the user circuit cannot be made faster than the value obtained from the data access time and the number of user circuits. Therefore, even when the user circuit is not performing memory access, the user circuit must be operated with a slow clock considering memory access. Therefore, there is a problem that it is difficult to operate the user circuit at high speed. As the scale of the system LSI increases, the circuit scale realized by the FPGA also increases and the number of functions to be verified increases. In recent years, early software development has also been performed using an emulation device. In this case, if the operation speed of the FPGA is slow, there is a problem that the verification time and the software development period become enormous. In order to solve this problem, it is conceivable to increase the number of memories in accordance with the number of user circuits in the FPGA. In this case, however, there is a problem that time and cost for redesigning the FPGA board increase.
Special table 2002-507294

  The conventional emulation apparatus has difficulty in high-speed emulation when the number of memories is smaller than that for a plurality of user circuits.

  An emulation apparatus according to the present invention includes a plurality of functional circuits disposed inside an electrically redesignable semiconductor device disposed on an evaluation board, and a plurality of functional circuits disposed on the evaluation board, and simultaneously from the plurality of functional circuits. When at least two of the memory to be accessed and the plurality of functional circuits simultaneously access the memory, the access is time-division multiplexed, and at least one of the plurality of functional circuits controls the memory. An access control circuit that outputs a pause signal that is in an active state when accessed; and a clock control circuit that stops clock supply to the plurality of functional circuits while the pause signal is in an active state. is there.

  According to the present invention, even in an emulation device having a plurality of functional circuits that perform time division multiple access to the memory, the functional circuit performs memory access by having the access control circuit and the clock control circuit. It is possible to stop the supply of the clock to the functional circuit while it is on, and to supply a high-speed clock to the functional circuit while the memory is not being accessed. As a result, the functional circuit can be operated at high speed while the memory is not being accessed, so that the time and cost of emulation verification can be reduced.

  According to the emulation apparatus of the present invention, high-speed emulation is possible for a plurality of user circuits even with a smaller number of memories.

  Embodiment 1

  FIG. 1 shows an emulation apparatus 100 according to the first embodiment. The emulation apparatus 100 will be described in detail with reference to FIG. The emulation apparatus 100 includes an FPGA 101 and a memory 102.

  The FPGA 101 controls the user circuit 103 that realizes the internal emulation function, the access control circuit 104 that controls the memory access of the user circuit 103 by time division multiplexing, the on-board clock input to the FPGA 101, and the user clock to the user circuit 103. A clock control circuit 105 that controls supply is provided.

  The user circuit 103 has user circuits 1 to 3 which are units of functional circuits to be emulated. The user circuits 1 to 3, respectively, are addresses 1 to 3, which are first address signals, signals Wen1 to 3 for designating data writing, signals Ren1 to 3 for designating data reading, and data 1 to 3 serving as transmission / reception data Is input or output. The input / output signal of the user circuit may be a separate bus in which input wiring and output wiring are separated or an input / output bus in which input wiring and output wiring are integrated.

  The access control circuit 104 includes an access information analysis unit 106 and a selector 107. The access information analysis unit 106 converts addresses 1 to 3 into a converted address that is a second address signal indicating an actual address on the memory, and outputs the converted address. Further, the access information analysis unit 106 outputs a select signal SEL for selecting any one of the user circuits 1 to 3 to which the selector 107 is connected based on the input addresses 1 to 3. The selector 107 enables transmission / reception of a signal between one user circuit selected based on the select signal SEL and the memory 102.

  Further, the access information analysis unit 106 outputs a pause signal and a memory clock based on the addresses 1 to 3. The pause signal is a signal for stopping the user clock output from the clock control circuit 105. The pause signal stops the user clock when it is at a high level (eg, power supply voltage) indicating an active state, and does not stop the user clock when it is at a low level (eg, ground voltage) indicating an inactive state. The memory clock is a clock that outputs a clock when the user circuit is accessing the memory and stops when the user circuit is not accessing the memory.

  The access information analysis unit 106 operates based on an external on-board clock. Further, the user clock output from the clock control circuit is monitored.

  The clock control circuit 105 includes a clock counter 108 and a determiner 109. The clock counter 108 counts the number of rising edges of the on-board clock input from the outside, and outputs the count value from the output terminal Q. In the clock counter 108, the pause signal inverted from the access control circuit 104 via the inverter 110 is input to the enable terminal. The clock counter 108 counts the onboard clock when a high level signal is input to the enable terminal, and stops counting the onboard clock when a low level signal is input.

  The determiner 109 determines the frequency division ratio of the clock counter according to the determination condition, and generates a user clock. In the first embodiment, for example, a determination condition of divide by 4 is used. The determination condition Q [1] == 1′b1 is that when the second bit of the output Q of the clock counter 108 is “1 (High)”, the determiner 109 outputs “1” and the second bit is “ When 0 (Low) ", the determination unit 109 is a condition for outputting" 0 ". In other words, when the output of the clock counter 108 has a 2-bit bit size and the tens place is 2 bits and the first place is 1 bit, the output of the clock counter 108 is “00”, “01”, “10”. Proceed with “11”. From this, it can be seen that the output of the determiner 109 repeats “1” and “0” every time the on-board clock rises twice, resulting in a division by four. This division ratio can be arbitrarily set such as 1/2 division, 2 division, and 8 division.

  The memory 102 has a virtual memory space divided as many as the number of user circuits that require the memory. For example, it has memories 1 to 3 corresponding to the user circuits 1 to 3, respectively.

  Next, FIG. 2 shows a timing chart of the operation of the emulation apparatus according to the first embodiment. The operation of the emulation apparatus according to the first embodiment will be described with reference to FIG.

  First, at timing T1, the user circuits 1 to 3 perform accesses 1 to 3 to the memories, respectively. In this case, the access control circuit 104 transmits / receives data between the user circuit 1 and the memory 1 based on the access 1 from the timing T1 to T2, and between the user circuit 2 and the memory 2 based on the access 2 from the timing T2 to T3. Data transmission / reception is performed, and transmission / reception of data between the user circuit 3 and the memory 3 is performed based on the access 3 from timing T3 to T4. That is, each access is time-division multiplexed at the access control circuit 104 timing T1 to T4.

  Further, the access control circuit 104 generates a memory clock based on an access signal from each user circuit at timing T1. The memory operates based on this memory clock. Furthermore, the access control circuit 104 generates a pause signal based on the access signal. The pause signal is inverted by the inverter 110 and is input to the enable terminal of the clock counter 108 in the clock control circuit 105. The clock counter 108 stops the on-board clock counting operation because a low level signal is input to the enable terminal. As a result, the output of the clock counter 108 is held at “10”. Since the output Q of the clock counter 108 remains “01”, the user clock output from the determiner 109 remains at the high level. While the user clock is held at the high level, each user circuit stops the data processing operation.

  When access from all user circuits is completed at timing T4, the access control circuit 104 sets the pause signal to the low level. In response to the pause signal, the enable terminal of the clock counter 108 is at a high level, so the on-board clock count is resumed. Therefore, the clock control circuit 105 outputs a user clock. Each user circuit performs a data processing operation based on the user clock. When none of the user circuits 1 to 3 accesses the memory, the access control circuit 104 stops the memory clock.

  When there is an access 2 to the memory 102 from the user circuit 2 at the timing T5 and there is no access to the memory 102 from the user circuits 1 and 3, the access control circuit 104 determines whether the user circuit 2 and the memory 2 are connected based on the access 2. Send and receive data. Also in this case, the pause signal becomes High level, and the count operation of the clock counter 108 is stopped. Therefore, each user circuit stops data processing until the user circuit 2 completes the access 2.

  According to the emulation apparatus 100 of the first embodiment, when at least one of the user circuits 1 to 3 transmits / receives data to / from the memory 102, the access control circuit 104 sets the pause signal to the high level, and the clock control circuit 105 Stop the user clock. Thus, even if the speed of the user clock is increased, the user circuit does not operate while each user circuit is accessing the memory 102. Therefore, the user circuit can be operated at high speed without causing a memory access failure. When verifying a complex and large-scale user circuit with a large number of verification patterns, it is possible to shorten the verification time compared to a conventional emulation device by operating the user circuit at high speed. Even when an emulation device is used for software development, the user circuit can be operated at high speed, so that the software development period can be shortened.

  Further, the emulation apparatus 100 according to the first embodiment performs time division multiple access to the memory 102 from each user circuit. Therefore, for example, an emulation verification board having various user circuits capable of high-speed operation can be realized with one FPGA and one memory. That is, if various user circuits can be verified with a predetermined emulation verification board, the time and cost for designing a new emulation verification board can be reduced.

  The present invention is not limited to the above embodiment, and can be modified as appropriate. For example, there may be one or more user circuits, and the number is not limited. Also, a plurality of memories may be used as long as time division multiple access is performed from the user circuit. Further, the connection between the access control circuit 104 and the clock control circuit 105 only needs to be able to stop the user clock by the pause signal, and the logic and connection method of the connection are not limited to the above embodiment.

  In the above embodiment, an FPGA is used as an electrically redesignable device. However, this may be any device that can be electrically redesigned. For example, it can be realized by a CPLD (Complex Programmable Logic Device). Further, the memory that is time-division multiple accessed from the user circuit is not limited to the memory, and may be any device that is time-division multiple access from the user circuit.

1 is a diagram illustrating an emulation device according to a first embodiment; 3 is an operation timing chart of the emulation device according to the first exemplary embodiment; It is a figure which shows a general FPGA board. FIG. 2 is a diagram of a general system having a plurality of user circuits and a plurality of memories. It is a figure which shows the conventional emulation apparatus. It is a figure which shows the operation | movement timing chart of the conventional emulation apparatus.

Explanation of symbols

101 FPGA (Field Programmable Gate Array)
102 Memory 103 User Circuit 104 Access Control Circuit 105 Clock Control Circuit 106 Access Information Analysis Unit 107 Selector 108 Clock Counter 109 Determinator 109 Determinator 110 Inverter 301 FPGA
302 Memory 401 User circuit 402 User circuit 403 User circuit 404 Memory 501 FPGA
502 memory 504 time division multiple access control circuit

Claims (7)

A plurality of functional circuits disposed inside an electrically redesignable semiconductor device disposed on an evaluation board;
A memory that is disposed on the evaluation board and may be accessed simultaneously from the plurality of functional circuits;
When at least two of the plurality of functional circuits access the memory at the same time, the access is time-division multiplexed, and when at least one of the plurality of functional circuits is accessing the memory, the active state An access control circuit that outputs a pause signal,
An emulation apparatus comprising: a clock control circuit that stops clock supply to the plurality of functional circuits while the pause signal is in an active state.   The emulation device according to claim 1, wherein the plurality of functional circuits divide the memory into areas and virtually use the plurality of memories as a plurality of memories.   The access control circuit includes an access information analysis unit that converts a first address signal output from each of the plurality of functional circuits into a second address signal indicating an actual address on a memory. 3. The emulation device according to 1 or 2.   The access control circuit is one of an access information analysis unit that outputs a select signal based on the first address signal output from each of the plurality of functional circuits, and transmission / reception data of the plurality of functional circuits based on the select signal. 4. The emulation apparatus according to claim 1, further comprising a selector for selecting one.   5. The emulation apparatus according to claim 1, wherein the access control circuit outputs a pause signal for stopping the clock supply of the clock control circuit based on the first address signal. 6. .   The emulation apparatus according to claim 1, wherein the clock control circuit supplies a clock to the plurality of functional circuits while the plurality of functional circuits are operating. Multiple functional circuits;
A memory that may be accessed simultaneously from the plurality of functional circuits;
When at least two of the plurality of functional circuits access the memory at the same time, the access is time-division multiplexed, and when at least one of the plurality of functional circuits accesses the memory, it is active. An access control circuit that outputs a pause signal that becomes a state;
An emulation apparatus comprising: a clock control circuit that stops clock supply to the plurality of functional circuits while the pause signal is in an active state.

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