JP2006268523A - Disk array device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disk array device for reducing a bottleneck of a cache memory by eliminating useless access to the cache memory as much as possible. <P>SOLUTION: A WT flag, an MOD flag, a PG flag and a TYPE flag are provided in management information for managing the cache memory 20, data on a cache page used for parity generation are data written from a host by fast writing, it is possible to recognize that parity update by the data is not completed, and in this case, the parity is updated by write data from the host in the same manner as that of a normal cache hit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a disk array device, and more particularly to a disk array device that performs high-speed processing using a cache memory as a temporary data storage unit.

  A disk array device is a file device that incorporates a plurality of magnetic disk devices using the “RAID architecture” devised at the University of California, Berkeley. One or more data disks that store data and their redundant data Data is managed by one or more redundant disks that store.

  In the “RAID architecture”, several methods are proposed for generating redundant data, which are classified into RAID 1, 3, 4, 5, etc. according to the redundant data generating method. Furthermore, today, a method called RAID 6 that can be restored even if a failure occurs in a plurality of disks is recognized as a method that emphasizes reliability. As documents describing the RAID architecture, there are Patent Document 1 and Patent Document 2.

  Among these, RAID 3, 4, 5, and 6 are obtained by performing parity operation on redundant data, so overhead due to parity generation during the write operation (hereinafter referred to as write penalty) occurs, and in terms of performance, particularly write performance. I left a challenge.

  It is generally known to use a cache memory as one method for solving this problem. In particular, by using a non-volatile memory as the cache memory, the response to the host has been dramatically increased by using the FAST write method that is completed when write data is written into the cache memory.

JP 2000-112668 A JP 2003-228461 A

  The first problem is that the update process of parity data for data written on the cache memory by the FAST write method is performed asynchronously with the request from the host computer, and the subsequent write operation from the host computer is cached. Even when data on the memory is hit, the data may not be updated because the data is used for generating parity data.

  For example, in FIG. 4, it is assumed that there is pre-update data D0n, new data D0n + 1, and pre-update parity data Pn on the cache memory, and new parity data Pn + 1 is generated using them. If a new data D0n + 1 write request for new data D0n + 1 occurs here, a cache hit occurs, but the corresponding cache page is busy, so another cache page must be opened and the latest data D0n + 2 stored therein. Don't be. Thereafter, after the generation of new parity data Pn + 1 is completed, new parity data Pn + 2 is generated again from D0n + 1, post-update data D0n + 2, and parity data Pn + 1 that have become pre-update data.

  In this case, in order to generate new parity data Pn + 2, six read transfers and two write transfers are performed, and an extra cache page is used.

  Recently, in order to process requests from a large number of host computers for the purpose of batch management of data, there is an increasing number of host director ports, and there is a problem that access to the cache memory becomes a bottleneck.

  An object of the present invention is to provide a disk array device that reduces unnecessary bottlenecks of the cache memory by minimizing unnecessary access to the cache memory in a disk array device that realizes high-speed processing using the cache memory. .

  In the disk array device of the present invention, in a disk array device that uses a cache memory to increase processing speed and generate parity data, even when a cache page that has been hit by write is in use, the corresponding data is parity data. A disk array device characterized in that if it is used for generation, writing to a cache page is possible in the same way as a normal write hit operation.

  The cache memory has a management area for managing cache pages, and the management area has a WT flag, a MOD flag, a PG flag, and a TYPE flag.

  The disk array device of the present invention processes write data in the same manner as a normal cache hit operation under a certain condition even when a cache page hit by a cache transfer in a write transfer from a host computer is already in use. Further, it is possible to reduce the access to the cache memory and reduce the bottleneck of the cache memory by interrupting useless transfer that is already in operation.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic block diagram of a disk array device equipped with a cache memory.

  Referring to FIG. 1, the host interface 1 performs communication and data transfer with a host computer.

  The host directors 10 to 11 make a cache hit determination based on the cache management information recorded on the cache memory 20 in response to a request from the host computer, access the corresponding cache page if it is a hit, and disk if it is a miss. Disk data is requested to the director 30.

  The cache memory 20 writes write data and returns read data in response to requests from the host directors 10 and 11 and the disk director 30. The cache memory 20 is logically managed in units of a large number of cache pages, and the management information is also stored on the cache memory 20. Further, the management information includes a WT flag, a MOD flag, a PG flag, and a TYPE flag as shown in FIG.

  The communication means 40 enables communication between the host directors 10 and 11 and the disk director 30 and can generate an interrupt for each director.

  The disk director 30 reads data from the disk devices 4 to 8 according to a request from the host directors 10 and 11, loads the data into the cache memory 20, and converts the data that has been FAST-written by the host directors 10 and 11. In contrast, the built-in EXOR engine 31 generates parity data in a timely manner. In addition, it has a function of writing data that has been FAST-written after the generation of parity data and the generated parity into the corresponding blocks of the disk devices 4-8. The built-in EXOR engine 31 can be interrupted and restarted in accordance with an instruction from the disk director 30.

  Although the configuration of the embodiment has been described in detail above, the disk devices 4 to 8 in FIG. 1 are well known to those skilled in the art and are not directly related to the present invention, so the detailed configuration is omitted.

  Next, a cache control method of the disk array device configured as described above will be described with reference to FIG.

  The host director 10 receives a write request from the host computer via the host interface 1. The host director 10 searches the management information of the cache memory 20 from the requested logical address and length of the disk, and determines whether or not the data at the corresponding address exists in the cache memory (hit determination). In addition, the management information for each cache page includes information as shown in FIG. 3, and whether the hit cache page is in use (BUSY = '1') or not, and what kind of transfer is in use. It is determined from the WT flag, the MOD flag, the PG flag, and the TYPE flag.

  If it is not in use (BUSY = '0'), management information is updated with BUSY = '1' and ID = '10 'to indicate that the host director 10 is in use. The cache page is executed, and when the page for the transfer length is secured, the host computer is notified that the data can be written, and the write transfer is started.

  Even when the cache page is in use, when WT = '0', MOD = '1', PG = '1', and TYPE = '0', that is, before update as shown in FIG. In the case of a write hit to D0n + 1 in the case where the transfer for generating the new parity Pn + 1 from the data D0n, the new data D0n + 1, and the pre-update parity Pn is started, the parity of the corresponding data is transmitted to the disk director 30 via the communication means 40. The interrupt of the transfer for generation is instructed and the host computer is notified that the data can be written, and the write transfer is started.

  When receiving the transfer interruption instruction from the host director 10, the disk director 30 interrupts the transfer of the EXOR engine 31 performing the corresponding transfer. At this time, the cache page remains in use so that the corresponding cache page can be used at any time.

  When the write transfer from the host computer is normally completed, the host director 10 instructs the disk director 30 to restart the interrupted transfer using the communication means 40.

  Upon receiving the instruction from the host director 10, the disk director 30 restarts the interrupted transfer using the EXOR engine 31, and newly writes the data D0n + 2 written before from the host computer, the data D0n before update, and the data before update. New parity data Pn + 2 is generated from the parity data Pn.

  Further, as another case when the cache page is in use, when WT = '0', PG = '1', and TYPE = '1', that is, by the disk director 30, the same as shown in FIG. Similarly, when data in a parity group (assumed to be 4 data + 1 parity here) exists in the cache and a transfer for generating new parity Pn + 1 from these data D0n + 1, D1n + 1, D2n + 1, D3n + 1 is activated. When the host director 10 updates the data D0n + 2 and restarts the transfer, a new parity Pn + 2 can be obtained.

It is a schematic block diagram of a disk array device equipped with a cache memory. It is a figure for demonstrating the parity production | generation when all the newest data exist on a cache. It is a figure which shows the management information on a cache memory. It is a figure for demonstrating a normal parity production | generation image (type 0).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Host interface 10, 11 Host director 20 Cache memory 30 Disk director 31 EXOR engine 40 Communication means 4-8 Disk apparatus

Claims (2)

In a disk array device that uses cache memory to increase processing speed and generate parity data, even if the cache page that was hit by write is in use, the corresponding data is used for parity data generation. For example, the disk array device can write to the cache page in the same manner as a normal write hit operation. 2. The disk array device according to claim 1, wherein the cache memory has a management area for managing the cache page, and the management area has a WT flag, a MOD flag, a PG flag, and a TYPE flag.

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