JP2006268518A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable embedding of a debug instruction in a plurality of instruction addresses by adding little HW. <P>SOLUTION: A DAA (branch destination address array) 13 is a memory for storing the branch destination address of a branch instruction stored in a BAA (branch instruction address array) 12 as a set to the instruction address of the branch instruction at a normal time and storing an instruction word desired to be used for debugging as a set to the instruction address stored in the BAA 12 at the time of debugging, receiving and the branch destination address or the instruction word for debugging through a signal line 114 and storing the branch destination address or the instruction word at the time of a store operation, and transmitting a past branch destination address or the instruction word for debugging from an entry shown by the lower-order bits of an instruction address transmitted from an IFAR (instruction prefetch address register) 11 through a signal line 106 to a predictive branch destination address register (PDAR) 17 through a signal line 110 at the time of a read operation. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that performs debugging using a branch history table.

  As conventional technologies, there are Patent Document 1 and Patent Document 2 as debug circuits using a branch history table. Each of these uses a virtual branch to execute a different instruction or change a microinstruction address to perform a different process, but these processes may require a branch destination memory space. A memory for holding the microinstruction for processing is required.

Japanese Patent Laid-Open No. 11-191071 Japanese Patent Laid-Open No. 11-167502

  Conventionally, when debugging is performed by rewriting an instruction word, the program is changed by software and rewritten. Therefore, even when performing simple data collection, etc., the program has to be changed every time, and the work is complicated.

  There is also a method of executing a debugging instruction for a specific instruction address on the HW. In that case, the number of debugging instruction words that can be embedded at the same time is small, or many debugging instructions are used. Dedicated memory is required to embed words.

  The information processing apparatus of the present invention includes a branch history table that stores debugging instructions.

  The present invention has the following effects.

  The first effect is that since the branch history table is used, it can be configured with a small amount of hardware.

  The second effect is that since a branch history table is used, debugging can be performed simultaneously on a plurality of instruction addresses.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 2, there is shown a configuration diagram of (1) a branch history table as one embodiment of the present invention.

  In FIG. 2, an instruction prefetch address register (IFAR) 11 receives an instruction address sent from the instruction prefetch control circuit (IFC) 1 via the signal line 101, and uses the lower bit as a memory address via the signal line 106. The branch instruction address array (BAA) 12, the branch destination address array (DAA) 13 and the information array (IA) 14 are sent to the comparison circuit 15 as the instruction address comparison information via the signal line 105. When the branch information is stored, it is sent to the BAA 12.

  The BAA 12 stores the upper address of the branch instruction sent from the IFAR 11 via the signal line 105 in the entry indicated by the lower bit of the instruction address sent from the IFAR 11 via the signal line 106 during the instruction address storing operation. In operation, the upper bits of the instruction address stored in the entry indicated by the lower bits of the instruction address sent from the IFAR 11 via the signal line 106 are sent to the comparison circuit 105 via the signal line 108.

  The DAA 13 normally stores the branch destination address paired with the instruction address of the branch instruction stored in the BAA 12, and stores the instruction word to be used for debugging paired with the instruction address stored in the BAA 12 during debugging. At the time of storage operation, the branch destination address or the branch destination address held in the write branch destination address register (WDAR) 19 in the entry indicated by the lower bit of the instruction address sent from the IFAR 11 via the signal line 106 An instruction word for debugging is received and stored via the signal line 114, and at the time of a read operation, from the entry indicated by the lower bits of the instruction address sent from the IFAR 11 via the signal line 106, a past branch destination address or Predictive branch destination address register (PDAR) for debugging instruction word via signal line 110 And it sends it to the 7.

  The information array (IA) 14 is a memory indicating whether the information stored in the DAA 13 is a predicted branch destination address or a debug instruction word, and is sent from the write information register (IAR) 20 via the signal line 115 at the time of writing. The stored information is stored in the entry indicated by the lower bit of the instruction address indicated by IFAR11 via the signal line 106, and at the time of reading, the stored content is indicated by the lower bit of the instruction address indicated by IFAR11 via the signal line 106. The data is sent from the entry to the read information register (RIR) 18 via the read signal line 111.

  The comparison circuit 15 compares the read instruction address with the address stored in the branch history table at the time of instruction read. The comparison circuit 15 compares the upper bits of the instruction address sent from the IFAR 11 via the signal line 105 and the signal. The high-order bits of the stored instruction address sent from the BAA 12 via the line 108 are compared, and information on whether or not they match is sent to the branch hit register (BHR) 16 via the signal line 109.

  The BHR 16 is a register indicating whether or not an address matching the instruction fetch address is found in the branch history table at the time of fetching an instruction, and is stored in the instruction fetch address sent from the comparison circuit 15 via the signal line 109 and the branch history. The comparison result with the command address is received and sent to the IFC 1 via the signal line 102.

  The PDAR 17 is a register that receives the predicted branch destination address or debug instruction word paired with the BHR 16, receives the predicted branch destination address or debug instruction word sent from the DAA 13 via the signal line 110, and receives the signal line The data is sent to the IFC 1 and the instruction buffer (IB) 3 via 103.

  The RIR 18 is a register indicating whether the data held in the BHR 16 is a predicted branch destination address or a debug instruction word, and receives information on the predicted branch destination address or the debug instruction word sent from the IA 14 via the signal line 111. Whether the predicted branch destination address or the instruction word for debugging is stored is sent to IFC1 and IB3 via the signal line 104.

  The WDAR 19 is a register for holding data when rewriting information stored in the DAA. The WDAR 19 receives a branch destination address or a debug instruction word sent from the IFC 1 through the signal line 112, and receives the DAA 13 through the signal line 114. To send.

  The WIR 20 is a register that holds data when the information stored in the IA is rewritten. Via the signal line 115, information on whether the data held in the WDAR 19 is a branch destination address or a debug instruction word is sent to the IA 14. Send it out.

  The configuration of the embodiment has been described in detail above. FIG. 1 is a block diagram showing the overall configuration. FIG. 3 is a block diagram showing an example of the configuration of IB3.

  Next, the operation of the best mode for carrying out the present invention will be described with reference to the drawings.

  Next, the operation during debugging of the branch history table of FIG. 2 will be briefly described.

  In the figure, at the time of debugging operation, the debug target address and the instruction word to be executed at the time of debugging are stored in BAA12 and DAA13, and the content indicating that the data stored in BAA12 and DAA13 is debug information is stored in the same entry of IA14. At the time of instruction fetch, the instruction address is set in IFAR 11, the contents thereof are compared with the instruction address stored in BAA 12, and the result is sent to BHR 16 via signal line 109. When the instruction address held in the IFAR 11 is a debug target, the instruction word to be executed during debugging stored in the DAA 13 is sent to the signal line 110, held in the PDAR 17, and sent from the IA 14 via the signal line 111. Information indicating that it is debug information is sent to the RIR 18. As a result, the debug instruction word stored in the branch history table (BHT) 2 is read out and transmitted.

The block diagram which shows the whole of the best form for implementing this invention. The block diagram which shows the structure of a branch history table. The block diagram which shows the structure of an instruction buffer.

Explanation of symbols

1 Instruction prefetch control circuit (IFC)
2 Branch history table (BHT)
3 Instruction buffer (IB)
11 IFAR
12 BAA
13 DAA
14 IA
15 Comparison circuit 16 BHR
17 PDAR
18 Read information register (RIR)
19 WDAR
20 Write information register (IAR)

Claims (1)

An information processing apparatus comprising a branch history table for storing debugging instructions.

Images