JP2006261557A - Substrate for package - Google Patents
Substrate for package Download PDFInfo
- Publication number
- JP2006261557A JP2006261557A JP2005079752A JP2005079752A JP2006261557A JP 2006261557 A JP2006261557 A JP 2006261557A JP 2005079752 A JP2005079752 A JP 2005079752A JP 2005079752 A JP2005079752 A JP 2005079752A JP 2006261557 A JP2006261557 A JP 2006261557A
- Authority
- JP
- Japan
- Prior art keywords
- coaxial cable
- insulating resin
- package substrate
- package
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
本発明は、高周波半導体素子を実装して高周波信号を低損失で伝送することを可能にするパッケージ用基板に関する。 The present invention relates to a package substrate that can mount a high-frequency semiconductor element and transmit a high-frequency signal with low loss.
近年の情報通信分野において、高速且つ大容量化は重要な課題であり、情報伝送量が比較的大きいマイクロ波帯、さらには、30GHz以上のミリ波帯が積極的に利用されつつある。 In the information communication field in recent years, high speed and large capacity are important issues, and a microwave band having a relatively large amount of information transmission and a millimeter wave band of 30 GHz or more are being actively used.
このような高周波での通信を行なう無線基地局や、無線端末には、高周波ICを実装したマイクロ波パッケージやミリ波パッケージが用いられ、また、情報通信以外の分野に於いても、車両の衝突防止等を目的とする車載用レーダ(ミリ波レーダ)や計測センサなどにはミリ波帯が利用されている。 For such wireless base stations and wireless terminals that perform high-frequency communication, microwave packages and millimeter-wave packages with high-frequency ICs are used, and vehicle collisions also occur in fields other than information communication. The millimeter wave band is used for in-vehicle radar (millimeter wave radar) and measurement sensors for the purpose of prevention.
このような状況に於いて、高周波での電気特性の維持に加え、高い量産性と低コスト性とを有するICパッケージの実現が望まれている。 Under such circumstances, it is desired to realize an IC package having high mass productivity and low cost in addition to maintaining electrical characteristics at high frequencies.
通常、ミリ波帯における半導体素子(ICチップ)を実装したミリ波パッケージには、半導体素子どうしの接続、或いは、半導体パッケージとアンテナとの接続の為、低損失な伝送線路が必要となる。 Usually, a millimeter-wave package on which a semiconductor element (IC chip) in the millimeter-wave band is mounted requires a low-loss transmission line for connecting the semiconductor elements or connecting the semiconductor package and the antenna.
一般に、高周波信号の信号線には、主にマイクロストリップ線路、同軸配線、導波管を接続して用い、回路基板に於ける同一平面上でマイクロストリップ線路の一端に半導体素子を実装し、また、アンテナを装備する場合には、他端に於いてマイクロストリップ線路と同軸−導波管変換するようになっていて、信号は導波管を伝搬して、導波管に接続されたアンテナから放射される。 Generally, a microstrip line, a coaxial wiring, and a waveguide are mainly used for a signal line of a high frequency signal, and a semiconductor element is mounted on one end of the microstrip line on the same plane on the circuit board. When the antenna is equipped, the other end is coaxial-waveguide-converted with the microstrip line, and the signal propagates through the waveguide and is transmitted from the antenna connected to the waveguide. Radiated.
図9は従来の高周波半導体パッケージの一例を表す要部切断側面図であり、図から明らかなように、パッケージ用基板11の一面側に発振回路(voltage controlled oscillator:VCO)12が搭載され、そして、同じ平面上にマイクロ波集積回路(monolithic microwave integrated circuit:MMIC)13がAuバンプ14を介して搭載され、両者はAuワイヤ15及び電極/伝送線路16により電気的な接続をとっている。また、同じ平面上に設けられて、マイクロ波集積回路13と電極/伝送線路17、ビア18、伝送線路19を介して接続された導波管20がアンテナ21に結ばれ、全体がハーメチックシールなどのキャン封止部22で封止されている。
FIG. 9 is a cutaway side view showing an example of a conventional high-frequency semiconductor package. As is clear from the figure, an oscillation circuit (Voltage Controlled Oscillator: VCO) 12 is mounted on one surface side of the
この従来例で、信号の伝送は、発振回路12→Auワイヤ15→電極/伝送線路16→Auバンプ14→マイクロ波集積回路13→Auバンプ14→電極/伝送線路17→ビア18→伝送線路19→同軸−導波管変換(ビア)20→アンテナ21という順序で行なわれる。
In this conventional example, the signal is transmitted by the
マイクロ波帯やミリ波帯では、伝送損失を少なくするため、できるだけ伝送線路長を短くすることが望ましい。しかしながら、図9に見られるように回路素子をマイクロストリップ線路に平面実装する高周波半導体パッケージでは、伝送線路を構成する導体の断面形状が不連続となる部分、即ち、上記伝送順序の説明に於ける矢印(→)の部分で、特性インピーダンスに不整合が生じ、伝送損失の原因となる。そして、特性インピーダンスの不整合は、たとえば不連続部分での信号反射、Auワイヤやビアでの寄生インダクタンス成分の増大に起因する。 In the microwave band and the millimeter wave band, it is desirable to shorten the transmission line length as much as possible in order to reduce transmission loss. However, as shown in FIG. 9, in the high-frequency semiconductor package in which the circuit elements are mounted on the microstrip line in a plane, the portion where the cross-sectional shape of the conductor constituting the transmission line is discontinuous, that is, in the description of the transmission order described above. In the portion indicated by the arrow (→), mismatch occurs in the characteristic impedance, which causes transmission loss. The mismatch in characteristic impedance is caused by, for example, signal reflection at discontinuous portions and increase in parasitic inductance components at Au wires and vias.
また、信号の伝送線路は、マイクロストリップ線路を平面実装する構造上、電磁妨害や電磁感受などの電磁干渉の影響を受けやすい。さらに、半導体素子間のアイソレーションを確保する為、パッケージの小型化にも限界がある。 In addition, the signal transmission line is susceptible to electromagnetic interference such as electromagnetic interference and electromagnetic susceptibility due to the structure in which the microstrip line is mounted in a plane. Furthermore, there is a limit to downsizing the package in order to ensure isolation between semiconductor elements.
ところで、多層配線基板において、同軸構造のスルーホール接続により、配線長を短縮する構成が知られている(例えば、特許文献1参照)。即ち、多層配線基板に、金属が充填された外層スルーホールと内層スルーホールから成る二重円筒形の同軸スルーホールを形成し、内層スルーホールの真上にフィルドビアを配設して配線長を短縮する。 By the way, the structure which shortens wiring length is known by the through-hole connection of a coaxial structure in a multilayer wiring board (for example, refer patent document 1). In other words, a double-cylindrical coaxial through hole consisting of an outer layer through hole and an inner layer through hole filled with metal is formed on the multilayer wiring board, and a filled via is disposed directly above the inner layer through hole to shorten the wiring length. To do.
然しながら、特許文献1に見られる構成は、多層配線基板の一面に実装された半導体素子(ICチップ)と、多層配線基板のもう他面に接続されたドータボードとを同軸スルーホールを介して電気的に接続することを目的とするものであり、両面実装半導体パッケージに関係するものではない。また、高周波伝送における伝送損失ついては何も考慮していない。
However, the configuration found in
また、多層誘電体基板の両面に高周波回路部品を搭載する高周波回路モジュールにおいて、基板の垂直方向に延びる同軸構造のビアホールを伝送線路の一部に用いることで、ミリ波用伝送線路での損失を低減する構成が提案されている(例えば、特許文献2参照)。 In addition, in a high-frequency circuit module in which high-frequency circuit components are mounted on both sides of a multilayer dielectric substrate, loss in the millimeter-wave transmission line can be reduced by using a coaxial via hole extending in the vertical direction of the substrate as a part of the transmission line. The structure which reduces is proposed (for example, refer patent document 2).
この構成は、伝送線路の一部として基板を貫通する垂直同軸ビアを用いてはいるが、同軸ビアから基板の反対側の面に位置する別の高周波回路素子への伝送にマイクロストリップ線路を用いている。従って、この場合も結局は図9について説明した従来の技術と同様、ビアとマイクロストリップ線路との間で導体の断面形状が不連続になり、特性インピーダンスに不整合が生じる。 This configuration uses a vertical coaxial via that penetrates the substrate as part of the transmission line, but uses a microstrip line for transmission from the coaxial via to another high frequency circuit element located on the opposite side of the substrate. ing. Accordingly, in this case as well, the cross-sectional shape of the conductor becomes discontinuous between the via and the microstrip line as in the conventional technique described with reference to FIG. 9, resulting in mismatch in characteristic impedance.
前記したように従来の技術に依る高周波半導体パッケージに於いては、半導体チップ間の高周波信号の伝送を行うための配線構造に問題があり、特に、マイクロ波帯およびミリ波帯では伝送損失を少なくしなければならない。 As described above, the conventional high-frequency semiconductor package has a problem in the wiring structure for transmitting a high-frequency signal between semiconductor chips, and in particular, transmission loss is reduced in the microwave band and the millimeter wave band. Must.
通常、マイクロ波帯およびミリ波帯の半導体パッケージに於いて、これらに用いるパッケージ用基板は、配線の構造上、ビアなど立体構造による寄生インダクタンスの影響を抑えるために、半導体チップを平面実装している。 Usually, in the semiconductor package of the microwave band and the millimeter wave band, the package substrate used for these has a semiconductor chip mounted in a plane in order to suppress the influence of the parasitic inductance due to the three-dimensional structure such as the via on the wiring structure. Yes.
その場合に用いられるマイクロストリップ線路やコプレーナウェーブガイド線路など、同一平面上にある配線はシールドされていないのが普通であり、1GHz以上のマイクロ波及び30GHz以上のミリ波を扱う高周波信号では、配線長さに対して波長が有意となるため、配線自体がアンテナとして機能することで電磁波の授受により配線間に干渉が発生し、機器の動作に不具合を発生させる原因となっている。 The wiring on the same plane, such as the microstrip line and coplanar waveguide line used in that case, is usually not shielded. For high-frequency signals that handle microwaves of 1 GHz or higher and millimeter waves of 30 GHz or higher, wiring Since the wavelength becomes significant with respect to the length, the wiring itself functions as an antenna, causing interference between the wirings due to the transmission and reception of electromagnetic waves, which causes a malfunction in the operation of the device.
そこで、寄生インダクタンスを発生させずに配線間をシールドする配線構造が必要となるのであるが、その配線の構造上、伝送線路にバンプ−配線−ビアなど境界で断面形状が不連続となる部分が形成され、従って、配線による寄生容量の影響で特性インピーダンスの不整合が生じて伝送損失を発生し易くなり、さらに、電磁妨害や電磁感受などの電磁干渉の影響を受け易いという問題があった。
本発明では、寄生インダクタンスや寄生容量の影響が小さく、従って、伝送損失が少なく、そして、電磁環境両立性(electoro magnetic compatibility:EMC)に優れた高周波半導体パッケージ用基板を提供しようとする。 The present invention seeks to provide a substrate for a high-frequency semiconductor package that is less affected by parasitic inductance and parasitic capacitance, therefore has less transmission loss, and that is excellent in electromagnetic environment compatibility (EMC).
本発明に依るパッケージ用基板に於いては、シールド被覆が表出されている同軸ケーブルを嵌挿可能な径の孔が設けられた導電性金属からなるコア基板と、先端が前記孔に嵌挿され、且つ、シールド被覆が孔の周縁に電気接続されてなる同軸ケーブルと、前記同軸ケーブルの先端が嵌挿されたコア基板の表裏を埋め、且つ、表面側が同軸ケーブルの先端と同一平面をなす絶縁性樹脂と、前記絶縁性樹脂と同一平面に表出された同軸ケーブル先端に於ける中心導体の端面に形成された電極パッドとを備えることが基本になっている。 In a package substrate according to the present invention, a core substrate made of a conductive metal provided with a hole having a diameter into which a coaxial cable with a shield coating exposed can be inserted, and a tip inserted into the hole. And a coaxial cable having a shield coating electrically connected to the periphery of the hole, and the front and back surfaces of the core substrate into which the front end of the coaxial cable is inserted, and the surface side is flush with the front end of the coaxial cable. It is basically provided with an insulating resin and an electrode pad formed on the end face of the central conductor at the end of the coaxial cable exposed on the same plane as the insulating resin.
パッケージ用基板に実装される高周波半導体素子どうしを同軸ケーブルでシールド接続することが容易であり、しかも、伝送損失が少なく、且つ、電磁環境両立(EMC)性に優れた小型のパッケージ用基板を実現できる。 A high-frequency semiconductor device mounted on a package substrate can be easily shielded with a coaxial cable, and a small package substrate with low transmission loss and excellent electromagnetic compatibility (EMC) has been realized. it can.
図1乃至図6は本発明に依るパッケージ用基板を製造するプロセスの第1例を説明する為の工程要所に於けるパッケージ用基板を表す要部分解斜面図(図1)、要部切断側面図(図2乃至図6)であり、以下、これ等の図を参照しつつ説明する。 FIG. 1 to FIG. 6 are fragmentary exploded perspective views (FIG. 1) showing the package substrate at the main points for explaining the first example of the process for manufacturing the package substrate according to the present invention. FIG. 2 is a side view (FIGS. 2 to 6), which will be described below with reference to these drawings.
図1参照
(1)
導電性金属からなるコア基板1を用意し、コア基板1には、絶縁外被を除去してシールド被覆2Aを表出した同軸ケーブル2を挿通可能な径をもつ孔1Aを形成する。尚、記号2Bは同軸ケーブル2の中心導体を指示している。
See Fig. 1 (1)
A
図2参照
(2)
コア基板1の孔1Aに同軸ケーブル2の先端を挿通し、孔1Aの周縁と同軸ケーブル2のシールド被覆2Aとをはんだ付けし、コア基板1とシールド被覆2Aとを電気的な接地接続と機械的な固着を行う。
See Figure 2 (2)
The tip of the
図3参照
(3)
同軸ケーブル2からなる配線を取り付けたコア基板1の裏面及び表面を絶縁性樹脂3で埋め込んで一体化する。尚、絶縁性樹脂3としては、エポキシ樹脂など熱硬化性の樹脂材料を用いることができる。
See Fig. 3 (3)
The back surface and the front surface of the
図4参照
(4)
表面側の絶縁性樹脂3の研磨を行い、同軸ケーブル2の中心導体2B、シールド被覆2Aをコア基板1の表面と同一平面とする。
See Fig. 4 (4)
The
図5参照
(5)
表出された同軸ケーブル2の端面に於ける中心導体2B上にめっき法を適用してAu、Ag、Cuなどから選択された材料からなる電極パッド4を形成する。尚、電極パッド4を形成するには、めっき法に代えて導電性ぺーストの印刷法を用いても良い。
Refer to FIG. 5 (5)
An electrode pad 4 made of a material selected from Au, Ag, Cu, or the like is formed on the
図6参照
(6)
半導体チップ5をフリップチップして、そのバンプを電極パッド4に対向させ、ボンディングを行って実装する。尚、半導体チップ5のバンプとしては、はんだバンプや金バンプを用いる。
See FIG. 6 (6)
The
図7及び図8は本発明に依るパッケージ用基板を製造するプロセスの第2例を説明する為の工程要所に於けるパッケージ用基板を表す要部切断側面図であり、以下、これ等の図を参照しつつ説明する。尚、さきの第1例に於いて、図1乃至図4について説明した製造プロセス、即ち、コア基板1を用意してから、同軸ケーブル2の中心導体2B、シールド被覆2Aをコア基板1の表面と同一平面となるように研磨するまでの工程は、この第2例でも同じであるから省略し、次の段階から説明する。
FIGS. 7 and 8 are cut side views of the main part showing the package substrate at the process points for explaining the second example of the process for manufacturing the package substrate according to the present invention. This will be described with reference to the drawings. In the first example, the manufacturing process described with reference to FIGS. 1 to 4, that is, the
図7参照
(1)
表出された同軸ケーブル2の端面に於ける中心導体2B上にめっき法を適用してAu、Ag、Cuなどから選択された材料からなる電極パッド4を形成すると共にシールド被覆2Aと接続された電極パッド4Aを形成する。尚、電極パッド4並びに4Aを形成するには、めっき法に代えて導電性ぺーストの印刷法を用いても良い。
See Fig. 7 (1)
An electrode pad 4 made of a material selected from Au, Ag, Cu, etc. is formed on the
図8参照
(2)
半導体チップ5をフリップチップして、そのバンプを電極パッド4に対向させ、また、電極パッド4及び電極パッド4Aに同軸ケーブル−導波管変換器6を介して導波管アンテナ7を対向させてボンディングを行って実装する。尚、ここで用いるバンプもはんだバンプや金バンプを用いて良い。
Refer to FIG. 8 (2)
The
1 コア基板
1A 孔
2 同軸ケーブル
2A シールド被覆
3 絶縁性樹脂
4 電極パッド
1
Claims (3)
先端が前記孔に嵌挿され、且つ、シールド被覆が孔の周縁に電気接続されてなる同軸ケーブルと、
前記同軸ケーブルの先端が嵌挿されたコア基板の表裏を埋め、且つ、表面側が同軸ケーブルの先端と同一平面をなす絶縁性樹脂と、
前記絶縁性樹脂と同一平面に表出された同軸ケーブル先端に於ける中心導体の端面に形成された電極パッドと
を備えてなることを特徴とするパッケージ用基板。 A core substrate made of a conductive metal provided with a hole having a diameter into which a coaxial cable having a shield coating exposed can be inserted;
A coaxial cable having a tip inserted into the hole, and a shield coating electrically connected to the periphery of the hole;
Filling the front and back of the core substrate into which the tip of the coaxial cable is inserted, and an insulating resin whose surface side is flush with the tip of the coaxial cable;
A package substrate, comprising: an electrode pad formed on an end face of a central conductor at a front end of a coaxial cable exposed on the same plane as the insulating resin.
を備えてなることを特徴とする請求項1記載のパッケージ用基板。 2. A semiconductor chip comprising bumps electrically connected to electrode pads formed on an end face of a central conductor at the end of a coaxial cable exposed on the same plane as the insulating resin. The package substrate according to 1.
を特徴とする請求項1記載のパッケージ用基板。 An antenna comprising a waveguide connected to an electrode pad formed on the end face of a central conductor at the end of a coaxial cable exposed on the same plane as the insulating resin via a coaxial-waveguide converter The package substrate according to claim 1, further comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005079752A JP4768292B2 (en) | 2005-03-18 | 2005-03-18 | Package substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005079752A JP4768292B2 (en) | 2005-03-18 | 2005-03-18 | Package substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006261557A true JP2006261557A (en) | 2006-09-28 |
JP4768292B2 JP4768292B2 (en) | 2011-09-07 |
Family
ID=37100424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005079752A Active JP4768292B2 (en) | 2005-03-18 | 2005-03-18 | Package substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4768292B2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0537211A (en) * | 1991-07-26 | 1993-02-12 | Nec Corp | Coaxial waveguide converter circuit |
JP2001521311A (en) * | 1997-10-20 | 2001-11-06 | エリクソン インコーポレイテッド | Small antenna structure including balun |
JP2003273496A (en) * | 2002-03-20 | 2003-09-26 | Fujitsu Ltd | Wiring board and method of manufacturing the same |
JP2004007176A (en) * | 2002-05-31 | 2004-01-08 | Toko Inc | Waveguide antenna |
-
2005
- 2005-03-18 JP JP2005079752A patent/JP4768292B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0537211A (en) * | 1991-07-26 | 1993-02-12 | Nec Corp | Coaxial waveguide converter circuit |
JP2001521311A (en) * | 1997-10-20 | 2001-11-06 | エリクソン インコーポレイテッド | Small antenna structure including balun |
JP2003273496A (en) * | 2002-03-20 | 2003-09-26 | Fujitsu Ltd | Wiring board and method of manufacturing the same |
JP2004007176A (en) * | 2002-05-31 | 2004-01-08 | Toko Inc | Waveguide antenna |
Also Published As
Publication number | Publication date |
---|---|
JP4768292B2 (en) | 2011-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6847276B2 (en) | Radio frequency circuit module on multi-layer substrate | |
EP3358670A1 (en) | Multilayer dielectric substrate and semiconductor package | |
US8436450B2 (en) | Differential internally matched wire-bond interface | |
JPWO2011118544A1 (en) | Wireless module and manufacturing method thereof | |
JP2001267814A (en) | Wiring board and connection structure between wiring board and waveguide | |
EP1081989A2 (en) | High frequency wiring board and its connecting structure | |
JP2017163385A (en) | Electronic device and electronic equipment | |
US6998292B2 (en) | Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier | |
JP3631667B2 (en) | Wiring board and its connection structure with waveguide | |
JP3420913B2 (en) | Circuit board for mounting semiconductor chip, package for storing semiconductor chip, and semiconductor device | |
JP4883010B2 (en) | Electronic component package | |
JP3217677B2 (en) | High frequency semiconductor device | |
US20050174190A1 (en) | Connection structure of high frequency lines and optical transmission module using the connection structure | |
JP4448461B2 (en) | Manufacturing method of semiconductor package | |
JP3619396B2 (en) | High frequency wiring board and connection structure | |
JP4768292B2 (en) | Package substrate | |
JP5112962B2 (en) | package | |
JP3140385B2 (en) | High frequency semiconductor device | |
JP3462062B2 (en) | Connection structure of high-frequency transmission line and wiring board | |
JP2011172173A (en) | Millimeter wave circuit module and millimeter wave transceiver employing the same | |
US7105924B2 (en) | Integrated circuit housing | |
JP3704440B2 (en) | High frequency wiring board connection structure | |
JP3181036B2 (en) | Mounting structure of high frequency package | |
JP4737192B2 (en) | Connection structure of two microstrip lines and mounting structure of integrated circuit chip on mounting board using housing | |
JP4127589B2 (en) | High frequency semiconductor device package and high frequency semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080121 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100311 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100427 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100615 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110329 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110525 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110614 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110616 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4768292 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140624 Year of fee payment: 3 |