JP2006261543A - Semiconductor device package and relay printed board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the efficiency of a wiring pattern in a land array area on a mother board without shortening the land diameter of each land in the land array area. <P>SOLUTION: A relay board 30 is constituted of forming lands 31a having the same arrays as those of solder balls 12b of a semiconductor device 10 on a surface side layer 30a, forming solder balls 32b having the same arrays as those of lands 21a of a mother board 20 and connected to the respective lands 31a through through-holes, and forming a by-pass wiring pattern extended from the solider ball 32b counted by the prescribed number of solder balls from the outer edge of the solder ball array area up to a by-pass wiring solder ball 35b on a rear side layer 30b. In the case of packaging the semiconductor device 10 through the relay board 30, the by-pass wiring pattern formed on the layer 30b of the relay board 30 is electrically connected to the wiring pattern of the mother board 20 through the by-pass wiring solder balls 35b and by-pass wiring lands 25a of the mother board 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device mounting package in which a ball grid array type semiconductor device is mounted on a mother board, and more specifically, the land arrangement without reducing the land diameter of each land in the land arrangement area of the mother board. The present invention relates to a semiconductor device mounting package capable of improving the efficiency of a wiring pattern in a region and a relay printed wiring board used therefor.

  A package in which a ball grid array (BGA) type semiconductor device is mounted on a printed wiring board, which is a motherboard of an information processing device or the like, is known.

  In this type of package, the BGA type semiconductor device has a structure in which spherical solders (hereinafter referred to as solder balls) functioning as leads on the back side thereof are arranged in a lattice pattern, while the motherboard has, for example, a figure on the front side. As shown in FIG. 11, the lands 61a corresponding to the connection terminals with the solder balls forming the lattice arrangement in the solder ball arrangement region of the BGA type semiconductor device are arranged in the same arrangement (grid arrangement) with the solder balls. Forming.

  Then, the solder balls are melted and fixed in a state where the solder balls in the solder ball arrangement region of the semiconductor device are in contact with the lands 61a in the land arrangement region 601a on the surface 60a side of the mother board 60. The semiconductor device can be mounted on the surface 60 a of the mother board 60.

  As for the structure on the mother board 60 side, in order to connect the mounted semiconductor device to each component, circuit, etc. on the mother board 60, the wiring pattern extends from each land 61a in the land array area 601a to the outside of the area. (See FIG. 11) 67a needs to be formed.

  In this case, if the number of lands is large, the wiring patterns 67a are inevitably crowded to be drawn out from the lands 61a in the land array area 601a to the outside of the land array area 601a.

  On the other hand, the pattern width of the wiring pattern 67a in the land array region 601a of the mother board 60 may be limited due to the narrow pitch interval between the land patterns for connecting the semiconductor device, the impedance control of the transmission line, and the like.

  In addition, due to the structure of the mother board 60, there are cases where switching of wiring to other layer surfaces by through-hole vias for improving signal integrity and reducing EMI noise may be restricted. In this case, wiring is performed within the land array region 601a. In the case where the pattern 61a has to be routed and the land arrangement pitch is limited as described above, the areas deeper from the outer edge of the land arrangement area 601a (areas 603a1, 603a2, and 603a3 in FIG. 11). 603a4), it is difficult to pull out the wiring pattern 67a from the land 61a, and the wiring pattern efficiency is remarkably lowered.

As a countermeasure to prevent the efficiency of the wiring pattern in such a land array region, the following Patent Document 1 describes a land diameter for connection to a ball grid array (BGA) type semiconductor device or the like in a printed wiring board (motherboard) as compared with a normal one. A technique for increasing the efficiency of pattern wiring on a printed wiring board by reducing the size is disclosed.
JP 2003-78240 A

  However, according to the technique described in Patent Document 1, since the land for connecting the BGA type semiconductor device on the motherboard is formed with a smaller diameter than usual, the land having the small diameter and the BGA type which is the side to be connected are formed. There was a problem that solderability between semiconductor devices deteriorated.

  In addition, if the land diameter is reduced to a certain level to ensure solderability to a certain level, the number of wiring patterns cannot be increased, and the land from the land in the land arrangement area on the motherboard (mother board) can be pulled out from the land. In particular, there is a problem that a reduction in wiring pattern efficiency is inevitable, such as difficulty.

  The present invention solves the above-described problems, and a semiconductor device mounting package capable of improving the wiring pattern efficiency in the land array region without reducing the land diameter of each land in the land array region on the mother board, and the same It is an object of the present invention to provide a relay printed wiring board used for the above.

  In order to achieve the above object, a first aspect of the present invention is directed to a ball grid array type semiconductor device in which solder balls are arranged in a grid pattern, and a mother board in which lands for solder joining are formed in the same arrangement as the solder balls. A relay printed wiring board that is inserted between the semiconductor device and the semiconductor device to be mounted on the mother board, wherein the solder ball of the semiconductor device is disposed on a first surface facing the solder ball arrangement region of the semiconductor device. And forming solder balls in the same arrangement as the lands of the mother board on the second surface facing the land arrangement area of the mother board, and forming each land on the first face. The structure is such that the lands and the solder balls on the second surface corresponding to the lands can be electrically connected to each other by through-holes. Characterized in that it has a land or any detour wiring patterns formed by extending from the solder ball to the appropriate land or a solder ball array region outside of the second solder ball array region on the surface.

  According to a second aspect of the present invention, in the first aspect of the invention, a solder ball for bypass wiring is formed outside the solder ball arrangement region on the second surface, and the solder ball arrangement region on the second surface is formed. The detour wiring pattern extending from an inner solder ball, which is a predetermined number of solder balls inside the outer edge of the region, to the detour wiring solder ball, is formed.

  According to a third aspect of the present invention, in the first aspect of the invention, a land for a detour wiring is formed outside the land arrangement area on the first surface, and the land arrangement area on the first surface is formed. The detour wiring pattern extending from the inner land, which is a predetermined number of lands inside the outer edge, to the detour wiring land is formed, and the detour wiring in the first surface is outside the solder ball arrangement region in the second surface. It is characterized in that a solder ball for bypass wiring connected by a through hole that can be electrically connected to the land for use is formed.

  The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the solder balls in the solder ball arrangement region on the second surface include a core material, and the solder balls of the semiconductor device It is characterized by being formed of a high melting point solder having a higher melting point.

  According to a fifth aspect of the present invention, there is provided a ball grid array type semiconductor device in which solder balls are arranged in a grid, a mother board in which lands for solder joining are formed in the same arrangement as the solder balls, and the solder balls of the semiconductor device A land having the same arrangement as the solder balls of the semiconductor device is formed on the first surface facing the arrangement region, and the land of the mother substrate is formed on the second surface facing the land arrangement region of the mother substrate. Forming the same arrangement, forming solder balls connected through through-holes that are electrically conductive with the corresponding lands of the first surface, and at least one of the first and second surfaces An arbitrary land in the land array region on the first surface or an arbitrary solder ball in the solder ball array region on the second surface is electrically connected to the wiring pattern on the mother board. And a relay printed wiring board formed by forming a bypass wiring pattern for connection to a semiconductor device, wherein the solder ball arrangement region of the semiconductor device faces the first surface of the relay printed wiring board Then, each solder ball in the solder ball array region and each land in the land array region on the first surface are soldered together, and the second surface of the relay printed wiring board is landed on the land of the mother substrate. Each solder ball in the solder ball array region on the second surface and each land in the land array region of the mother board are soldered to face each other.

  According to a sixth aspect of the present invention, in the fifth aspect of the present invention, a detour wiring land is formed outside the land arrangement area on the mother board, and the relay printed wiring board includes the land A solder ball for bypass wiring is formed outside the solder ball arrangement region on the second surface, and the solder ball for bypass wiring is formed from an inner solder ball which is a predetermined number of solder balls inside the outer edge of the solder ball arrangement region. The bypass wiring pattern is formed to extend to the solder printed circuit board, and the bypass wiring solder ball on the second surface of the relay printed wiring board and the bypass wiring land of the mother board are solder-bonded when the semiconductor device is mounted. It is characterized by being.

  The invention according to claim 7 is the invention according to claim 5, wherein a land for bypass wiring is formed outside the land arrangement area on the mother board, and the relay printed wiring board is The detour wiring pattern that forms a detour wiring land outside the land array area on the first surface and extends from an inner land that is a predetermined number of lands inside the area outer edge of the land array area to the detour wiring land. And forming a bypass wiring solder ball connected to the bypass wiring land on the first surface by a through-hole that is electrically conductive to the outside of the solder ball arrangement region on the second surface. When the semiconductor device is mounted, the bypass wiring solder balls on the second surface of the relay printed wiring board and the bypass wiring of the mother board And lands, characterized in that it is solder-bonded.

  According to the present invention, a relay printed wiring board is inserted between a BGA type semiconductor device and a mother board, and the semiconductor device is mounted on the mother board. The relay printed wiring board has a solder ball arrangement region of the semiconductor device. A land having the same arrangement as the solder balls of the semiconductor device is formed on the first surface opposite to the first substrate, and a land having the same arrangement as the land of the mother substrate is formed on the second surface opposite to the land arrangement region of the mother substrate. In addition to forming solder balls, a structure is provided in which each land on the first surface and each solder ball on the second surface corresponding to each land can be electrically connected by a through hole. It extends from any land in the land array area on one surface or from any solder ball in the solder ball array area on the second surface to the outside of the corresponding land or solder ball array area. Those having a bypass wiring patterns.

  According to this structure, when the semiconductor device is mounted on the mother board via the relay printed wiring board, the detour wiring pattern provided on the relay printed wiring board is used, for example, the second surface of the relay printed wiring board. Can be connected to a wiring pattern outside the land array region on the mother board, and on the mother board, the land array on the mother board can be connected. It is necessary to form a wiring pattern for drawing out from an inner land (a land corresponding to the inner solder ball on the second surface of the relay printed wiring board) which is a predetermined number of lands inside the outer edge of the area to the outside of the land arrangement area. The wiring pattern efficiency can be improved accordingly.

  Further, since the wiring pattern efficiency is improved, it is not necessary to reduce the land diameter of each land in the land array region on the mother board. Therefore, between each land in the land array region and each corresponding solder ball of the semiconductor device. Good solderability.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a conceptual diagram showing a side cross-sectional structure of a semiconductor device mounting package according to the present invention.

  This package is a relay printed wiring board between a BGA type semiconductor device (hereinafter referred to as a semiconductor device) 10 and a printed wiring board (hereinafter referred to as a motherboard: a mother board in claims) 30 which is a motherboard of an information processing apparatus or the like. The semiconductor device 10 and the mother board 20 are electrically connected via the relay board 30 (hereinafter referred to as a relay board) 20.

  The semiconductor device 10 has a solder ball arrangement region in which solder balls 12b, which are spherical solders used as leads, are arranged in a lattice shape (matrix shape) on the back surface 10b (the surface facing the relay substrate 30 in FIG. 1). is doing.

  Both the mother board 20 and the relay board 30 are general multilayer printed wiring boards having two or more layers based on FR-4 or the like, and have printed wiring pattern layers on the front and back and inner layers.

  Among them, the mother board 20 has the same layer 20a on the surface (surface facing the relay board 30 in FIG. 1) as each solder ball 32b in the solder ball arrangement region of the relay board 30 described later (semiconductor device 10). The same as the solder balls 12b of FIG. 1). The land has a land arrangement region in which the lands 21a are arranged in a lattice pattern, and a printed wiring pattern is formed on the back layer 20b.

  The relay substrate 30 has a land arrangement region in which lands 31a having the same arrangement as the solder balls 12b of the semiconductor device 10 are formed in a layer 30a on the surface (front surface: first surface) side facing the semiconductor device 10, and a motherboard. A layer 30b on the surface (back surface: second surface) side facing 20 is provided with a solder ball arrangement region in which solder balls 32b having the same arrangement as the lands 21a of the mother board 20 are formed.

  Further, in the relay substrate 30, each land 31a in the land array region formed in the front surface layer 30a and each solder ball 32b in the solder ball array region formed in the back surface layer 30b correspond to each other. The structures to be electrically connected can be electrically connected by the through hole 33.

  Further, a solder ball 35b for bypass wiring is formed outside the arrangement region of the solder balls 32b on the layer 30b on the back surface side of the relay substrate 30, and on the other hand, the layer 20a on the front surface side of the mother board 20 is formed on the layer 20b of the relay substrate 30. By-pass wiring lands 25a each having an array corresponding to the bypass wiring solder balls 35b provided on the back layer 30b are formed.

  In the mounted state in FIG. 1, each solder ball 12b in the solder ball array region on the back surface 10b of the semiconductor device 10 and each land 31a in the land array region of the layer 20a on the surface side of the relay substrate 20 correspond to each other. They are soldered together.

  Further, between the mother boat 20 and the relay substrate 30, each land 21 a in the land array region of the layer 20 a on the surface side of the mother board 20, a bypass wiring land 25 a outside the land array region, and the back surface of the relay substrate 30. The solder balls 32b in the solder ball arrangement region of the side layer 30b and the solder balls 35b for the bypass wiring outside the solder ball arrangement region are soldered to each other corresponding to each other.

  Thus, in this package, each solder ball 12b of the semiconductor device 10 is connected to each land 31a of the layer 30a on the front surface side of the relay substrate 30 → each through hole 33 → each solder ball 32b of the layer 30b on the back surface → the motherboard 20 Is electrically connected to a wiring pattern formed on the surface 20a of the mother board 20 through the lands 21a of the surface 20a of the front surface.

  At this time, each bypass wiring solder ball 35b of the layer 30b on the back surface side of the relay board 30 and each bypass wiring land 25a of the layer 20a on the front surface side of the mother board 20 are also electrically connected. become.

  In addition, as will be described later (see FIG. 5), each bypass wiring solder ball 35b formed on the layer 30b on the back surface side of the relay substrate 30 is a predetermined number from the outer edge of the region in the solder ball arrangement region of the layer 30b. The inner (back side) solder ball 32b (referred to as an inner solder ball for convenience) is connected to a bypass wiring pattern formed on the layer 30b from outside the solder ball arrangement region.

  Thereby, in the mounting state shown in FIG. 1, each solder ball (inner solder ball) 12 b that is a predetermined number inside of the outer edge of the solder ball arrangement region on the back surface 10 b of the semiconductor device 10 is placed on the surface side of the relay substrate 30. Each land 31a corresponding to the layer 30a → each through hole 33 → each solder ball (inner solder ball) 32b on the back side layer 30b → detour wiring pattern → solder ball 35b for detour wiring → the layer 20a on the surface side of the motherboard 20 It is electrically connected to the wiring pattern formed on the layer 20a on the surface side of the mother board 20 through each bypass wiring land 25a.

  FIG. 2 is a conceptual diagram showing an exploded structure of the package in FIG.

  FIG. 3 is a diagram showing an external configuration of the layer 10b on the back surface side of the semiconductor device 10 as viewed from the direction of arrow A in FIG.

  4 is a diagram showing an external configuration of the surface layer 30a of the relay board 30 viewed from the direction of arrow B in FIG. 2, and FIG. 5 is a diagram of the relay board 30 viewed from the direction of arrow C in FIG. It is a figure which shows the external appearance structure of the layer 30b on the back side.

  FIG. 6 is a diagram showing an external configuration of the layer 20a on the surface side of the mother board 20 viewed from the direction of arrow D in FIG.

  In FIG. 3, for example, solder balls 12 b having a 9 × 9 matrix (lattice) arrangement are formed on the back surface side layer 10 b of the semiconductor device 10.

  In the solder ball array region 101b corresponding to the entire 9 × 9 matrix region, a central portion including nine solder balls (center solder balls) 12b formed in a 3 × 3 matrix array in the central portion. There are solder ball array regions 102b and inner solder ball array regions 103b1, 103b2, 103b3, and 103b4 each including three solder balls 12b formed at positions corresponding to the outer four sides of the central solder ball array region 102b. .

  Here, each solder ball (inner solder ball) 12b in the inner solder ball arrangement area 103b1, 103b2, 103b3, 103b4 is a predetermined number (three in this example) inside (back) from the outer edge of the solder ball arrangement area 101b. Side).

  In FIG. 4, lands 31 a having an array of 9 × 9 matrix are formed on the layer 30 a on the front surface side of the relay substrate 30, similarly to the solder balls 12 b on the layer 10 b on the back surface side of the semiconductor device 10.

  In the land array region 301a corresponding to the entire 9 × 9 matrix region, a central land array region including nine lands (central land) 31a formed in a 3 × 3 matrix array at the center thereof. There are 302a and inner land array regions 303a1, 303a2, 303a3 and 303a4 each including three lands 31a formed at positions corresponding to the four outer sides of the central land array region 302a.

  Here, each land (inner land) 31a in the inner land array areas 303a1, 303a2, 303a3, 303a4 is formed on the inner side (back side) by a predetermined number (three in this example) from the outer edge of the land array area 301a. It is what is done.

  In FIG. 5, solder balls 32b having a 9 × 9 matrix arrangement are formed on the layer 30b on the back surface side of the relay substrate 30 in the same manner as each land 31a in the land array region 301a in the layer 30a on the front surface side. ing.

  In the solder ball array region 301b corresponding to the entire 9 × 9 matrix region, a central portion including nine solder balls (center solder balls) 32b formed in a 3 × 3 matrix array in the central portion. There are solder ball arrangement regions 302b and inner solder ball arrangement regions 303b1, 303b2, 303b3, and 303b4 each including three solder balls 32b that are formed at positions corresponding to the outer four sides of the central solder ball arrangement region 302b. .

  Here, each solder ball (inner solder ball) 32b in the inner solder ball arrangement area 303b1, 303b2, 303b3, 303b4 is a predetermined number (three in this example) inside (back) from the outer edge of the solder ball arrangement area 301b. Side).

  Each solder ball 32 b in the solder ball arrangement region 301 b is connected to each corresponding land 31 a in the surface-side layer 30 a by a through hole 33.

  Further, in FIG. 5, on the layer 30b on the back surface side of the relay substrate 30, bypass wiring solder ball array regions 304b1, 304b2, each having three bypass wiring solder balls 35b formed outside the solder ball array region 301b. 304b3 and 304b4 exist.

  And between each detour wiring solder ball 35b in these detour wiring solder ball arrangement area 304b1, 304b2, 304b3, 304b4 and each inner solder ball 32b in inner solder ball arrangement area 303b1, 303b2, 303b3, 303b4 In each case, a bypass wiring pattern 39b is formed.

  Here, each solder ball 32b in the solder ball arrangement region 301b in the layer 30b on the back side of the relay substrate 30 and each detour wiring solder ball 35b outside the solder ball arrangement region 301b both include a core material, and The semiconductor device 10 is formed of a high melting point solder having a melting point higher than that of the solder balls 12b on the back surface 10b.

  In FIG. 6, the land 20a on the front surface side of the mother board 20 is a land having a 9 × 9 matrix arrangement, similar to the solder balls 32b in the solder ball arrangement region 301b in the layer 30b on the back surface side of the relay substrate 30. 21a is formed.

  In the land array region 201a corresponding to the entire 9 × 9 matrix region, a central land array region including nine lands (central land) 21a formed in a 3 × 3 matrix array at the center thereof. 202a and inner land array regions 203a1, 203a2, 203a3, 203a4 each including three lands 21a formed at positions corresponding to the outer four sides of the central land array region 202a.

  Here, each land (inner land) 21a in the inner land array area 203a1, 203a2, 203a3, 203a4 is formed on the inner side (back side) by a predetermined number (three in this example) from the outer edge of the land array area 201a. It is what is done.

  Further, in FIG. 6, on the layer 20a on the surface side of the mother board 20, there are detour wiring land array areas 204a1, 204a2, 204a3, 204a4 in which three detour wiring lands 25a are formed outside the land array area 201a. Exists.

  Here, the detour wiring lands 25a in the detour wiring land array areas 204a1, 204a2, 204a3, 204a4 correspond to the detour wiring solder ball array areas 304b1, 304b2, 304b3, 304b4 in the layer 30b on the back surface side of the relay substrate 30, respectively. It is formed in the same arrangement pattern as the bypass wiring solder balls 35b.

  In FIG. 6, the layer 20a on the surface side of the mother board 20 has a land arrangement area 201a from each land 21a that is less than a predetermined number (less than three in this example) inside the land arrangement area 201a. Wiring patterns 27a extending so as not to interfere with the lands 21a between them are formed to the outside of the area, and further, from the detour wiring lands 25a in the detour wiring land array areas 204a1, 204a2, 204a3, 204a4 to the outside thereof. A detour wiring pattern 29a routed toward is formed.

The wiring patterns 27 a and 29 a are wiring patterns formed to electrically connect components and circuits mounted on the layer 20 a of the motherboard 20 and the semiconductor device 10.

  The semiconductor device 10 having the solder ball arrangement pattern shown in FIG. 3 is applied to the mother board 20 having the land arrangement pattern as shown in FIG. 6 through the land shown in FIGS. 4 and 5 or the relay substrate 30 having the solder ball arrangement pattern. In order to mount and assemble into a package as shown in FIG. 1, first, as shown in FIG. 7, the back surface 10b of the semiconductor device 10 is made to face the layer 30a on the front surface side of the relay substrate 30, and the back surface of the semiconductor device 10 is 10b (see FIG. 3), the solder ball arrangement region 101b, the central solder ball arrangement region 102b, the inner solder ball arrangement regions 103b1, 103b2, 103b3, 103b4, and the layer 30a (see FIG. 4) on the surface side of the relay substrate 30 Land arrangement area 301a, central land arrangement area 302a, inner land arrangement area 303a , While the 303a2,303a3,303a4 is obtained by contact with the solder balls 12b and each land 31a facing performing positioning to face each implementing reflow soldering process.

  In this reflow soldering process (semi-assembled process), each solder ball 12b which is an external connection terminal of the semiconductor device 10 and each land 31a of the layer 30a on the surface side of the relay substrate 30 are in contact with each other. The step of melting the solder balls 12b and the step of cooling and fixing are performed, and each solder ball 12b in the solder ball arrangement region 101b on the back surface 10b of the semiconductor device 10 and the land arrangement region 301a in the layer 30a on the surface side of the relay substrate 30 are performed. A semi-assembled product having a form as shown in FIG. 7 can be manufactured in which each of the lands 31a is soldered (electrically joined).

  In the present invention, each solder ball 32b in the solder ball arrangement region 301b in the layer 30b on the back surface side of the relay substrate 30 and each bypass wiring solder ball 35b outside the solder ball arrangement region 301b are both made of a core material. In the reflow soldering process, the solder balls 32b and the bypass wiring solder balls 35b are solder balls because the solder balls are formed of high melting point solder having a melting point higher than that of the solder balls on the back surface 10b of the semiconductor device 10. No need to crush.

  Next, the layer 20a on the front surface side of the motherboard 20 faces the layer 30b on the back surface side of the relay substrate 30 in this semi-assembled product as shown in FIG. 8, and the layer 20a on the front surface side of the motherboard 20 (see FIG. 6). Land array area 201a, center land array area 202a, inner land array areas 203a1, 203a2, 203a3, 203a4, detour wiring land array areas 204a1, 204a2, 204a3, 204a4, and layer 30b on the back side of relay substrate 30 (FIG. 5) The solder ball arrangement region 301b, the central solder ball arrangement region 302b, the inner solder ball arrangement regions 303b1, 303b2, 303b3, and 303b4, and the detour wiring solder ball arrangement regions 304b1, 304b2, 304b3, and 304b4 face each other. Together And each land 21a and bypass wiring lands 25a opposed performed, being in contact with solder balls 32b and bypass wiring solder balls 35b, performing the soldering process (step assembled Completed in FIG. 8).

  In the soldering process in the finished product assembly process, the solder balls 32b and the bypass wiring solder balls 35b as leads are melted at a temperature higher than that in the reflow soldering process in FIG. 7, and then cooled and fixed.

  Thereby, each land 21a in the land arrangement area 201a in the layer 20a on the surface side of the mother board 20 and each detour wiring land 25a outside the area 201a and the relay board 30 (on the surface side through the reflow soldering step in FIG. 7). The solder balls 32b in the solder ball arrangement region 301b and the bypass wiring solder balls 35b outside the region 301b in the layer 30b on the back surface side of the semiconductor device 10 already bonded to the layer 30a correspond to each other. As a result, a finished product (semiconductor device mounting package: see FIG. 1) of the embodiment shown in FIG. 8 in which the semiconductor device 10 is mounted on the motherboard via the relay substrate 30 is manufactured. can do.

  Prior to the soldering process in the finished product assembly process in FIG. 8, the reflow soldering process as shown in FIG. 7 has already been performed, but each solder ball 32 b in the layer 30 b on the back surface side of the relay substrate 30. Since each detour wiring solder ball 35b is formed of a high melting point solder including a core material, the reflow soldering process does not cause the ball to collapse.

  For this reason, after that, when the solder joint is completed by the soldering process at a higher temperature in the finished product assembly process shown in FIG. 8, the solder ball 32b and the bypass wiring solder ball 35b and the land 21a and the bypass wiring on the motherboard 20 Good solderability between the lands 25a can be maintained.

  Thus, in the present invention, the semiconductor device 10 is mounted on the mother board 20 by inserting the relay substrate 30 between the BGA type semiconductor device 10 and the mother board 20 (see FIG. 1).

  In this case, the relay substrate 30 forms lands 31a in the same arrangement as the solder balls 12b of the semiconductor device 10 on the first surface side layer 30a corresponding to the surface 10b on which the solder balls 12b of the semiconductor device 10 are arranged. (See FIG. 4), and the second surface layer 30b facing the layer 20a on which the lands 21a of the motherboard 20 are arranged has the same arrangement as the lands 21a of the motherboard 20, and the first surface Solder balls 32b that can be electrically connected are formed by the corresponding lands 31a and through-holes 33 of the side layer 30a (see FIG. 5).

  Further, on the layer 30b on the second surface side of the relay substrate 20, detour wiring solder balls 35b are formed outside the solder ball arrangement region 301b, and, for example, three more inside than the outer edge of the solder ball arrangement region 301b. A bypass wiring pattern 39b routed from the inner solder ball 32b, which is a solder ball, to the solder ball arrangement region 301b and the bypass wiring solder ball 35b is formed (see FIG. 5).

  On the other hand, as shown in FIG. 6, the solder ball arrangement region in the layer 30 b on the second surface side of the relay substrate 30 is provided on the layer 20 a facing the layer 30 b on the second surface side of the relay substrate 30 of the motherboard 20. In addition to the lands 21a in the same arrangement as the solder balls 32b in the 301b, the detour wiring lands 25a (the detour wiring formed on the layer 30b on the second surface side of the relay substrate 30) outside the arrangement area 201a of the lands 21a. Corresponding to the solder balls 35b).

  As a result, the semiconductor device 10 faces the layer 30a on the first surface side of the relay substrate 30, and each solder ball 12b in the solder ball arrangement region 101b of the semiconductor device 10 and each of the land arrangement region 301a in the relay substrate 20 are arranged. While soldering the lands 31a to each other, the layer 30b on the second surface side of the relay substrate 30 faces the layer 20a on the surface side where the land array region 201a of the motherboard 20 is formed, and the solder ball array region of the relay substrate 20 Each solder ball 32b in 301b, the bypass wiring solder ball 35b outside the region 301b, each land 21a in the land array region 201a of the motherboard 20, and the bypass wiring land 25a outside the region 201a are mutually connected. In the soldered semiconductor device mounting state (see FIG. 1), the solder bolt of the semiconductor device 10 is used. Each solder ball 12b in the solder array region 101b is connected to each land 31a of the layer 30a on the first surface side of the relay substrate 30 → each through hole 33 → each solder ball 32b of the layer 30b on the second surface side → the motherboard 20 Is electrically connected to the wiring pattern 27a formed on the surface 20a of the mother board 20 through the lands 21a of the surface 20a.

  Further, in this semiconductor mounted state, each of the three solder balls (inner solder balls) 12b inside the solder ball arrangement region 101b of the semiconductor device 10 inside the region outer edge is an essential part of the package in the mounted state shown in FIG. As can be seen from the partial side configuration conceptual diagram, each solder ball (inner solder) of each land 31a corresponding to the layer 30a on the first surface side of the relay substrate 30 → each through hole 33 → the layer 30b on the second surface side. Ball) 32 b → detour wiring pattern 39 b → detour wiring solder ball 35 b → electrically connected to the wiring pattern 29 a formed on the layer 20 a on the surface side of the mother board 20 through each detour wiring land 25 a of the layer 20 a on the surface side of the mother board 20. Connected.

  According to this mounting structure, each solder ball (inner solder ball) 32b of the layer 30b on the second surface side of the relay substrate 30 → the bypass wiring pattern 39b → the bypass wiring solder ball 35b (see FIG. 5 above) → the motherboard 20 The detour wiring route composed of each detour wiring land 25a → wiring pattern 29a (refer to FIG. 6 above) of the surface layer 20a of the front side is the inner land array region 203a1, in the surface layer 20a of the mother board 20 shown in FIG. In place of each inner land in 203a2, 203a3, and 203a4 (each three lands on the inner side of the outer edge of the land array area 201a) from 21a to the outside of the land array area 201a. .

  Therefore, in the configuration of the present invention having the bypass wiring route including the bypass wiring pattern 39b between each inner solder ball 32b and the bypass wiring solder ball 35b in the layer 30b on the second surface side of the relay substrate 30, as shown in FIG. In the layer 20a on the front surface side of the mother board 20, each inner land in the inner land array regions 203a1, 203a2, 203a3, 203a4 (each land on the inner side of the land array region 201a by only three lands) 21a from the land array region 201a It is unnecessary to form a wiring pattern that extends outside the region.

  In this regard, conventionally, as shown in FIG. 11, in the layer on the surface side of the mother board 60, the lands (areas 603a1, 603a2, 603a3, 603a4) 61a inside the land arrangement area are also drawn out of the area. Although the wiring pattern efficiency is inevitably deteriorated due to the necessity of providing the wiring pattern 67a, in the present invention, as shown in FIG. 6, it is 3 from the outer edge of the land array region 201a in the layer 20a on the surface side of the mother board 20. A wiring pattern for routing the inside of the land array area 201a from the inner land (inner land) 21a to the outside of the area is not necessary, and the wiring pattern efficiency in the land array area 201a is improved accordingly. Can do.

  That is, according to the mounting structure of the semiconductor device 10 on the mother board 20 using the relay board 30 according to the present invention, wiring of a pattern that is difficult to wire only on the mother board 20 is routed through the bypass wiring pattern 39b formed on the relay board 30. Can be done.

  Further, according to the mounting structure according to the present invention, a plurality of bypass wiring solder balls 35b are provided outside the solder ball arrangement region 301b in the layer 30b on the second surface side of the relay substrate 30 (in the example of FIG. 3 are provided in the vicinity of each side of the ball array area 301b), and the bypass wiring pattern 39b is provided between each of the bypass wiring solder balls 35b and the different inner solder balls 32b in the solder ball array area 301b. Thus, the respective wiring patterns 29a to which the respective bypass wiring patterns 39b are connected can be dispersed in each direction through the respective bypass wiring lands 25a formed on the mother board 20 corresponding to the respective bypass wiring patterns 39b. .

  In the present invention, the detour wiring route including the detour wiring pattern 39b between each inner solder ball 32b and the detour wiring solder ball 35b in the layer 30b on the second surface side of the relay substrate 30 in the present invention suppresses the wiring length as short as possible. Therefore, the problem of skew between signals in the high-speed transmission path can be minimized.

  Of the lands 21a of the land array area 201a in the layer 20a on the surface side of the mother board 20 shown in FIG. 6, the lands 21a in the center land array area 202a are used as power supply or GND lands. However, according to the structure of the present invention, the detour wiring pattern 39b is formed in the layer 30b on the second surface side of the relay board 30 for each of the central lands 21a to the mother board 20. It may be possible to secure a detour connection route.

  In addition, the present invention is not limited to the embodiment described above and shown in the drawings, and can be implemented by being appropriately modified within a range not changing the gist thereof.

  For example, in the above-described embodiment, an example in which the bypass wiring pattern 39b is formed on the layer 30b on the surface of the relay substrate 30 facing the mother board 20 has been described. For example, as illustrated in FIG. In the surface layer 30a, one or a plurality of detour wiring lands 35a are formed outside the land array region 301a, and an inner land that is a predetermined number (for example, only three) lands inside the region outer edge of the land array region 301a. A detour wiring pattern 39a routed from the land 32a to each detour wiring land 35a outside the land arrangement region 301b is formed, and each detour wiring land 35a is formed on the second surface side through the through hole 350. You may make it the structure electrically connected with the detour wiring land 25a provided in the layer 30b.

  The present invention can be applied to a semiconductor device mounting package in which a BGA type semiconductor device is mounted on a motherboard, and a detour wiring pattern for bypassing a predetermined number of lands on the motherboard from the outer edge of the land arrangement region of the semiconductor device. By mounting a semiconductor device on a mother board via a relay printed wiring board having a wiring pattern for drawing from an inner land, which is a predetermined number of lands inside the outer edge of the land arrangement area on the mother board, to the outside of the land arrangement area The wiring pattern efficiency can be improved by that amount.

The conceptual diagram which shows the side surface cross-section of the semiconductor device mounting package which concerns on this invention. The conceptual diagram which shows the decomposition | disassembly structure of the package in FIG. FIG. 3 is a diagram showing an external configuration of a semiconductor device viewed from the direction of arrow A in FIG. 2. The figure which shows the external appearance structure of the relay board | substrate seen from the arrow B direction in FIG. The figure which shows the external appearance structure of the relay board | substrate seen from the arrow C direction in FIG. The figure which shows the external appearance structure of the motherboard seen from the arrow D direction in FIG. The conceptual diagram which shows the lamination | stacking state in a half assembly process. The conceptual diagram which shows the lamination | stacking state in a finished product assembly process. The principal part side surface conceptual diagram of the semiconductor device mounting package by relay board | substrate insertion. The principal part side surface conceptual diagram of the semiconductor device mounting package by the relay board | substrate insertion of another example. The figure which shows the external appearance structure of the semiconductor device opposing surface in the conventional motherboard.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... BGA type | mold semiconductor device, 10b ... Semiconductor device back surface, 12b ... Solder ball, 101b ... Solder ball arrangement | positioning area | region, 102b ... Center part solder ball arrangement | positioning area | region, 103b1, 103b2, 103b3, 103b4 ... Inner solder ball arrangement | positioning area, 20 ... Printed wiring board (motherboard), 20a ... layer on the front side, 201a ... land arrangement area, 202a ... central land arrangement area, 203a1, 203a2, 203a3, 203a4 ... inner land arrangement area, 204a1, 204a2, 204a3, 204a4 ... detour Land layout area for wiring, 21a ... land, 25a ... land for bypass wiring, 27a ... wiring pattern, 29a ... bypass wiring pattern, 20b ... layer on the back side, 30 ... relay printed wiring board (relay board), 30a ... front side Layer, 301a ... Land arrangement , 302a ... center land arrangement area, 303a1, 303a2, 303a3, 303a4 ... inner land arrangement area, 35a ... detour wiring land, 350 ... through hole, 39a ... detour wiring pattern, 31a ... land, 30b ... on the back side Layer, 301b ... solder ball arrangement area, 302b ... central solder ball arrangement area, 303b1, 303b2, 303b3, 303b4 ... inner solder ball arrangement area, 304b1, 304b2, 304b3, 304b4 ... detour wiring solder ball arrangement area, 32b ... Solder balls, 33 through holes, 35b solder balls for detour wiring, 39b detour wiring patterns

Claims (7)

The semiconductor device is interposed between a ball grid array type semiconductor device in which solder balls are arranged in a grid and a mother substrate in which solder lands are formed in the same arrangement as the solder balls. It is a relay printed wiring board that is mounted on
Forming a land of the same arrangement as the solder balls of the semiconductor device on the first surface facing the solder ball arrangement region of the semiconductor device;
In addition, solder balls having the same arrangement as the lands of the mother board are formed on the second surface facing the land arrangement area of the mother board, and
Each land on the first surface and each solder ball on the second surface corresponding to each land can be electrically connected by a through hole,
Further, a detour formed by extending from an arbitrary land in the land arrangement area on the first surface or an arbitrary solder ball in the solder ball arrangement area on the second surface to the outside of the corresponding land or solder ball arrangement area. A relay printed wiring board having a wiring pattern. Forming a solder ball for bypass wiring outside the solder ball arrangement region on the second surface;
The detour wiring pattern extending from an inner solder ball, which is a solder ball a predetermined number of inner sides than the outer edge of the solder ball arrangement region on the second surface, to the detour wiring solder ball is formed. Relay printed wiring board. Forming a land for detour wiring outside the land arrangement region on the first surface;
And forming the detour wiring pattern extending from the inner land, which is a land a predetermined number of lands inside the outer edge of the land arrangement area on the first surface, to the detour wiring land,
A bypass wiring solder ball connected to the bypass wiring land on the first surface by a through hole electrically connected to the second surface is formed outside the solder ball arrangement region on the second surface. The relay printed wiring board according to claim 1. The solder balls in the solder ball arrangement region on the second surface are formed of a high melting point solder including a core material and having a melting point higher than that of the solder balls of the semiconductor device. The relay printed wiring board according to any one of the above. A ball grid array type semiconductor device in which solder balls are arranged in a grid, and
A mother board in which lands for solder bonding are formed in the same arrangement as the solder balls;
On the first surface facing the solder ball arrangement region of the semiconductor device, lands having the same arrangement as the solder balls of the semiconductor device are formed, and on the second surface facing the land arrangement region of the mother substrate, Forming solder balls which are arranged in the same arrangement as the lands of the mother board and are connected to through-holes which are electrically conductive with the corresponding lands on the first surface; An arbitrary land in the land array region on the first surface or an arbitrary solder ball in the solder ball array region on the second surface is connected to a wiring pattern on the mother board on at least one of the surfaces. A semiconductor device mounting package having a relay printed wiring board formed by forming a bypass wiring pattern for electrical connection,
The solder ball arrangement region of the semiconductor device is made to face the first surface of the relay printed wiring board, and each solder ball in the solder ball arrangement region and each land in the land arrangement region on the first surface are connected to each other. Solder joining and making the second surface of the relay printed wiring board face the land array region of the mother board, each solder ball in the solder ball array region on the second surface and the land array of the mother board A package for mounting a semiconductor device, characterized by soldering each land in the area. On the mother board, a land for bypass wiring is formed outside the land arrangement area, and
In the relay printed wiring board, a solder ball for bypass wiring is formed outside the solder ball arrangement area on the second surface, and the inside is a predetermined number of solder balls inside the outer edge of the solder ball arrangement area Forming the detour wiring pattern extending from the solder ball to the detour wiring solder ball;
The solder ball for the bypass wiring on the second surface of the relay printed wiring board and the bypass wiring land of the mother board are solder-bonded when the semiconductor device is mounted. Semiconductor device mounting package. On the mother board, a land for bypass wiring is formed outside the land arrangement area, and
In the relay printed wiring board, lands for detour wiring are formed outside the land array area on the first surface, and the detour is made from an inner land that is a land that is a predetermined number inside the outer edge of the land array area. While forming the detour wiring pattern extending to the wiring land,
Forming a solder ball for bypass wiring connected by a through hole electrically conductive with the land for bypass wiring on the first surface outside the solder ball arrangement region on the second surface;
The solder ball for the bypass wiring on the second surface of the relay printed wiring board and the bypass wiring land of the mother board are solder-bonded when the semiconductor device is mounted. Semiconductor device mounting package.

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