JP2006260766A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable realizing high speed operation and low power consumption, and also to realize an effective test for evaluating reliability. <P>SOLUTION: In a normal mode, a voltage drop circuit 43 gives large internal power source voltage intVccp to peripheral circuits, a voltage drop circuit 45 gives small internal power source voltage intVcca to a memory cell array. thereby, high speed operation and low power consumption can be realized. At the time of burn-in test, an external power source voltage supply line 51 and internal power source voltage supply lines 53, 55 are connected. Thereby, external power source voltage extVcc is given directly to the internal power source voltage supply lines 53, 55. Thereby, the effective burn-in test can be performed. Further, at the time of the burn-in test, the voltage drop circuits 43, 45 are made non-activation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a circuit related to a test for reliability evaluation.

  In recent years, the power supply voltage of the system itself including the memory is generally higher than the voltage necessary for the operation of the memory. In order to supply the memory power supply voltage from the power supply voltage of the system itself, the voltage is dropped inside the memory chip. The internal power supply voltage necessary for memory operation is often generated. A circuit that generates the internal power supply voltage in this way is called a voltage drop circuit. By using such a voltage drop circuit, the power consumption of the memory chip is greatly reduced, and a stable voltage can be supplied into the memory chip.

  FIG. 16 is a schematic diagram showing a part of a semiconductor memory device as a conventional semiconductor integrated circuit device.

  Referring to FIG. 16, the conventional semiconductor integrated circuit device includes a power supply pad 41, a voltage drop circuit (VDC) 245 and a PMOS transistor 47. Voltage drop circuit 245 is provided between external power supply voltage supply line 51 and internal power supply voltage supply line 247. The PMOS transistor 47 is provided between the external power supply voltage supply line 51 and the internal power supply voltage supply line 247. A signal / STR is applied to the gate of the PMOS transistor 47. External power supply voltage extVcc is applied to external power supply voltage supply line 51 through power supply pad 41. Voltage drop circuit 245 steps down external power supply voltage extVcc to generate internal power supply voltage intVcc, and provides this internal power supply voltage intVcc to internal power supply voltage supply line 247. The voltage drop circuit 245 performs such operation in a normal mode other than the test mode for reliability evaluation, and stops its operation in the test mode for reliability evaluation. The test for reliability evaluation will be described in detail later. The PMOS transistor 47 is off in the normal mode, and the external power supply voltage supply line 51 and the internal power supply voltage supply line 247 are disconnected. That is, in the normal mode, signal / STR is at “H” level. The PMOS transistor 47 connects the external power supply voltage supply line 51 and the internal power supply voltage supply line 247 in the test mode for reliability evaluation. That is, in the test mode for reliability evaluation, the signal / STR is at the “L” level.

  FIG. 17 is a circuit diagram showing details of the differential amplifier section of the voltage drop circuit (VDC) 245 of FIG. Referring to FIG. 17, the differential amplifier portion of the conventional semiconductor memory device includes a standby circuit and an active circuit. The standby circuit of the differential amplifier section includes a differential amplifier 93, an NMOS transistor 97, and a PMOS transistor 105. A reference voltage Vref is applied to one input node of the differential amplifier 93. The other input node of differential amplifier 93 is connected to internal power supply voltage supply line 247. The drain of the NMOS transistor 97 is connected to the differential amplifier 93, the source is connected to a node having a ground voltage, and a constant intermediate voltage BiasL is applied to the gate. PMOS transistor 105 is provided between a node having external power supply voltage extVcc and internal power supply voltage supply line 247. The gate of the PMOS transistor 105 is connected to the output node of the differential amplifier 93. The active circuit of the differential amplifier section includes a differential amplifier 95, an NMOS transistor 101, and PMOS transistors 107 and 109. A reference voltage Vref is applied to one input node of the differential amplifier 95. The other input node of differential amplifier 95 is connected to internal power supply voltage supply line 247. The drain of the NMOS transistor 101 is connected to the differential amplifier 95, the source is connected to a node having the ground voltage, and the signal ACT is given to the gate. PMOS transistor 109 is connected between a node having external power supply voltage extVcc and internal power supply voltage supply line 247. The gate of the PMOS transistor 109 is connected to the output node N 1 of the differential amplifier 95. PMOS transistor 107 is provided between a node having external power supply voltage extVcc and output node N 1 of differential amplifier 95. A signal ACT is supplied to the gate of the PMOS transistor 107.

  The standby circuit of the differential amplifier section compares the reference voltage Vref and the internal power supply voltage intVcc with the differential amplifier 93, and controls the PMOS transistor 105 that receives the output of the differential amplifier 93, whereby the internal power supply voltage intVcc. It is a feedback type circuit that adjusts the level of. Similarly to the standby circuit, the active circuit of the differential amplifier unit compares the reference voltage Vref and the internal power supply voltage intVcc with the differential amplifier 95, and controls the PMOS transistor 109 that receives the output of the differential amplifier 95. Thus, the feedback type circuit adjusts the level of the internal power supply voltage intVcc. The standby circuit of the differential amplifier section must always operate, but the current of the differential amplifier 93 is limited by a certain intermediate voltage BiasL in order to reduce current consumption. The active circuit of the differential amplifier unit is activated only during a period in which the chip consumes a large current. That is, the signal ACT is at the CMOS level (“H” level) during a period in which the chip consumes a large current, and is at the “L” level during other periods. Here, in a period in which the chip does not consume a large current, that is, in a period in which the signal ACT is at the “L” level, the PMOS transistor 107 is on, and the node N1 is at the “H” level. Therefore, when the signal ACT is at “L” level, the PMOS transistor 109 is turned off and the active circuit is inactivated.

  Next, a test for reliability evaluation will be described. In general, a device failure is roughly divided into three periods. That is, as time passes, there are an initial failure period, an accidental failure period, and a wear failure period. An initial failure is a failure that occurs immediately after use, and a defect appears when a device is created. This failure rate decreases rapidly with time. After that, a low failure rate continues for a certain period of time (an accidental failure period). Eventually, the device approaches the useful life and the failure rate increases rapidly (wear failure period). The device is preferably used within a random failure period, and this area is the useful life. Therefore, in order to improve the reliability of the device, it is required that the accidental failure is low and constant and the accidental failure period lasts long. On the other hand, in order to remove the initial failure in advance, it is necessary to perform accelerated operation aging for a certain period of time on the device to perform screening for removing defective products. In order to perform this effectively in a short period, it is desirable that the initial failure rate decreases rapidly with respect to time and enters the accidental failure period early. Currently, a burn-in test (high temperature operation test) is generally performed as one of the screening methods. The burn-in test is a method that allows direct evaluation of dielectric films using actual devices, and is a test that reveals all defective factors by applying high-temperature and high-field stresses, including migration of aluminum wiring. . In particular, it is effective to increase the acceleration by operating the device during temperature acceleration.

  In the semiconductor memory device as the conventional semiconductor integrated circuit device as shown in FIG. 16, one type of voltage drop circuit 245 is used and one type of internal power supply voltage intVcc is used. In this case, the following problem occurs.

  In general, a memory cell array is a large power consumption source compared to peripheral circuits. Therefore, the internal power supply voltage intVcc applied to the memory cell array is reduced to reduce power consumption. However, since the conventional semiconductor memory device is provided with only one type of voltage drop circuit 245, high speed operation cannot be achieved by applying such a small internal power supply voltage intVcc to the peripheral circuit.

  On the other hand, in order to achieve high-speed operation, the internal power supply voltage intVcc may be increased and applied to the peripheral circuit. However, in the conventional semiconductor memory device, only one type of voltage drop circuit 245 is provided, and power consumption cannot be reduced if such a large internal power supply voltage intVcc is also applied to the memory cell array.

  The present invention has been made to solve the above-described problems. A semiconductor integrated circuit device capable of realizing high-speed operation and low power consumption and capable of performing a test for effective reliability evaluation is provided. The purpose is to provide.

  A semiconductor integrated circuit device according to a first aspect of the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of driver means, a boosted voltage generating means, and a test voltage supply means. The plurality of memory cells are arranged in a matrix of rows and columns. A word line is arranged corresponding to each row. A corresponding memory cell is connected to each word line. Driver means is provided corresponding to the word line. The boosted voltage generating means generates a boosted voltage in the normal mode and supplies the boosted voltage to the driver means. The test voltage supply means supplies the first test voltage to each driver means via the voltage supply line based on the external power supply voltage in the test mode for reliability evaluation. In the normal mode, the driver means corresponding to the selected word line supplies a voltage to the corresponding word line based on the boosted voltage. In the test mode, each driver means supplies a voltage to the corresponding word line based on the first test voltage. The test voltage supply means includes current limiting means for limiting the current flowing into the voltage supply line.

  A semiconductor integrated circuit device according to a second aspect of the present invention is the semiconductor integrated circuit device according to the first aspect, wherein the current limiting means includes a constant current source for generating a constant current and a current mirror means.

  According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device according to the first aspect, further comprising a plurality of bit line pairs. Bit line pairs are arranged corresponding to the respective columns. Each bit line pair is connected to a memory cell in a corresponding column. The memory cell includes a memory cell transistor and a memory cell capacitor. The control electrode of the memory cell transistor is connected to the corresponding word line, the first electrode of the memory cell transistor is connected to the corresponding bit line of the corresponding bit line pair, and the second electrode of the memory cell transistor is connected to the memory Connected to one end of the cell capacitor. In the test mode, a second test voltage is applied to the other end of each memory cell capacitor, and a ground voltage is applied to each bit line pair.

  According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device according to the third aspect, further comprising a plurality of sense amplifiers, equalizing / precharging means, and sense amplifier control means. A sense amplifier is provided corresponding to each bit line pair. Each sense amplifier amplifies the potential difference between the bit lines of the corresponding bit line pair. The equalize / precharge means sets a plurality of bit line pairs to a predetermined potential. The sense amplifier control means stops the operation of each sense amplifier in the test mode. The equalize / precharge means sets each bit line pair to the ground potential in the test mode.

  In the semiconductor integrated circuit device according to the present invention, when the first test voltage is applied to the driver means via the voltage supply line in the test mode for reliability evaluation, the current flowing into the voltage supply line is limited. Therefore, in the semiconductor integrated circuit device according to the present invention, excessive current can be prevented from flowing into the voltage supply line, and chip defects can be avoided.

  Preferably, in the test mode for reliability evaluation, when a voltage is applied to the word line based on the boosted voltage, a second test voltage is applied to the other end of the memory cell capacitor, and a bit line pair is applied to the word line. Apply ground voltage. Therefore, the reliability test of the gate oxide film of the memory cell transistor connected to the word line and the reliability test of the memory cell capacitor can be performed simultaneously.

A semiconductor integrated circuit device according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a schematic block diagram showing an overall configuration of a dynamic random access memory (hereinafter referred to as “DRAM”) as a semiconductor integrated circuit device according to a first embodiment of the present invention. Referring to FIG. 1, the DRAM according to the first embodiment includes a clock generation circuit 17, a logic gate 21, a row and column address buffer 23, a row decoder 25, a column decoder 27, an input / output circuit 29, a sense amplifier column 31, a memory. Cell array 33, input buffer 35, output buffer 37, intVcc generation unit 19, / CAS input pad 1, / RAS input pad 3, / W input pad 5, address signal input pad group 7, external power supply voltage input pad group 9, ground A voltage input pad group 11, a data input / output pad group 13, and an / OE input pad 15 are provided. A column address strobe signal / CAS is applied to / CAS input pad 1. A row address strobe signal / RAS is applied to / RAS input pad 3. A write control signal / W is applied to / W input pad 5. Address signal input pads 7 are supplied with address signals A1 to An. External power supply voltage input pad group 9 is supplied with external power supply voltage extVcc. A ground voltage Vss is applied to the ground voltage input pad group 11. Data input / output pad group 13 is supplied with input data DQ1-DQ4 or output data DQ1-DQ4. An output enable signal / OE is applied to / OE input pad 15.

  In the memory cell array 33, a plurality of word lines (not shown) are arranged along the row direction, and a plurality of bit line pairs (not shown) are arranged along the column direction. A plurality of memory cells (not shown) are arranged at intersections of the plurality of word lines and the plurality of bit line pairs. Hereinafter, the operation of the DRAM in the normal mode, which is a mode other than the test mode for reliability evaluation, will be described. The row decoder 25 selects and drives one of the plurality of word lines in response to a row address signal supplied from the row and column address buffer 23. Column decoder 27 selects one of a plurality of bit line pairs in response to a column address signal supplied from row and column address buffer 23. The sense amplifier row 31 includes a plurality of sense amplifiers (not shown). The plurality of sense amplifiers are provided corresponding to the plurality of bit line pairs. Each sense amplifier amplifies the potential difference between the bit lines of the corresponding bit line pair. The input / output circuit 29 supplies the voltage of the bit line pair selected by the column decoder 27 to the output buffer 37. The output buffer 37 amplifies the supplied voltage and outputs it as output data DQ1 to DQ4. The input buffer 35 amplifies input data DQ1 to DQ4 supplied from the outside. The input / output circuit 29 supplies the input data amplified in the input buffer 35 to the bit line pair selected by the column decoder 27. The row and column address buffer 23 selectively supplies externally supplied address signals A1 to An to the row decoder 25 and the column decoder 27. Clock generation circuit 17 generates various internal control signals in response to row address strobe signal / RAS and column address strobe signal / CAS. The intVcc generation unit 19 generates internal power supply voltages intVccp and intVcca. Internal power supply voltage intVcca smaller than internal power supply voltage intVccp is supplied to input / output circuit 29, sense amplifier array 31 and memory cell array 33 in order to reduce current consumption. Internal power supply voltage intVccp larger than internal power supply voltage intVcca is supplied to clock generation circuit 17, row and column address buffer 23, row decoder 25, column decoder 27, input buffer 35 and output buffer 37 to achieve high-speed operation. Is done.

  FIG. 2 is a schematic diagram showing a part of the DRAM of FIG. Referring to FIG. 2, the DRAM of FIG. 1 includes capacitors 32, 34, 36, and 38, voltage drop circuits (VDC) 43 and 45, a power supply pad 41, and PMOS transistors 47 and 49. Here, voltage drop circuits 43 and 45 constitute intVcc generation unit 19 of FIG. The PMOS transistor 47 is provided between the external power supply voltage supply line 51 and the internal power supply voltage supply line 53. Burn-in mode detection signal / STR is applied to the gate of PMOS transistor 47. The voltage drop circuit 43 is provided between the external power supply voltage supply line 51 and the internal power supply voltage supply line 53. The PMOS transistor 49 is provided between the external power supply voltage supply line 51 and the internal power supply voltage supply line 55. Burn-in mode detection signal / STR is applied to the gate of PMOS transistor 49. The voltage drop circuit 45 is provided between the external power supply voltage supply line 51 and the internal power supply voltage supply line 55. Capacitors 32 and 36 are provided between external power supply voltage supply line 51 and a node having a ground voltage. Capacitor 38 is provided between internal power supply voltage supply line 55 and a node having a ground voltage. Capacitor 34 is provided between internal power supply voltage supply line 53 and a node having a ground voltage.

  External power supply voltage extVcc is applied to external power supply voltage supply line 51 through power supply pad 41. In a normal mode (read operation, write operation, etc.) that is a mode other than a test mode for reliability evaluation (for example, burn-in test mode), burn-in mode detection signal / STR is at “H” level, The PMOS transistors 47 and 49 are off. For this reason, the external power supply voltage supply line 51 and the internal power supply voltage supply lines 53 and 55 are disconnected. Next, the operation of the voltage drop circuits 43 and 45 in the normal mode will be described. Voltage drop circuit 43 steps down external power supply voltage extVcc to generate internal power supply voltage intVccp, and provides internal power supply voltage intVccp to internal power supply voltage supply line 53. Voltage drop circuit 45 steps down external power supply voltage extVcc, generates internal power supply voltage intVcca, and provides internal power supply voltage intVcca to internal power supply voltage supply line 55. A large internal power supply voltage intVccp is applied from the internal power supply voltage supply line 53 to the clock generation circuit 17, the row and column address buffer 23, the column decoder 27, the row decoder 25, the input buffer 35 and the output buffer 37. A small internal power supply voltage intVcca is applied from the internal power supply voltage supply line 55 to the input / output circuit 29, the sense amplifier row 31 and the memory cell array 33. Thus, different internal power supply voltages intVccp and intVcca are applied to corresponding internal circuits by different voltage drop circuits 43 and 45 based on the same external power supply voltage extVcc. For this reason, the internal power supply voltage supply line 53 and the internal power supply voltage supply line 55 are disconnected.

  During the burn-in test (during a test for reliability evaluation), the voltage drop circuits 43 and 45 are deactivated. In the burn-in test, since the burn-in mode detection signal / STR is at the “L” level, the PMOS transistors 47 and 49 are turned on. Therefore, during the burn-in test, external power supply voltage supply line 51 and internal power supply voltage supply lines 53 and 55 are connected, and external power supply voltage extVcc is directly applied to internal power supply voltage supply lines 53 and 55. Thus, the external power supply voltage extVcc is directly applied to the internal power supply voltage supply lines 53 and 55 during the burn-in test for the following reason. That is, the voltage drop circuits 43 and 45 step down the external power supply voltage extVcc to transmit the constant internal power supply voltages intVccp and intVcca to the corresponding internal circuits. This is because a sufficiently high voltage cannot be applied to the internal circuit.

  Here, the power supply pad 41 is included in the external power supply voltage input pad group 9 of FIG. The capacitors 32, 34, 36, and 38 are provided for relaxing the electric field when a surge such as static electricity enters the power supply pad 41. That is, the capacitors 32, 34, 36, and 38 are capacitors for preventing coupling that are intentionally inserted for noise countermeasures. Capacitors 32 and 36 have a capacitance of about several hundred pF, and capacitors 34 and 38 have a capacitance of about several thousand pF. The capacitors 32, 34, 36, and 38 are MOS capacitors.

  FIG. 3 is a circuit diagram showing details of voltage drop circuit 3 and voltage drop circuit 5 (intVcc generating unit 19 in FIG. 1). The same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Referring to FIGS. 2 and 3, voltage drop circuit 43 includes a constant current source 57, a Vrefp generation circuit 61, and a differential amplifier unit 65. Voltage drop circuit 45 includes a constant current source 57, a Vrefa generation circuit 59 and a differential amplifier unit 63. Here, the constant current source 57 is a common part of the voltage drop circuit 43 and the voltage drop circuit 45. The constant current source 57 includes PMOS transistors 67 and 69, NMOS transistors 87 and 89, and a resistance element 91. PMOS transistor 67 and NMOS transistor 87 are connected in series between a node having external power supply voltage extVcc and a node having a ground voltage. Resistance element 91, PMOS transistor 69 and NMOS transistor 89 are connected in series between a node having external power supply voltage extVcc and a node having a ground voltage. The gate and drain of PMOS transistor 67 and the gate of PMOS transistor 69 are connected to the gates of PMOS transistors 71 and 79. The gates of the NMOS transistors 87 and 89 are connected to the drain (node N2) of the NMOS transistor 89.

  Vrefa generation circuit 59 includes PMOS transistors 71, 73, 75, 77. PMOS transistors 71, 73, 75 and 77 are connected in series between a node having external power supply voltage extVcc and a node having a ground voltage. The gates of PMOS transistors 73-77 are connected to a node having a ground voltage. The node N3 is connected to the differential amplifier unit 63. The potential of the node N3 becomes the reference voltage Vrefa. Vrefp generation circuit 61 includes PMOS transistors 79, 81, 83 and 85. PMOS transistors 79 to 85 are connected in series between a node having external power supply voltage extVcc and a node having a ground voltage. The gates of PMOS transistors 81-85 are connected to a node having a ground voltage. The node N4 is connected to the differential amplifier unit 65. The potential of the node N4 is the reference voltage Vrefp.

  A constant current source 57 generates a constant current i that is less dependent on the external power supply voltage extVcc, and inputs it to a Vrefa generation circuit 59 and a Vrefp generation circuit 61. Then, in the Vrefa generation circuit 59, the input constant current i is converted into a voltage by the channel resistance of the PMOS transistors 71 to 77. On the other hand, in the Vrefp generation circuit 61, the input constant current i is converted into a voltage by the channel resistance of the PMOS transistors 79 to 85. Here, the sum of the channel resistances of the three PMOS transistors 73 to 77 is a channel resistance ra, and the sum of the channel resistances of the three PMOS transistors 81 to 85 is a channel resistance rp. In this case, the channel resistance ra is set to a value different from the channel resistance rp. Thus, the reference voltage (potential of the node N3) Vrefa generated by the Vrefa generation circuit 59 becomes i × ra, and the reference voltage (potential of the node N4) Vrefp generated by the Vrefp generation circuit 61 becomes i × rp. The reference voltage Vrefa and the reference voltage Vrefp can be set to different values. The reference voltage Vrefa generated from the Vrefa generation circuit 59 is input to the differential amplifier unit 63. The reference voltage Vrefp generated from the Vrefp generation circuit 61 is input to the differential amplifier unit 65.

  FIG. 4 is a circuit diagram showing details of the differential amplifier section 63 of FIG. The same parts as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  Referring to FIG. 4, the differential amplifier section that generates internal power supply voltage intVcca to be supplied to memory cell array 33 (FIG. 1) and the like includes a standby circuit and an active circuit. The standby circuit includes a differential amplifier 93, PMOS transistors 103 and 105, and NMOS transistors 97 and 99. Differential amplifier 93 is provided between a node having external power supply voltage Vcc and node N5. A reference voltage Vrefa is applied to one input node of the differential amplifier 93. The other input node of differential amplifier 93 is connected to internal power supply voltage supply line 55. The output node of the differential amplifier 93 is connected to the gate of the PMOS transistor 105. NMOS transistors 97 and 99 are connected in series between node N5 and a node having a ground voltage. The gate of the NMOS transistor 97 is connected to the node N2 of the constant current source 57 in FIG. Here, the size of the NMOS transistor 97 is the same as the size of the NMOS transistors 87 and 89 of FIG. Burn-in mode detection signal / STR is applied to the gate of NMOS transistor 99. PMOS transistor 103 is provided between a node having external power supply voltage extVcc and the output node of differential amplifier 93. Burn-in mode detection signal / STR is applied to the gate of PMOS transistor 103. PMOS transistor 105 is provided between a node having external power supply voltage extVcc and internal power supply voltage supply line 55.

  The active circuit includes an AND circuit 111, a differential amplifier 95, an NMOS transistor 101, and PMOS transistors 107 and 109. A signal ACT is applied to one input node of the AND circuit 111. A standby mode detection signal / STR is applied to the other input node of AND circuit 111. The output node of AND circuit 111 is connected to the gates of NMOS transistor 101 and PMOS transistor 107. The NMOS transistor 101 is provided between the node N6 and a node having a ground voltage. Differential amplifier 95 is provided between a node having external power supply voltage extVcc and node N6. A reference voltage Vrefa is applied to one input node of the differential amplifier 95. The other input node of differential amplifier 95 is connected to internal power supply voltage supply line 55. Output node N 7 of differential amplifier 95 is connected to the gate of PMOS transistor 109. PMOS transistor 107 is provided between a node having external power supply voltage extVcc and node N7. PMOS transistor 109 is provided between a node having external power supply voltage extVcc and internal power supply voltage supply line 55.

  The standby circuit and the active circuit compare the reference voltage Vrefa and the internal power supply voltage intVcca with the differential amplifiers 93 and 95, and control the PMOS transistors 105 and 109 that receive the outputs of the differential amplifiers 93 and 95. Thus, the feedback type circuit adjusts the level of the internal power supply voltage intVcca. During the burn-in test, the burn-in mode detection signal / STR is at the “L” level, so that the NMOS transistors 99 and 101 are turned off. Further, since the PMOS transistors 103 and 107 are turned on, the PMOS transistors 105 and 109 are turned off. In this way, during the burn-in test, the standby circuit and the active circuit are deactivated. The PMOS transistor 107 is provided for the following reason. That is, when the burn-in mode detection signal / STR is at "L" level or the signal ACT is at "L" level, the potential of the node N7 is not uniquely determined. Therefore, the PMOS transistor 109 is forcibly turned off to activate the active circuit. This is to inactivate. The reason for providing the PMOS transistor 103 is also the same.

  The operation of the standby circuit and the active circuit in the normal mode will be described. In the normal mode, burn-in mode detection signal / STR is at “H” level (CMOS level). For this reason, the NMOS transistor 99 is turned on and the PMOS transistor 103 is turned off. In the normal mode, the standby circuit must always operate. However, to reduce current consumption, the differential amplifier 93 is limited in current by a constant intermediate voltage BiasL. On the other hand, the active circuit is activated only in a period in which the chip consumes a large current in the normal mode. In the normal mode, since the burn-in mode detection signal / STR is at the “H” level and the signal ACT is at the “H” level (CMOS level) during the period in which the chip consumes a large current, the NMOS transistor 101 is turned on, and the PMOS The transistor 107 is turned off. The period during which the chip consumes a large current is, for example, during sensing. The active circuit consumes a larger amount of current than the standby circuit, but is designed to operate at high speed with high driving capability. Even in the normal mode, the signal ACT is at the “L” level during the period when the chip does not consume a large current, the NMOS transistor 101 is turned off, and the PMOS transistor 107 is turned on. For this reason, the active circuit is inactivated.

  The activation / inactivation of the active circuit is controlled by the AND signal of the signal ACT and the burn-in mode detection signal / STR, whereas the standby circuit controls the activation / inactivation of the circuit. The reason why the AND circuit is not used is that the NMOS transistor 97 is controlled by the intermediate voltage BiasL. Here, the configuration and operation of the differential amplifier unit 65 in FIG. 3 are the same as the configuration and operation of the differential amplifier unit in FIG. 4 (differential amplifier unit 63 in FIG. 3). 3 is activated only during a period in which the chip consumes a large current in the normal mode, similarly to the active circuit of the differential amplifier unit 63. The period during which the chip consumes a large current is, for example, a period in which the row address strobe signal / RAS is activated.

  FIG. 5 is a circuit diagram showing details of a burn-in mode detection signal generating circuit for generating burn-in mode detection signal / STR. Referring to FIG. 5, the burn-in mode detection signal generation circuit includes a super VIH detection circuit 115, NAND circuits 117, 119, 121 and inverters 123, 125, 127. Super VIH detection circuit 115 is connected to address signal input pad 113. This address signal input pad 113 is included in the address signal input pad group 7 of FIG. For example, address signal input pad 113 is an address signal input pad to which address signal A1 is input in the normal mode. One input node of NAND circuit 117 is supplied with test mode entry signal TENT, and the other input node is supplied with signal SVIH from super VIH detection circuit 115. One input node of the NAND circuit 119 is connected to the output node of the NAND circuit 117. An output node of NAND circuit 119 is connected to an input node of inverter 125. Burn-in mode detection signal / STR is output from the output node of inverter 125. A test mode end signal TEXT is supplied to the input node of the inverter 123. One input node of NAND circuit 121 is connected to the output node of inverter 123. The output node of NAND circuit 121 is connected to the input node of inverter 127. A signal STR having a level opposite to that of burn-in mode detection signal / STR is output from the output node of inverter 127. The NAND circuit 119 and the NAND circuit 121 constitute a set / reset flip-flop circuit.

  FIG. 6 is a circuit diagram showing details of the super VIH detection circuit 115 of FIG. The same parts as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. 6, the super VIH detection circuit includes an input protection circuit 129, NMOS transistors 131, 133, Tr1,..., Trn, a PMOS transistor 139, inverters 141, 143, and a reset circuit 145. The input protection circuit 129 is connected to the address signal input pad 113. NMOS transistors 131 and 133 and PMOS transistor 139 are connected in series between node N8 and input protection circuit 129. The NMOS transistors 131 and 133 are diode-connected. Internal power supply voltage intVccp is applied to the gate of PMOS transistor 139. Node N8 and the input node of inverter 141 are connected. The output node of inverter 141 is connected to the input node of inverter 143. Signal SVIH is output from the output node of inverter 143. This signal SVIH is applied to NAND circuit 117 in FIG. NMOS transistors Tr1,..., Trn are connected in series between node N8 and a node having a ground voltage. The internal power supply voltage intVccp is applied to the gates of the NMOS transistors Tr1,. Reset circuit 145 includes a delay circuit 147, a logic gate 149, an inverter 151, and an NMOS transistor 153. Row address strobe signal / RAS is applied to the input node of delay circuit 147. Row address strobe signal / RAS is applied to one input node of logic gate 149, and a signal obtained by delaying row address strobe signal / RAS is applied to the other input node. The output node of logic gate 129 is connected to the input node of inverter 151. The output node of the inverter 151 is connected to the gate of the NMOS transistor 153. NMOS transistor 153 is provided between node N8 and a node having the ground voltage.

  In order to detect that the burn-in mode is entered in the chip after molding, a technique called super VIH detection is used. For example, the DRAM according to the first embodiment employs a configuration in which the burn-in mode is entered when an excessive voltage equal to or higher than the “H” level of the normal external power supply voltage extVcc is input to a specific address signal input pad. . With reference to FIG. 6, the operation of the super VIH detection circuit including detection of the burn-in mode will be described. In the normal mode, the node N8 is maintained at the “L” level via the NMOS transistors Tr1,..., Trn provided as resistors. Therefore, signal SVIH is also maintained at the “L” level in the normal mode. Here, the resistance values of the NMOS transistors Tr1,..., Trn are increased in order to reduce power consumption. When an excessive voltage is input to the address signal input pad 113, if the voltage stepped down by the two NMOS transistors 131 and 133 is sufficiently larger than the internal power supply voltage intVccp, the PMOS transistor 139 is turned on, and the node N8 is turned on. A sufficient voltage is supplied as the “H” level. Therefore, signal SVIH is also at the “H” level. In this way, the burn-in mode can be detected without adding a dedicated pad. However, since the circuit can be reset only by a minute current flowing through the NMOS transistors Tr1,..., Trn as it is, the super VIH detection circuit has a reset circuit 145. At the end of the active cycle, a pulse is generated at the node N9 at the rise timing of the row address strobe signal / RAS, and a larger driving force than that of the PMOS transistor 139 is applied to lower the potential of the node N8 to the “L” level. The NMOS transistor 153 is turned on. As a result, the super VIH detection circuit can be reset at high speed.

  The operation of the burn-in mode detection signal generation circuit will be described with reference to FIG. In addition to the burn-in test, there are cases where it is desired to perform other tests on the chip after molding. A mode for performing a series of tests is generally called a test mode. When test mode entry signal TENT is at “H” level and signal SVIH from super VIH detection circuit 115 is at “H” level, the set / reset flip-flop circuit configured by NAND circuits 119 and 121 is set. . As a result, burn-in mode detection signal / STR goes to "L" level and signal STR goes to "H" level. On the other hand, the set / reset flip-flop circuit composed of NAND circuits 119 and 121 is reset by a test mode end signal TEXT of “H” level. As a result, burn-in mode detection signal / STR goes to "H" level and signal STR goes to "L" level. Various generation methods are conceivable for the test mode entry signal TENT and the test mode end signal TEXT. For example, the test mode entry signal TENT is set to “H” level at the timing of WCBR (/ W, / CAS before / RAS), the test mode is entered, and the test mode ends at the timing of CBR (/ CAS before / RAS). The signal TEXT is set to “H” level, and the test mode is exited.

  As described above, in the DRAM according to the first embodiment, internal power supply voltage intVccp is applied to peripheral circuits (clock generation circuit 17, row and column address buffer 23, row decoder 25, column decoder 27, input buffer 35 and output buffer 37). A voltage drop circuit 43 to be supplied, and a voltage drop circuit 45 to supply the internal power supply voltage intVcca to the input / output circuit 29, the sense amplifier row 31, and the memory cell array 33 are provided. Further, NMOS transistors 47 and 49 are provided corresponding to the respective voltage drop circuits 43 and 45. During the burn-in test, the external power supply voltage extVcc is directly applied to the internal power supply voltage supply line 53, by the NMOS transistors 47 and 49. 55. Therefore, the DRAM according to the first embodiment can realize high-speed operation and low power consumption, and can execute an effective burn-in test.

(Embodiment 2)
Referring to FIG. 2, internal power supply voltage intVccp is larger than internal power supply voltage intVcca. Therefore, when the same external power supply voltage extVcc is supplied to the internal power supply voltage supply lines 53 and 55 during the burn-in test, the stress condition for the internal circuit to which the voltage is applied from the internal power supply voltage supply line 53, and the internal power supply voltage supply line The stress conditions for the internal circuit to which voltage is applied from 55 are different. In the DRAM as the semiconductor integrated circuit device according to the second embodiment of the present invention, the stress condition for the internal circuit to which the voltage is applied from the internal power supply voltage supply line 53 and the stress to the internal circuit to which the voltage is applied from the internal power supply voltage supply line 55. The task is to match the conditions.

  The overall configuration of the DRAM according to the second embodiment is the same as that of the DRAM according to the first embodiment (FIG. 1). FIG. 7 is a schematic diagram showing a part of the DRAM according to the second embodiment. The same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. Referring to FIG. 7, the DRAM according to the second embodiment includes power supply pads 155 and 157, capacitors 32, 34, 36 and 38, voltage drop circuits 43 and 45, and PMOS transistors 47 and 49. The voltage drop circuit 43 is provided between the external power supply voltage supply line 159 and the internal power supply voltage supply line 53. The PMOS transistor 47 is provided between the external power supply voltage supply line 159 and the internal power supply voltage supply line 53. Burn-in mode detection signal / STR is applied to the gate of PMOS transistor 47. An external power supply voltage is applied to the external power supply voltage supply line 159 via the power supply pad 155. The voltage drop circuit 45 is provided between the external power supply voltage supply line 161 and the internal power supply voltage supply line 55. The PMOS transistor 49 is provided between the external power supply voltage supply line 161 and the internal power supply voltage supply line 55. Burn-in mode detection signal / STR is applied to the gate of PMOS transistor 49. Capacitor 32 is provided between external power supply voltage supply line 159 and a node having a ground voltage. Capacitor 36 is provided between external power supply voltage supply line 161 and a node having a ground voltage. An external power supply voltage is applied to external power supply voltage supply line 161 via pad 157. Here, the burn-in mode detection signal generating circuit for generating burn-in mode detection signal / STR is the same as the burn-in mode detection signal generating circuit shown in FIGS.

  The operation in the normal mode will be described. The same external power supply voltage extVcc1 is applied to external power supply voltage supply lines 159 and 161 from pads 155 and 157. Since burn-in mode detection signal / STR is at "H" level, PMOS transistors 47 and 49 are off. Therefore, voltage drop circuit 43 steps down external power supply voltage extVcc1 and provides internal power supply voltage intVccp to internal power supply voltage supply line 53. On the other hand, voltage drop circuit 45 steps down external power supply voltage extVcc1, generates internal power supply voltage intVcca, and supplies it to internal power supply voltage supply line 55. Note that intVccp> intVcca. Other operations in the normal mode and the method of applying external power supply voltage extVcc1 from pads 155 and 157 are the same as those of the DRAM according to the second embodiment.

  The operation during the burn-in test will be described. The voltage drop circuits 43 and 45 are deactivated. Since burn-in mode detection signal / STR is at "L" level, PMOS transistors 47 and 49 are turned on. External power supply voltage extVcc2 is applied to internal power supply voltage supply line 53 via pad 155, external power supply voltage supply line 159 and PMOS transistor 47. On the other hand, external power supply voltage extVcc3 is applied to internal power supply voltage supply line 55 via pad 157, external power supply voltage supply line 161 and PMOS transistor 49. Here, external power supply voltage supply lines 159 and 159 are connected from pads 155 and 157 so that the difference between external power supply voltage extVcc2 and internal power supply voltage intVccp is equal to the difference between external power supply voltage extVcc3 and internal power supply voltage intVcca. 161 is supplied with external power supply voltages extVcc2 and extVcc3. That is, external power supply voltages extVcc2 and extVcc3 are applied from pads 155 and 157 to external power supply voltage supply lines 159 and 161 so that (extVcc2−intVccp) = (extVcc3−intVcca). That is, the stress condition for the circuit to which the voltage is supplied from the internal power supply voltage supply line 53 is matched with the stress condition for the circuit to which the voltage is supplied from the internal power supply voltage supply line 55. The other operations during the burn-in test and the method of applying external power supply voltages extVcc2 and extVcc3 from pads 155 and 157 are the same as those of the DRAM according to the second embodiment.

  As described above, in the DRAM according to the second embodiment, two external power supply voltage supply lines are provided, one corresponding to the internal power supply voltage supply line 53 and one corresponding to the internal power supply voltage supply line 38. . Therefore, the stress condition for the circuit to which the voltage is supplied from the internal power supply voltage supply line 53 can be matched with the stress condition for the circuit to which the voltage is supplied from the internal power supply voltage supply line 55. For this reason, the DRAM according to the second embodiment can perform a burn-in acceleration test with higher reliability than the DRAM according to the first embodiment. Further, the same effect as the DRAM according to the first embodiment can be obtained.

(Embodiment 3)
The overall configuration of the DRAM as the semiconductor integrated circuit device according to the third embodiment is the same as that of the DRAM according to the first embodiment (FIG. 1). FIG. 8 is a schematic diagram showing a part of the DRAM according to the third embodiment. 7 that are the same as those in FIG. 7 are assigned the same reference numerals, and descriptions thereof are omitted as appropriate. A PMOS transistor 163 is provided between the external power supply voltage supply line 159 and the external power supply voltage supply line 161. A signal STR is supplied to the gate of the PMOS transistor 163. Here, the burn-in mode detection signal generation circuit for generating burn-in mode detection signal / STR and signal STR is the same as the burn-in mode detection signal generation circuit of FIGS.

  In the normal mode, since the signal STR is at the “L” level, the PMOS transistor 163 is turned on, and the external power supply voltage supply line 159 and the external power supply voltage supply line 161 are connected. On the other hand, in the burn-in test, since the signal STR is at “H” level, the PMOS transistor 163 is turned off and the external power supply voltage supply line 159 and the external power supply voltage supply line 161 are disconnected. As described above, in the burn-in test, external power supply voltage supply line 159 and external power supply voltage supply line 161 are disconnected from each other by a voltage applied from internal power supply voltage supply line 53 as in the DRAM according to the second embodiment. This is because the stress condition for the circuit to be applied matches the stress condition for the circuit to which a voltage is applied from the internal power supply voltage supply line 55. In the normal mode, the external power supply voltage supply line 159 and the external power supply voltage supply line 161 are connected for the following reason. That is, the reliability of the chip is considered. In other words, when a surge such as static electricity is applied to either of the power supply pads 155 or 157, if the external power supply voltage supply line 159 and the external power supply voltage supply line 161 are connected, a region where high voltage is applied can be obtained. This is because it can be dispersed over a wide area and the electric field can be more effectively relaxed. For example, when a surge occurs in the power supply pad 155, since the external power supply voltage supply line 159 and the external power supply voltage supply line 161 are connected, the electric field can be relaxed by the two capacitors 32 and 36. . On the other hand, in the circuit as shown in FIG. 7, for example, when a surge occurs in the power supply pad 155, the external power supply voltage supply line 159 and the external power supply voltage supply line 161 are disconnected, so that only the capacitor 32 is present. Thus, the electric field is relaxed.

  As described above, in the DRAM according to the third embodiment, by providing the PMOS transistor 163, the external power supply voltage supply line 159 and the external power supply voltage supply line 161 are connected in the normal mode. Therefore, the DRAM according to the third embodiment can more effectively reduce the electric field when a surge is applied to either pad 155 or 157 as compared with the DRAM according to the second embodiment.

  Further, as in the DRAM according to the second embodiment, the DRAM according to the third embodiment disconnects the external power supply voltage supply line 159 and the external power supply voltage supply line 161 during the burn-in test, and (extVcc2−intVccp) = External power supply voltages extVcc2 and extVcc3 are applied so as to be (extVcc3-intVcca). Therefore, in the DRAM according to the third embodiment, the stress condition for the circuit to which the voltage is supplied from internal power supply voltage supply line 53 is matched with the stress condition for the circuit to which the voltage is supplied from internal power supply voltage supply line 55. Compared to the DRAM according to the first embodiment, a more reliable burn-in acceleration test can be performed. In addition, the same effect as the DRAM according to the first embodiment is obtained.

(Embodiment 4)
The overall configuration of the DRAM as the semiconductor integrated circuit device according to the fourth embodiment is the same as that of the DRAM according to the first embodiment (FIG. 1). FIG. 9 is a schematic diagram showing a part of the DRAM according to the fourth embodiment. The same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Referring to FIG. 9, PMOS transistor 49 and NMOS transistor 165 are connected in series between external power supply voltage supply line 11 and external power supply voltage supply line 55. Burn-in mode detection signal / STR is applied to the gate of PMOS transistor 49. The NMOS transistor 165 is diode-connected. Here, the burn-in mode detection signal generating circuit for generating burn-in mode detection signal / STR is the same as the burn-in mode detection signal generating circuit shown in FIGS.

  During the burn-in test, burn-in mode detection signal / STR is at "L" level. Therefore, a voltage obtained by stepping down external power supply voltage extVcc by NMOS transistor 165 is applied to internal power supply voltage supply line 55. Here, the NMOS transistor 165 reduces the difference between the external power supply voltage extVcc and the internal power supply voltage intVccp, and the difference between the external power supply voltage extVcc and the internal power supply voltage intVccp. The external power supply voltage extVcc is stepped down so as to be equal to. That is, in the burn-in test, the stress condition for the circuit to which the voltage is supplied from the internal power supply voltage supply line 53 is matched with the stress condition for the circuit to which the voltage is supplied from the internal power supply voltage supply line 55. Other operations in the burn-in test are the same as those of the DRAM according to the first embodiment. The operation in the normal mode is the same as that of the DRAM according to the first embodiment.

  As described above, in the DRAM according to the fourth embodiment, by providing the diode-connected NMOS transistor 165, the stress condition for the circuit to which the voltage is applied from the internal power supply voltage supply line 53 and the internal power supply voltage are provided during the burn-in test. The stress condition for the circuit to which the voltage is supplied from the supply line 55 can be matched. For this reason, the DRAM according to the fourth embodiment can perform a burn-in acceleration test with higher reliability than the DRAM according to the first embodiment. In addition, the same effect as the DRAM according to the first embodiment is obtained.

(Embodiment 5)
In the burn-in test, in order to significantly shorten the burn-in time, a plurality of word lines are activated, a word line driving voltage is supplied from a pad, and a gate oxide film reliability test is sometimes performed. Such a mode is called a multiple word line drive mode. In this case, the magnitude of the word line driving voltage is the same as the boosted voltage Vpp generated by the internal boosted voltage generating circuit. The reason why the voltage for driving the word line is supplied from the pad is that the internal boost voltage generation circuit has insufficient capability.

  FIG. 10 is a diagram for explaining a problem in a burn-in test in a general DRAM. Referring to FIG. 10, a typical DRAM includes a pad 167, a PMOS transistor 169, and a word driver 171. In the multiple word line drive mode, since the signal / BIAC is at the “L” level, the PMOS transistor 169 is on. Therefore, a word line driving voltage is applied from the pad 167 to the word driver 171. However, in the circuit configuration as shown in FIG. 10, in the process of applying the first test voltage to the word driver 171, excess current flows to the aluminum wiring via the pad 167 and is temporarily generated. Due to the excessive current, chip failure due to aluminum migration may occur. An object of the DRAM as the semiconductor integrated circuit device according to the fifth embodiment is to prevent such excessive current.

  FIG. 11 is a schematic block diagram showing the overall configuration of the DRAM according to the fifth embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Referring to FIG. 11, the DRAM according to the fifth embodiment includes a BIAC detection circuit (test voltage supply circuit) 173 and a boosted voltage generation circuit 175. Boosted voltage generation circuit 175 generates boosted voltage Vpp and applies it to Vpp supply line 177. Boosted voltage Vpp is applied to row decoder 25 and sense amplifier row 31 from Vpp supply line 177. The reason why the boosted voltage Vpp is supplied to the row decoder 25 is to drive the word line at the “H” level. The reason why the boosted voltage Vpp is supplied to the sense amplifier row 31 is to drive the bit line at the “H” level. The BIAC detection circuit 173 detects a plurality of word line drive modes, and restricts current from the pad to the Vpp supply line while applying a word line drive voltage (hereinafter referred to as “first test voltage”) having the same magnitude as the boost voltage Vpp. Supply). Here, since the multiple word line drive mode is a test for testing the reliability of the gate oxide film of the memory cell transistor, the / OE input pad 15 is not used. Therefore, the first test voltage is applied from / OE input pad 15 in the multiple word line drive mode.

  FIG. 12 is a schematic diagram showing a part of the DRAM according to the fifth embodiment. Note that portions similar to those in FIG. 11 are denoted by the same reference numerals, and description thereof is omitted as appropriate. Referring to FIG. 12, the DRAM according to the fifth embodiment includes / OE input pad 15, BIAC detection circuit 173, boosted voltage generation circuit 175, and word driver 171. BIAC detection circuit 173 includes a constant current source 187 and PMOS transistors 181, 183 and 185. Constant current source 187 is provided between node N11 and a node having a ground voltage. The PMOS transistor 181 is provided between the node N10 and the node N11. PMOS transistors 183 and 185 are connected in series between node N10 and Vpp supply line 177. The gates of PMOS transistors 181 and 183 are connected to node N11. A signal / BIAC is applied to the gate of the PMOS transistor 185. Word driver 171 is connected to Vpp supply line 177. Boosted voltage generation circuit 175 is connected to Vpp supply line 177.

  In the multiple word line drive mode (during burn-in test), since the signal / BIAC is at the “L” level, the PMOS transistor 185 is turned on. In the multiple word line drive mode, boosted voltage generation circuit 175 is inactivated. Therefore, the first test voltage is applied from the / OE input pad 15 to the word driver 171. Then, the word driver 171 applies this first test voltage to the word line WL. FIG. 12 shows only one word driver 171 and one word line WL, but actually there are a plurality of word drivers and a plurality of word lines. A first test voltage is applied to the word driver, and a first test voltage is applied to the plurality of word lines. Here, since the PMOS transistors 181 and 183 constitute a current mirror circuit, the current flowing through the PMOS transistor 185 is limited according to the current generated by the constant current source 187. In other words, it is possible to prevent an excessive current from flowing into / Vpp supply line 177 from / OE input pad 15 in the multiple word line drive mode (during burn-in test). The constant current source 187 and the current mirror circuit (PMOS transistors 181 and 183) constitute a current limiting circuit.

  In the normal mode, the signal / BIAC is at “H” level, and the PMOS transistor 185 is off. On the other hand, boosted voltage generation circuit 175 generates boosted voltage Vpp and provides boosted voltage Vpp to word driver 171. Word driver 171 applies boosted voltage Vpp to word line WL selected by the row address signal.

  FIG. 13 is a circuit diagram showing details of the boosted voltage generation circuit 175 of FIG. Note that portions similar to those in FIG. 12 are denoted by the same reference numerals, and description thereof is omitted as appropriate. Referring to FIG. 13, the boosted voltage generating circuit includes a NAND circuit 189, an inverter 191, capacitors 193, 195, 197, and NMOS transistors 199, 201, 203, 205, 207, 209. One input node of NAND circuit 189 is supplied with clock signal CLK, and the other input node is supplied with signal / BIAC. One end of capacitor 193 is connected to the output node of NAND circuit 189. The other end of the capacitor 193 is connected to the gates of the NMOS transistors 203 to 207 and the sources of the NMOS transistors 199 and 203. NMOS transistor 199 has its gate and drain connected to a node having power supply voltage Vcc. NMOS transistor 201 is connected to a node having power supply voltage Vcc and the drain of NMOS transistor 203. The gate of the NMOS transistor 201 is connected to the drain of the NMOS transistor 203. An input node of inverter 191 is connected to an output node of NAND circuit 189. One ends of capacitors 195 and 197 are connected to the output node of inverter 191. The other end of the capacitor 195 is connected to the source of the NMOS transistor 207 and the gate of the NMOS transistor 209. The other end of the capacitor 197 is connected to one source / drain of the NMOS transistor 209. NMOS transistor 205 is connected between a node having power supply voltage Vcc and the other end of capacitor 197. The other source / drain of NMOS transistor 209 is connected to Vpp supply line 177. NMOS transistor 207 is provided between a node having power supply voltage Vcc and the gate of NMOS transistor 209.

  In the normal mode, since signal / BIAC is at “H” level, clock signal CLK is applied to capacitor 193 and inverter 191. In response to clock signal CLK, boosted voltage Vpp is generated on Vpp supply line 177. In the multiple word line drive mode, since signal / BIAC is at "L" level, clock signal CLK is not applied to capacitor 193 and inverter 191, and the boosted voltage generation circuit is inactivated.

  The configuration of the circuit for generating signal / BIAC is the same as that of the burn-in mode detection signal generating circuit shown in FIGS. In this case, the signal / BIAC corresponds to the burn-in detection signal / STR generated by the burn-in mode detection signal generation circuit of FIG. 5, and the signal BIAC corresponds to the signal STR.

  As described above, the DRAM according to the fifth embodiment is provided with the current limiting circuit (consisting of the constant current source 187 and the PMOS transistors 181 and 183). It is possible to prevent the current from flowing into the Vpp supply line 177.

(Embodiment 6)
The overall configuration of the DRAM as the semiconductor integrated circuit device according to the sixth embodiment is the same as that of the DRAM according to the fifth embodiment (FIG. 11). That is, the DRAM according to the sixth embodiment is premised on the DRAM according to the fifth embodiment.

  FIG. 14 is a circuit diagram showing details of a memory cell of a DRAM according to the sixth embodiment. Note that portions similar to those in FIG. 12 are denoted by the same reference numerals, and description thereof is omitted as appropriate. Referring to FIG. 14, the DRAM memory cell according to the sixth embodiment includes a memory cell transistor 211 and a memory cell capacitor 213. Memory cell transistor 211 is provided between bit line BL and storage node SN. The gate of the memory cell transistor 211 is connected to the word line WL. One end of capacitor 213 is connected to storage node SN. Depending on the memory cell, memory cell transistor 211 is connected between bit line / BL and storage node SN. Here, the bit line BL and the bit line / BL constitute a bit line pair. In the DRAM according to the sixth embodiment, the reliability test of the memory cell capacitor 213 is performed simultaneously with the reliability test of the gate oxide film of the memory cell transistor 211 described in the fifth embodiment. That is, in order to perform a reliability test of the gate oxide film of the memory cell transistor 211, the potential of the bit line BL is set to the “L” level (GND level) when the word line WL is activated, and the memory cell capacitor The other end (cell plate) of 213 is set to the “H” level (Vcc level). By doing so, since the word line WL is activated, a sufficient potential is supplied to the memory cell capacitor 213, and the reliability test of the memory cell capacitor 213 is performed in accordance with the reliability of the gate oxide film of the memory cell transistor 211. Can be done at the same time as the test.

  Next, the operation of the DRAM when the bit line BL (/ BL) is set to the “L” level (“GND” level) for the reliability test of the memory cell capacitor 213 will be described in detail. FIG. 15 is a circuit diagram showing details of a part of the DRAM according to the sixth embodiment. The DRAM according to the sixth embodiment includes a sense amplifier composed of PMOS transistors 231, 233, 235 and NMOS transistors 221, 223, 225, a sense amplifier control circuit composed of OR circuit 239 and AND circuit 241, NMOS transistors 215, 217, 219, an OR circuit 237, an inverter 243, and an equalize / precharge circuit comprising NMOS transistors 227 and 229. The DRAM also includes a bit line pair BL, / BL. Referring to FIG. 15, the output node of OR circuit 239 is connected to the gate of PMOS transistor 231. Signal S0P1 is applied to one input node of OR circuit 239, and signal BIAC is applied to the other input node. The output node of the AND circuit 241 is connected to the gate of the NMOS transistor 225. Signal S0N1 is applied to one input node of AND circuit 241 and signal / BIAC is applied to the other input node. The output node of the OR circuit 237 is connected to the gates of the NMOS transistors 215 to 219. A signal BLEQ1 is applied to one input node of the OR circuit 237, and a signal BIAC is applied to the other input node. The NMOS transistor 227 is provided between the node having the ground voltage and the precharge voltage supply line VBL2. A signal BIAC is supplied to the gate of the NMOS transistor 227. The NMOS transistor 229 is provided between the precharge voltage supply line VBL1 and the precharge voltage supply line VBL2. A signal obtained by inverting the signal BIAC by the inverter 243 is applied to the gate of the NMOS transistor 229.

  In the normal mode, signal BIAC is at "L" level and signal / BIAC is at "H" level. Therefore, when “H” level sense amplifier activation signal S0N1 is applied to AND circuit 241, signal S0N2 is also at “H” level. On the other hand, when “L” level sense amplifier activation signal S0P1 is applied to OR circuit 239, signal S0P2 also goes to “L” level. As described above, the NMOS transistor 225 and the PMOS transistor 231 are turned on, and the sense amplifier is activated.

  In the normal mode, when the sense amplifier is deactivated, the signal BLEQ1 is set to the “H” level, so that the signal BLEQ2 is also set to the “H” level. As a result, the NMOS transistors 215 to 219 are all turned on. On the other hand, in the normal mode, since the signal BIAC is at the “L” level, the NMOS transistor 227 is turned off and the NMOS transistor 229 is turned on. Therefore, a voltage (1/2 Vcc) that is ½ of the power supply voltage Vcc is supplied to the bit line pair BL, / BL. That is, the bit line pair BL, / BL is precharged. When the sense amplifier is activated (at the time of sensing), the signal BLEQ1 becomes “L” level, and therefore the signal BLEQ2 becomes “L” level. As a result, the NMOS transistors 215 to 219 are all turned off, and the bit line BL and the bit line / BL are disconnected. Sense is started after the bit line BL and the bit line / BL are disconnected.

  When the test mode (multiple word line drive mode) is entered, that is, when the reliability test of the gate oxide film of the memory cell transistor and the reliability test of the memory cell capacitor are performed, the signal BIAC becomes “H” level. , Signal / BIAC attains “L” level. Therefore, the signal S0N2 becomes “L” level. Further, the signal S0P2 becomes “H” level. In this way, the sense amplifier is deactivated when the test mode is entered. On the other hand, since the signal BLEQ2 becomes “H” level, all of the NMOS transistors 215 to 219 are turned on. Since the signal BIAC is at “H” level, the NMOS transistor 227 is turned on and the NMOS transistor 229 is turned off. As a result, the ground voltage is applied to the precharge voltage supply line VBL2. That is, the ground voltage is applied to the bit lines BL and / BL. The above has been described for one set of bit line pairs. However, as described above, the precharge voltage is also applied to the plurality of bit line pairs BL and / BL provided in the memory cell array 33 (FIG. 11) in the normal mode. In the test mode, the ground voltage is supplied.

  As described above, the DRAM according to the sixth embodiment is premised on the DRAM according to the fifth embodiment, and when the reliability test of the gate oxide film of the memory cell transistor is performed, the bit line pair BL, / BL has a ground voltage. And the power supply voltage Vcc is applied to the cell plate. Therefore, in the DRAM according to the sixth embodiment, the reliability test of the memory cell capacitor can be performed simultaneously with the reliability test of the gate oxide film of the memory cell transistor. Further, since the DRAM according to the sixth embodiment is premised on the DRAM according to the fifth embodiment, the same effects as the DRAM according to the fifth embodiment are obtained.

1 is a schematic block diagram showing an overall configuration of a DRAM according to a first embodiment of the present invention. 1 is a schematic diagram showing a part of a DRAM according to a first embodiment of the present invention; It is a circuit diagram which shows the detail of the intVcc generation | occurrence | production unit of FIG. FIG. 4 is a circuit diagram showing details of a differential amplifier section for generating an internal power supply voltage intVcca shown in FIG. 3. FIG. 3 is a circuit diagram showing details of a burn-in mode detection signal generating circuit that generates the burn-in mode detection signal / STR shown in FIG. 2. FIG. 6 is a circuit diagram showing details of the super VIH detection circuit of FIG. 5. It is the schematic which shows a part of DRAM by Embodiment 2 of this invention. It is the schematic which shows a part of DRAM by Embodiment 3 of this invention. It is the schematic which shows a part of DRAM by Embodiment 4 of this invention. FIG. 10 is a diagram for explaining a problem of a general DRAM when a test for reliability evaluation is performed. It is a schematic block diagram which shows the whole structure of DRAM by Embodiment 5 of this invention. FIG. 10 is a circuit diagram showing in detail a part of a DRAM according to a fifth embodiment of the present invention. FIG. 13 is a circuit diagram showing details of the boost voltage generation circuit of FIG. 12. It is a circuit diagram which shows the detail of the memory cell of DRAM by Embodiment 6 of this invention. It is a circuit diagram which shows a part of DRAM by Embodiment 6 of this invention in detail. It is the schematic which shows a part of conventional DRAM. It is a circuit diagram which shows a part of voltage drop circuit (VDC) of FIG. 16 in detail.

Explanation of symbols

  1 / CAS input pad, 3 / RAS input pad, 5 / W input pad, 7 address signal input pad group, 9 external power supply voltage input pad group, 11 ground voltage input pad group, 13 data input / output pad group, 15 / OE Input pad, 17 clock generation circuit, 19 intVcc generation unit, 21,149 logic gate, 23 row and column address buffer, 25 row decoder, 27 column decoder, 29 input / output circuit, 31 sense amplifier row, 32, 34, 36, 38,193-197 Capacitor, 33 Memory cell array, 35 Input buffer, 37 Output buffer, 41, 155, 157 Power supply pad, 43, 45, 245 Voltage drop circuit (VDC), 47, 49, 67-85, 103-109 , 139, 163, 169, 181 to 185, 231 235 PMOS transistor, 51, 159, 161 External power supply voltage supply line, 53, 55, 247 Internal power supply voltage supply line, 57, 187 Constant current source, 59 Vrefa generation circuit, 61 Vrefp generation circuit, 63, 65 Differential amplifier section 87, 89, 97-101, 131, 133, 153, 165, 199-209, 215-229 NMOS transistor, 91 resistance element, 93, 95 differential amplifier, 111, 241 AND circuit, 113 address signal input pad, 115 Super VIH detection circuit, 117-121,189 NAND circuit, 123-127,141,143,151,191,243 inverter, 129 input protection circuit, 145 reset circuit, 147 delay circuit, 171 word driver, 173 BIAC detection circuit 1 5 step-up voltage generator, 177 Vpp supply line, 211 a memory cell transistor, 213 a memory cell capacitor, 237, 239 OR circuit, 167 a pad.

Claims (4)

A plurality of memory cells arranged in a matrix of rows and columns;
A plurality of word lines arranged corresponding to each row and connected to the corresponding memory cells;
A plurality of driver means provided corresponding to each word line;
A test voltage supply means for supplying a first test voltage to each of the driver means via a voltage supply line based on an external power supply voltage in a test mode for reliability evaluation;
In a normal mode other than the test mode, a boosted voltage generating means for generating a boosted voltage and supplying the boosted voltage to the driver means;
In the normal mode, the driver means corresponding to the selected word line supplies a voltage to the corresponding word line based on the boosted voltage,
In the test mode, each driver means supplies a voltage to the corresponding word line based on the first test voltage,
The test voltage supply means includes
A semiconductor integrated circuit device comprising current limiting means for limiting a current flowing into the voltage supply line. The current limiting means includes
A constant current source for generating a constant current;
2. The semiconductor integrated circuit device according to claim 1, further comprising current mirror means. A plurality of bit line pairs arranged corresponding to the respective columns and connected to the memory cells in the corresponding columns;
Each memory cell has
A memory cell transistor;
Including a memory cell capacitor,
The control electrode of the memory cell transistor is connected to the corresponding word line, the first electrode of the memory cell transistor is connected to the corresponding bit line of the corresponding bit line pair, and the first electrode of the memory cell transistor Two electrodes are connected to one end of the memory cell capacitor,
2. The semiconductor integrated circuit device according to claim 1, wherein a second test voltage is applied to the other end of each memory cell capacitor and a ground voltage is applied to each bit line pair in the test mode. A plurality of sense amplifiers provided corresponding to the respective bit line pairs and amplifying a potential difference between the bit lines of the corresponding bit line pairs;
Equalizing / precharging means for setting each bit line pair to a predetermined potential;
In the test mode, further comprising sense amplifier control means for stopping the operation of each sense amplifier,
4. The semiconductor integrated circuit device according to claim 3, wherein said equalize / precharge means sets each bit line pair to a ground potential in the test mode.

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