JP2006253438A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of obtaining many kinds of identification information effectively using a small number of resistive elements. <P>SOLUTION: The semiconductor device 1 is equipped with a semiconductor substrate 10, n (n is an integer of two or above) resistive elements 20, interconnect lines 30, and terminals 40a and 40b. The resistive elements 20 are set different from each other in resistance value and constitute a circuit element group. Concretely, provided that the resistive element having the smallest resistance value of all the other n resistive elements has a resistance value of R, the resistance values of the residual (n-1) resistive elements 20 are represented by 2<SP>j</SP>×R (j=1, 2, ..., n-1), respectively. The k (k is an integer of 1 to n) resistive elements 20 out of the n resistive element 20 are electrically interconnected with each other by the interconnect lines 30. By this setup, the sum of the resistance values of the k resistive elements 20 appears between the terminals 40a and 40b. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In general, in the manufacture of a semiconductor device, a plurality of semiconductor devices are obtained from a single wafer. These semiconductor devices are shipped after being packaged. At that time, if no means are taken, information such as the manufacturing lot number, wafer number, or position in the wafer of each semiconductor device will not be known.

  In view of this, a method for marking identification information for identifying each semiconductor device on a package has also been proposed. However, the seal disappears after the package is opened for failure analysis or the like. Further, when a semiconductor device is shipped without packaging, it is impossible even to seal it.

  On the other hand, methods for storing identification information in the semiconductor device itself have also been proposed (Patent Documents 1 to 4). For example, in the semiconductor device described in Patent Document 1, a plurality of resistance elements having different resistance values are provided, and a combination of their connection relation and resistance value ratio is used as identification information.

Moreover, in the semiconductor device described in Patent Document 2, a resistive element on a line, a plurality of contacts provided at equal intervals on the resistive element, and three measurement terminals are provided. Of these three measurement terminals, the first and second terminals are respectively connected to a contact provided at one end of the resistance element and a contact adjacent thereto. Then, by making the contact to which the remaining third terminal is connected different for each semiconductor device, the resistance value appearing between the first and second terminals and the resistance value appearing between the first and third terminals are The ratio is used as identification information.
Japanese Patent Laid-Open No. 5-102263 JP-A-5-218207 JP-A-5-315207 JP 2000-21694 A

  By the way, in these semiconductor devices, it is preferable that various types of identification information can be efficiently obtained by using a small number of resistance elements from the viewpoint of miniaturization of the entire device. However, the methods described in Patent Documents 1 and 2 have room for improvement in terms of efficiency.

The semiconductor device according to the present invention includes a circuit element group composed of n (n is an integer of 2 or more) circuit elements having different characteristic values, and k (k is 1 or more and n) among the n circuit elements. (The following integer) are electrically connected to each other, and first and second characteristic value measuring terminals respectively connected to two different locations of the wiring, and the n circuit elements are connected to each other. When the minimum characteristic value is X, the characteristic values of the other n−1 circuit elements are expressed as 2 ^j · X (j = 1, 2,..., N−1), respectively. The wiring connects the k circuit elements to each other so that a sum of the characteristic values of the k circuit elements appears between the first and second characteristic value measuring terminals. And

In this semiconductor device, n circuit elements having characteristic values represented by X, 2X, 2 ² X,..., 2 ⁿ⁻¹ X are provided. Some or all of these circuit elements are electrically connected by wiring, and the sum of the characteristic values of the connected circuit elements appears between the first and second characteristic value measuring terminals. Yes. Here, all 2 ⁿ −1 integers from 1 to 2 ⁿ −1 are k integers selected from n integers ¹ , 2, 2 ² ,..., 2 ^n−1. Is obtained as the sum of Therefore, by using the sum of the characteristic values appearing between the first and second characteristic value measuring terminals as identification information, 2 ⁿ −1 types of identification information can be obtained from ⁿ circuit elements.

In addition, a method of manufacturing a semiconductor device according to the present invention includes a circuit element forming step of forming n (n is an integer of 2 or more) circuit elements having different characteristic values on a semiconductor substrate, and the n circuit elements. Of these, k (k is an integer of 1 or more and n or less) wiring forming step for forming wirings that are electrically connected to each other, and the first and second characteristics are connected to two different locations of the wirings, respectively. A terminal forming step of forming a value measuring terminal, and in the circuit element forming step, when the minimum characteristic value of the n circuit elements is X, another n-1 The circuit elements are formed such that the characteristic values of the circuit elements are expressed as 2 ^j · X (j = 1, 2,..., N−1), respectively. Sum of the characteristic values of the k circuit elements connected to each other The wiring is formed in such a manner that appears between the first and second characteristic value measuring terminals.

According to this manufacturing method, a semiconductor device provided with n circuit elements having characteristic values represented as X, 2X, 2 ² X,..., 2 ⁿ⁻¹ X, respectively, is manufactured. In the semiconductor device, some or all of these circuit elements are electrically connected by wiring, and the sum of the characteristic values of the connected circuit elements is between the first and second characteristic value measuring terminals. It is configured to appear. Therefore, by using the sum of the characteristic values appearing between the first and second characteristic value measuring terminals as identification information, a semiconductor device capable of obtaining 2 ⁿ −1 types of identification information from ⁿ circuit elements. Is obtained.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can obtain many types of identification information efficiently, and its manufacturing method are implement | achieved.

  Hereinafter, preferred embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. The semiconductor device 1 includes a semiconductor substrate 10, a resistance element 20 (circuit element), a wiring 30, and terminals 40a and 40b. The semiconductor substrate 10 is a silicon substrate, for example.

On the semiconductor substrate 10, n (n is an integer of 2 or more) resistance elements 20 are formed. These resistance elements 20 have different resistance values (characteristic values) and constitute a circuit element group. Specifically, when the resistance value (reference resistance value) of the resistance element (reference resistance) having the minimum resistance value among the n resistance elements 20 is R, other n−1 resistance elements 20 The resistance values are expressed as 2 ^j · R (j = 1, 2,..., N−1), respectively. That is, the n resistance values are R, 2R, 2 ² R,..., 2 ⁿ⁻¹ R in ascending order. In addition, it is preferable that the value of n is 8 or more.

  The resistance element 20 is connected to the wiring 30 by a contact plug 52. The wiring 30 electrically connects k (k is an integer of 1 to n) of the n resistive elements 20 to each other. These k resistance elements 20 are connected in series with each other. Thereby, the sum of the resistance values of the k resistance elements 20 appears between terminals 40a and 40b, which will be described later. In the present embodiment, the wiring 30 is formed in multiple layers. The wirings of different layers are connected to each other by via plugs 54.

  A terminal 40a (first characteristic value measuring terminal) and a terminal 40b (second characteristic value measuring terminal) are connected to the uppermost wiring 30. These terminals 40 a and 40 b are pads for measuring the sum of resistance values of the resistance element 20 connected by the wiring 30 from the outside of the semiconductor device 1, and are connected to two different locations of the wiring 30, respectively. Specifically, the terminals 40a and 40b are respectively connected to both ends of a combined resistor formed by connecting the k resistance elements 20 in series. The terminals 40a and 40b for measuring the sum of the resistance values have the same shape as normal pads used for signal input / output of the semiconductor device. When the semiconductor device is packaged, the terminals 40a and 40b are used. Shall be connected to an external terminal so that measurement can be performed from the outside.

  With reference to FIG. 2, an example of the connection relationship among the resistance element 20, the wiring 30, and the terminals will be described. In the figure, four resistance elements 201, 202, 203, and 204 having resistance values of R, 2R, 4R, and 8R are provided. In this example, one end of the resistance element 204 is connected to the terminal 40a. In addition, two terminals are connected to both ends of the resistance element 201 which is a reference resistance. These terminals 421 to 424 (reference resistance measurement terminals) are terminals for measuring the resistance value of the reference resistance. Specifically, terminals 421 and 422 are connected to one end of the resistance element 201, and terminals 423 and 424 are connected to the other end. The terminal 40b described above is shared with the terminal 421.

  Further, the resistance elements 201, 203, and 204 are connected to each other in series by the wiring 30. That is, in this example, k = 3. As a result, a resistance value of 13R appears as a combined resistance of these three resistance elements 201, 203, and 204 between the terminals 40a and 40b.

  Note that it is not essential to provide all the terminals 421 to 424, and one terminal may be provided at each of both ends. Further, if the resistance value of the reference resistor is known, the reference resistance measurement terminal may not be provided. However, in this example, since the terminal 421 is shared with the terminal 40b, the terminal 421 is provided even when the reference resistance measurement terminal is not provided.

FIG. 3 is a circuit diagram showing an example of the configuration of the circuit element group. However, this figure shows a state in which the resistance elements are not connected to each other. In this example, eight resistance elements 211 to 218 each having a resistance value of 2 ^j−1 · R (j = 1, 2,..., 8) are provided. Moreover, in order to connect these resistance elements 211-218 arbitrarily, it is comprised so that a contact can be taken at each both ends of each resistance element.

  The resistance values of the wiring 30, contact plug 52, and via plug 54 are preferably 1% or less of R, more preferably 0.1% or less of R. The contact resistance value when a measuring instrument such as a probe is brought into contact with the terminals 40a and 40b is preferably 1% or less of the above R, more preferably 0.1% or less of the above R. Further, when the semiconductor device is packaged, the resistance value from the terminals 40a and 40b to the external terminal is preferably 1% or less of the R, and more preferably 0.1% or less of the R.

Next, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described together with a method for manufacturing the semiconductor device 1. In the manufacturing method according to the present embodiment, a circuit element forming step of forming n resistance elements 20 having different resistance values on the semiconductor substrate 10 and k of the n resistance elements 20 are electrically connected to each other. A wiring forming process for forming the wiring 30 to be performed, and a terminal forming process for forming the terminals 40a and 40b so as to be connected to two different locations of the wiring 30, respectively. Here, in the circuit element formation step, when the minimum resistance value of the n resistance elements 20 is R, the resistance values of the other n−1 resistance elements 20 are 2 ^j · R and As shown, the resistance element 20 is formed. Further, in the wiring formation step, the wiring 30 is formed so that the sum of the resistance values of the k resistance elements 20 connected to each other by the wiring 30 appears between the terminals 40a and 40b.

  Specific examples of the method for manufacturing the semiconductor device 1 include the following. In this example, a silicon substrate is used as the semiconductor substrate 10. First, a diffusion layer region and an element isolation region are formed on a silicon substrate. Next, ion implantation for forming a transistor is performed. Subsequently, a silicon oxide film to be a gate oxide film is formed.

  Thereafter, a polycrystalline silicon film to be a gate electrode is formed. This polycrystalline silicon may contain germanium. Subsequently, the polycrystalline silicon is patterned using photolithography or the like to form a gate electrode. At this time, the polycrystalline silicon on the element isolation region is patterned and designed to have a desired resistance value, and a circuit element group is formed (circuit element forming step).

  Next, ion implantation for forming a transistor is performed. Subsequently, the diffusion layer and the upper part of the gate electrode are silicided. At this time, in this example, in order to obtain a desired resistance value, the upper part of the circuit element group is not silicided. In order to prevent silicidation, a silicon oxide film is formed on the entire surface of the wafer. Thereafter, only the silicon oxide film to be silicided is removed by a method such as photolithography or etching. At this time, the silicon oxide film on the circuit element group is not removed.

  Next, a metal such as Ti, Co, or Ni is formed on the entire surface of the wafer, silicidized, and then the excess metal is removed. Subsequently, as an interlayer insulating film, an insulating film having a silicon oxide film or a laminated structure of a silicon nitride film and a silicon oxide film is formed on the entire surface of the wafer. Thereafter, contact plugs 52 are formed so as to be connected to both ends of each resistance element 20 of the circuit element group.

  Next, a wiring layer is formed on the contact plug 52. Subsequently, a via plug 54 is formed in the wiring layer so as to be connected to the wiring 30. In the same manner, an arbitrary number of wiring layers are formed so as to be electrically connected to each resistance element 20 of the circuit element group. Furthermore, each resistance element 20 of the circuit element group is connected using EB (electron beam) drawing so as to have different resistance values among a plurality of semiconductor devices manufactured on the wafer (wiring forming step). ). Thereafter, terminals 40a and 40b are formed (terminal forming step). Thus, the semiconductor device 1 of FIG. 1 is obtained.

  In the wiring formation step, for example, for the first semiconductor device, only the resistance element having the resistance value R is connected so that the resistance value R appears between the terminals 40a and 40b. For the second semiconductor device, only the resistance element having the resistance value 2R is connected so that the resistance value 2R appears between the terminals 40a and 40b. Further, for the third semiconductor device, the resistance value R and the resistance value 2R are connected in series so that the resistance value 3R appears between the terminals 40a and 40b.

  Note that wirings other than the circuit element group in the semiconductor device 1 may be patterned by a photolithography technique. At this time, the region to which each resistance element 20 of the circuit element group is connected is not patterned. Subsequently, in order to connect each resistance element 20 of the circuit element group, only the region is patterned by EB direct drawing to form a wiring 30.

The effect of this embodiment will be described. In the semiconductor device 1, n resistive elements 20 having resistance values represented as R, 2R, 2 ² R,..., 2 ⁿ⁻¹ R are provided. And some or all of these resistance elements 20 are connected by the wiring 30, and the sum of the resistance values of the connected resistance elements 20 appears between the terminals 40a and 40b. Here, all 2 ⁿ⁻¹ integers from 1 to 2 ⁿ −1 are k integers selected from n integers ¹ , 2, 2 ² ,..., 2 ^n−1. Is obtained as the sum of Therefore, by using the sum of the resistance values appearing between the terminals 40a and 40b as identification information, 2 ⁿ −1 types of identification information can be obtained from ⁿ resistance elements. For this reason, in the semiconductor device 1, it is possible to efficiently obtain various types of identification information even if a few resistance elements are used.

By the way, there are _n C ₁ + _n C ₂ +... + _N C _n = 2 ⁿ −1 combinations when k are selected from n integers. It is clear from the binomial theorem: (1 + 1) ⁿ = _n C ₀ + _n C ₁ + _n C ₂ +... + _N C _n that this equation holds. Here, in the semiconductor device 1, as described above, 2 ⁿ −1 types of identification information are obtained using n resistance elements. That is, there is a one-to-one correspondence between the combination when selecting k elements from n resistance elements and the identification information (the sum of resistance values here) obtained thereby. In other words, there is no duplication of identification information between different combinations. This also shows that in the semiconductor device 1, various types of identification information are efficiently obtained from the n resistance elements.

  For the semiconductor device 1 having such a configuration, Patent Document 3 discloses a method of forming a dot matrix using a laser marker. Patent Document 4 discloses a method of writing character information by converting character information into a binary system and cutting a prepared fuse with a laser.

  However, in the method of writing information so that it can be read visually like the methods described in these documents, in the case of a packaged semiconductor device, the information cannot be read unless it is opened. It is also possible to write similar information on the package. However, in that case, information must be written twice in the semiconductor device and in the package. In this respect, according to the semiconductor device 1, the identification information written in the semiconductor device can be read out electrically, so that the identification information can be read out without opening the package.

  In addition, as another method for storing identification information in a semiconductor device, it may be possible to mount a nonvolatile memory in the semiconductor device. However, this increases the number of manufacturing steps. In this regard, according to the present embodiment, it is possible to store identification information in the semiconductor device 1 without increasing the number of manufacturing steps.

  In the present embodiment, the circuit element is a resistance element, and the characteristic value is the resistance value. Therefore, n circuit elements having different characteristic values can be realized with a simple configuration.

When the value of n is 8 or more, the effect of the semiconductor device 1 that various types of identification information can be efficiently obtained from a few resistor elements becomes remarkable. For example, when n = 8, 2 ⁸ −1 = 255 kinds of identification information can be obtained from only 8 resistance elements.

  As shown in FIG. 2, when two terminals are provided at both ends of the reference resistor, the resistance value of the reference resistor can be measured as a Kelvin pattern.

  In addition, when at least one of the terminals 40a and 40b is shared with the reference resistance measurement terminal, the number of terminals can be reduced as compared with the case where the terminals are not shared, so that the configuration of the semiconductor device 1 is simplified.

  By forming the wiring 30 by EB direct drawing, it is possible to easily form the wiring 30 having a different pattern between a plurality of semiconductor devices.

  By the way, EB direct drawing is inferior in throughput as compared with photolithography. In this regard, while the wiring 30 is formed by EB direct drawing, wiring other than the circuit element group in the semiconductor device 1 is formed by a photolithography technique, so that each semiconductor device has a different resistance value while suppressing a decrease in throughput. A combined resistor can be formed. However, an EB stepper may be used instead of photolithography, and in this case, the same effect as described above can be obtained.

The semiconductor device according to the present invention is not limited to the above embodiment, and various modifications are possible. For example, although the resistance element is used as the circuit element in the above embodiment, a capacitive element may be used as the circuit element. In that case, the characteristic value is the capacitance value. The wiring 30 connects k of the n capacitive elements in parallel with each other. Thereby, 2 ⁿ −1 types of identification information can be obtained as the sum of the capacitance values.

In addition, a plurality of circuit element groups including n circuit elements may be provided. When m circuit element groups are provided (m is an integer of 2 or more), (2 ⁿ −1) ^m types of identification information can be obtained. As a result, more types of identification information can be obtained. The value of m is preferably 4 or more. For example, when n = 8 and m = 4, (2 ⁸ −1) ⁴ = about 4.2 billion identification information is obtained.

  Further, when a plurality of circuit element groups are provided, any one of the terminals 40a and 40b may be shared between the plurality of circuit elements. In that case, the configuration of the semiconductor device 1 is simplified. Further, when a reference resistance measurement terminal is provided, a reference resistance measurement terminal connected to one end of the reference resistor may be shared among a plurality of circuit elements. Even in that case, the configuration of the semiconductor device 1 can be simplified.

1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. FIG. 2 is a plan view for explaining an example of a connection relationship among resistance elements, wirings, and terminals in the semiconductor device of FIG. 1. It is a circuit diagram which shows an example of a structure of a circuit element group.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor substrate 20 Resistance element 30 Wiring 40a, 40b Characteristic value measurement terminal 52 Contact plug 54 Via plug 201,202,203,204 Resistance element 421,422,423,424 Reference resistance measurement terminal

Claims (7)

A circuit element group composed of n (n is an integer of 2 or more) circuit elements having different characteristic values;
A wiring for electrically connecting k (k is an integer of 1 to n) among the n circuit elements;
First and second characteristic value measuring terminals respectively connected to two different locations of the wiring,
When the minimum characteristic value among the n circuit elements is X, the characteristic values of the other n−1 circuit elements are 2 ^j · X (j = 1, 2,..., Respectively). n-1),
The wiring connects the k circuit elements to each other so that a sum of the characteristic values of the k circuit elements appears between the first and second characteristic value measuring terminals. A semiconductor device. The semiconductor device according to claim 1,
The semiconductor device, wherein the circuit element is a resistance element, and the characteristic value is a resistance value of the resistance element. The semiconductor device according to claim 2,
A semiconductor device in which two reference resistance measurement terminals for measuring the resistance value of the resistance element are connected to both ends of the resistance element having the minimum resistance value among the n resistance elements. The semiconductor device according to claim 3.
A semiconductor device in which at least one of the first and second characteristic value measuring terminals is shared with the reference resistance measuring terminal. The semiconductor device according to claim 1,
A semiconductor device in which a plurality of the circuit element groups are provided. A circuit element forming step of forming n (n is an integer of 2 or more) circuit elements having different characteristic values on a semiconductor substrate;
A wiring forming step of forming wirings that electrically connect k (k is an integer of 1 to n) among the n circuit elements;
Forming a first and second characteristic value measurement terminal so as to be connected to two different locations of the wiring, respectively,
In the circuit element forming step, when the minimum characteristic value of the n circuit elements is X, the characteristic values of the other n−1 circuit elements are 2 ^j · X (j = 1, 2,..., N−1), forming the circuit element,
In the wiring forming step, the wiring is formed so that a sum of the characteristic values of the k circuit elements connected to each other by the wiring appears between the first and second characteristic value measuring terminals. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 6,
In the wiring formation step, a method for manufacturing a semiconductor device, wherein the wiring is formed by direct drawing of an electron beam.

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