JP2006253338A - Semiconductor apparatus, led head and image forming apparatus employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus in which contact characteristics of an anode wiring layer and a cathode wiring layer as a metal wiring layer and an interlayer dielectric are improved by forming an adhesion layer of Ti having a thickness of 5-500 Å between the interlayer dielectric and the metal wiring layer and the anode wiring layer and the cathode wiring layer can be formed simultaneously in the same process, and to provide an LED head and an image forming apparatus employing it. <P>SOLUTION: The semiconductor apparatus comprises a semiconductor substrate 21, an interlayer dielectric 23 formed on the semiconductor substrate and having a contact hole opening to the semiconductor substrate, a metal wiring layer 13 having one end connected with the contact hole and the other end constituting a bonding pad, and an adhesion layer 31 of Ti having a thickness of 5-500 Å provided between the interlayer dielectric and the metal wiring layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, an LED head, and an image forming apparatus using the same.

  2. Description of the Related Art Conventionally, in an image forming apparatus such as an electrophotographic printer, a facsimile machine, and a copying machine, an LED (Light Emitting Diode) as a light emitting element in an exposure process for forming an electrostatic latent image based on image data on a photoconductor. An LED head including an LED array chip on which an LED array in which a plurality of elements are arranged is formed is used as a light source. In this case, the LED head includes an optical system such as a lens, and forms an exposure image on the photoconductor by irradiating the photoconductor with light from the LED array via the optical system. (For example, see Patent Document 1 and Non-Patent Document 1). Note that LED arrays are generally manufactured by a method of diffusing impurities on a compound semiconductor substrate using a vapor phase diffusion technique, a solid phase diffusion technique, or the like.

  FIG. 2 is a plan view showing a configuration of a conventional LED array chip.

  As shown in the figure, the LED array chip 101 includes a light-emitting region 102 that also serves as a p-side electrode, an n-side electrode 103, and the light-emitting region 102 and the n-side formed on the surface of a compound semiconductor substrate made of GaAs or the like. Bonding pads 104 to 106 corresponding to the electrodes 103 are provided.

  As the compound semiconductor substrate, for example, a substrate in which an AlGaAs layer is formed on a GaAs substrate is used. A light emitting region 102 and a contact region 107 are formed by diffusing impurities in the AlGaAs layer. Furthermore, wiring layers 108 a to 108 e made of a gold alloy are formed so as to be drawn out from the light emitting region 102 and the contact region 107 onto an interlayer insulating film made of a SiN film or the like. The other ends of the wiring layers 108a to 108e constitute bonding pads 104 to 106 formed on the interlayer insulating film.

  For example, when the LED array chip 101 is used as a light source of a print head, the LED array chip 101 is bonded to a printed wiring board or the like, bonding pads 104 to 106 and electrode pads on the printed wiring board Are connected by wire bonding using a bonding wire such as gold.

  FIG. 3 is a diagram showing the configuration of another conventional LED array chip. 3A is a cross-sectional view, and FIG. 3B is a top view.

In this case, the substrate of the LED array chip 101 has a structure as shown in FIG. 3A, a GaAsP layer is formed on an n-type GaAs substrate, and a p-type impurity such as Zn is formed in the GaAsP layer. As a result of the selective diffusion, a light emitting portion 111 composed of a p-type impurity region is formed. As shown in FIG. 3B, a plurality of the light emitting portions 111 are formed so as to be arranged in an array. The Al electrode 112 of each light emitting unit 111 is an individual electrode formed for each light emitting unit 111, and an insulating layer as an interlayer insulating film so that one end thereof is electrically connected to the light emitting unit 111. 113 is formed on the p-type impurity region via 113. The other end of each Al electrode 112 is electrically connected to an individual electrode pad 114 as a bonding pad for wire bonding, which has a predetermined area to be electrically connected to an external wire and is formed in a planar shape. Has been. On the other hand, the AuGeNi electrode 115, which is a common electrode, is formed on and in contact with the lower layer of the n-type GaAs substrate so as to be electrically connected to the n-type GaAs substrate.
JP 2004-71684 A “Design of LED printers” published by Trikeps, Inc. 63

  However, in the conventional LED array chip, the adhesion between the interlayer insulating film made of SiN film or the like and the gold alloy layer as the wiring material is weak, and the bonding pad peels off from the interlayer insulating film in the wire bonding process. It will come off.

  FIG. 4 is a diagram showing an example of a defect in a conventional LED array chip. 4A is a top view and FIG. 4B is a cross-sectional view.

  As shown in the figure, when a metal wiring layer made of a gold alloy layer including a bonding pad 116 is formed on an interlayer insulating film 118 made of a SiN film or the like formed on a substrate 119, gold or the like When the bonding wire 117 is connected to the bonding pad 116 by wire bonding, the bonding pad 116 may be peeled off from the interlayer insulating film 118 when the bonding pad 116 receives a pulling force.

  The present invention solves the above-described conventional problems, and forms an adhesion layer made of Ti having a thickness of 5 to 500 [Å] between the interlayer insulating film and the metal wiring layer, thereby providing a metal wiring layer. The semiconductor device, the LED head, and the image using the semiconductor device, in which the contact characteristics between the anode wiring layer and the cathode wiring layer of the present invention and the interlayer insulating film are improved and the anode wiring layer and the cathode wiring layer can be formed simultaneously in the same process An object is to provide a forming apparatus.

  Therefore, in the semiconductor device of the present invention, a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate and having a contact hole to the semiconductor substrate, one end connected to the contact hole, and the other end Has a metal wiring layer constituting a bonding pad, and an adhesion layer made of Ti having a thickness of 5 to 500 [Å] provided between the interlayer insulating film and the metal wiring layer.

  According to the present invention, in the semiconductor device, an adhesion layer made of Ti having a thickness of 5 to 500 [Å] is formed between the interlayer insulating film and the metal wiring layer.

  As a result, the contact characteristics between the anode wiring layer and the cathode wiring layer as the metal wiring layer and the interlayer insulating film are improved, and the anode wiring layer and the cathode wiring layer can be formed simultaneously in the same process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 5 is a diagram showing the configuration of the image forming apparatus main body in the embodiment of the present invention.

  In the figure, reference numeral 50 denotes an image forming apparatus, for example, an electrophotographic printer, a facsimile machine, a copying machine, a multifunction machine having both functions of a printer, a facsimile machine, and a copying machine. It may also be one that forms a monochrome image or one that forms a color image. In the present embodiment, the case where the image forming apparatus is a so-called tandem color electrophotographic printer will be described.

  Since the image forming apparatus 50 in the present embodiment is a color electrophotographic printer, the image forming apparatus 50 includes four process units 51 to 51 that respectively form yellow, magenta, cyan, and black color images. 54 are arranged in order from the upstream side (right side in FIG. 5) of the conveyance path 71 along the conveyance path 71 of the paper 55 as a recording medium. Since the internal configurations of these process units 51 to 54 are common, the internal configuration will be described using the cyan process unit 53 as an example.

  Here, in the process unit 53, a photosensitive drum 53a as an image carrier is rotatably arranged in the direction indicated by the arrow, and the photosensitive drum 53a is exposed around the photosensitive drum sequentially from the upstream side in the rotation direction. A charging roller 53b for supplying electricity to the surface of the body drum 53a for charging; an exposure device 53c for selectively irradiating light on the surface of the charged photosensitive drum 53a to form an electrostatic latent image; A developing device 53d that conveys toner of a predetermined color (cyan) and a cleaning device 53e that removes toner remaining on the surface of the photosensitive drum 53a are disposed on the surface of the photosensitive drum 53a. The exposure device 53c includes an LED print head 40 as an LED head described later. The photosensitive drum 53a is rotated by a drive source and a gear (not shown).

  Further, the image forming apparatus 50 has a paper cassette 56 for storing the paper 55 stacked in a lower portion of the image forming apparatus 50, and a hopping for separating and transporting the paper 55 one by one above the paper cassette 56. A roller 57 is provided. Further, the sheet 55 is sandwiched with the pinch rollers 58 and 59 on the downstream side of the hopping roller 57 in the conveyance direction of the sheet 55 to correct the skew of the sheet 55 and conveyed to the process units 51 to 54. Registration rollers 60 and 61 are disposed. These hopping roller 57 and registration rollers 60 and 61 are interlocked by a driving source (not shown).

  Further, transfer rollers 62 formed of semiconductor rubber or the like are disposed at positions facing the respective photosensitive drums 51a, 52a, 53a and 54a of the process units 51 to 54, respectively. In order to adhere the toner on the photosensitive drums 51a, 52a, 53a and 54a to the paper 55, a potential difference is generated between the surfaces of the photosensitive drums 51a, 52a, 53a and 54a and the surfaces of the transfer rollers 62. Has come to occur.

  The fixing device 63 includes a heating roller and a backup roller, and fixes the toner transferred on the paper 55 by pressurizing and heating. The discharge rollers 64 and 65 pinch the paper 55 discharged from the fixing device 63 together with the pinch rollers 66 and 67 of the discharge unit and discharge the paper 55 to the recording medium stacker unit 68. The discharge rollers 64 and 65 are rotated by a driving source (not shown).

  Next, the operation of the image forming apparatus 50 will be described.

  First, the paper 55 stored in the paper cassette 56 is conveyed by the hopping roller 57 and conveyed to the image forming unit by the pinch rollers 58 and 59 and the registration rollers 60 and 61. For example, in the cyan process unit 53, the surface of the rotating photosensitive drum 53a is charged by the charging roller 53b, the charged surface is exposed by the exposure device 53c, and an electrostatic latent image is written. The electrostatic latent image is developed with toner by the developing device 53d to form a toner image.

  Here, the toner image on the surface of the photoconductive drum 53 a is transferred onto the paper 55 when the paper 55 conveyed in time passes between the photoconductive drum 53 a and the transfer roller 62. In this way, each time the paper 55 passes through the process units 51 to 54 for each color, the transfer is performed for each color, and a color toner image is formed on the paper 55.

  The toner image on the paper 55 is fixed on the paper 55 by the fixing device 63, and the paper 55 is conveyed by the discharge rollers 64 and 65 and the pinch rollers 66 and 67 and discharged to the recording medium stacker unit 68.

  Next, the configuration of the LED print head 40 provided in the exposure device 53c will be described.

  FIG. 6 is a diagram showing a main configuration of the LED print head according to the embodiment of the present invention.

  As shown in FIG. 6, in the LED print head 40, a printed circuit board 42 is placed on and fixed to the base member 41. An LED array chip 42a as a semiconductor device is mounted on the printed circuit board 42 together with a driver IC 42b by die bonding and wire bonding. A rod lens array 43 as an optical system for condensing the light emitted from the light emitting unit 11 is disposed above the light emitting unit 11 described later of the LED array chip 42a. The rod lens array 43 has a large number of columnar optical lenses arranged along the linearly arranged light emitting portions of the LED array chip 42a. The rod lens array 43 has a predetermined position by a lens holder 44 as a holder corresponding to the optical system holder. Is held in.

  As shown in FIG. 6, the lens holder 44 is formed so as to cover the base member 41 and the printed circuit board 42. The base member 41, the printed circuit board 42, and the lens holder 44 are integrally held by an opening 41 a formed in the base member 41 and the lens holder 44 and a clamper 45 disposed through the opening 44 a. .

  Therefore, the light generated by the LED array chip 42a is irradiated to the surfaces of the photosensitive drums 51a, 52a, 53a and 54a charged through the rod lens array 43.

  Next, the configuration of the LED array chip 42a will be described.

  1 is a plan view showing a configuration of an LED array chip in an embodiment of the present invention, FIG. 7 is a cross-sectional view of the LED array chip in an embodiment of the present invention, and FIG. 8 is an LED array chip in an embodiment of the present invention. FIG. 9 is a diagram showing the relationship between the film thickness of the adhesion layer and the contact resistance in the embodiment of the present invention, and FIG. 10 is the film thickness of the adhesion layer, the contact resistance and the resistance in the embodiment of the present invention. It is a table | surface which shows the relationship of adhesive force. 7A is a cross-sectional view taken along the line A-A 'in FIG. 1, and FIG. 7B is a cross-sectional view taken along the line B-B' in FIG.

  As shown in FIGS. 1 and 8, the LED array chip 42 a in the present embodiment includes a light emitting unit 11 as an anode electrode arranged in a row on the first conductive semiconductor layer 22, and the light emitting unit 11. And LED as a light emitting element which is a semiconductor element composed of a first conductive type semiconductor contact electrode 12 as a cathode electrode formed adjacent to the cathode electrode.

  An anode electrode layer 13 as an anode wiring layer that is a metal wiring layer is connected to the light emitting portion 11, and an anode bonding pad 14 as a bonding pad that is a part of the anode wiring layer is formed at the opposite end. Has been. The anode bonding pad 14 is connected so that two light emitting portions 11 of the odd numbered light emitting portions 11 and the even numbered light emitting portions 11 are paired. As a result, the number of anode bonding pads 14 is half the number of light emitting portions 11.

  Also, every other first conductive semiconductor contact electrode 12 is connected to a cathode electrode layer 15 as a cathode wiring layer which is a metal wiring layer, and at the opposite end is a bonding pad which is a part of the cathode wiring layer. The cathode bonding pad 16 is formed. The wiring layer is not directly connected to the rest of the first conductive type semiconductor contact electrode 12, but the common contact electrode 17 as a cathode wiring layer formed via the first conductive type semiconductor layer 22 itself is provided. The cathode bonding pad 16 is connected to the common contact electrode 17.

  Adjacent LED elements are electrically separated by a zigzag separating portion 19. The isolation portion 19 is formed by an isolation groove or impurity diffusion layer that reaches the high resistance substrate 21.

  Here, the semiconductor substrate on which the LED array chip 42a is formed is a first conductive semiconductor electrically separated from the high resistance substrate 21 on the high resistance substrate 21 as a base substrate as shown in FIG. This is a substrate having a structure in which the layer 22 is epitaxially grown. An interlayer insulating film 23 is formed on the first conductive semiconductor layer 22. The light emitting unit 11 is formed by diffusing an impurity such as Zn of the second conductivity type, and forms a PN junction. An anode electrode layer 13 is connected to the light emitting part 11 through a contact hole provided in the interlayer insulating film 23.

More specifically, the interlayer insulating film 23 is composed of a SiN (Si ₃ N ₄ ) layer and is formed on the first conductive semiconductor layer 22. The interlayer insulating film 23 is provided with an opening on the light emitting unit 11 and the contact region. On the interlayer insulating film 23, an anode electrode layer 13 and a cathode electrode layer 15 as metal wiring layers connected to the light emitting portion 11 and the first conductive semiconductor contact electrode 12 are formed.

  As shown in FIG. 8, the anode electrode layer 13 and the cathode electrode layer 15 as metal wiring layers are both metal wirings made of a gold alloy containing Ge formed on the adhesion layer 31 made of Ti. The first wiring layer 32 as a layer and the second wiring layer 33 as a metal wiring layer made of gold or a gold alloy. Here, the adhesion layer 31 is preferably a layer having good adhesion to the interlayer insulating film 23, particularly the SiN layer. Then, the adhesion layer 31 made of Ti is preferably thicker for improving the adhesion to the SiN layer and thinner for improving the cathode contact resistance. That is, as shown in FIG. 9, when the thickness of the adhesion layer 31 exceeds 500 [Å] (50 [nm]), the cathode contact resistance increases and the power consumption of the device increases. . Further, as shown in the table of FIG. 10, since the adhesion strength is reduced when the thickness is less than 5 [Å], the thickness of the adhesion layer 31 is 5 [Å] (0.5 [nm]) to 500 [Å]. ] (50 [nm]).

  The first wiring layer 32 is preferably made of a gold alloy containing Ge, such as AuGeNi or AuGe. If the adhesion layer 31 is a thin layer within the above-described thickness range, Ge is allowed to pass through the adhesion layer 31 during the contact annealing step by including Ge in the first wiring layer 32. Thus, it is presumed that it is diffused on a substrate containing GaAs as a main component and has a function of reducing contact resistance. Further, when Ni is further contained in the first wiring layer 32, Au reacts with excess As generated when Au and Ga that have passed through the adhesion layer 31 react at the same time, thereby stabilizing the substrate. 32 is preferably made of an AuGeNi alloy.

  The second wiring layer 33 is preferably a metal layer containing as little impurities as possible because the resistance value is low and the surface is resistant to deterioration such as oxidation. In particular, it is not necessary to provide the second wiring layer 33 different from the first wiring layer 32, and a single layer of AuGeNi may be used.

  The anode electrode layer 13 and the cathode electrode layer 15 as such a metal wiring layer are formed on a resist layer on which a wiring pattern is formed by vapor deposition, sputtering, electroless plating, electrolytic plating, or the like by a Ti layer, an AuGeNi alloy layer, an Au It is preferable to sequentially form the layers and remove the resist layer by so-called lift-off because a photolithography process can be performed once even though a plurality of metal layers are stacked. Note that this embodiment can also be applied to other semiconductor devices using a SiN film.

  Next, a method for manufacturing the LED array chip 42a will be described.

  FIG. 11 is a first diagram showing the manufacturing process of the LED array chip in the embodiment of the present invention, FIG. 12 is a second diagram showing the manufacturing process of the LED array chip in the embodiment of the present invention, and FIG. The 3rd figure which shows the manufacturing process of the LED array chip in embodiment of invention, FIG. 14 is the 4th figure which shows the manufacturing process of LED array chip in embodiment of this invention. 11A to 12G, (2) is a top view, and (1) is a cross-sectional view taken along the line C-C 'in (2).

  First, as the semiconductor substrate of the LED array chip 42a, a substrate having a structure in which the first conductive semiconductor layer 22 electrically isolated from the base substrate 21 is epitaxially grown on the base substrate 21 is used. For example, the base substrate 21 is a semi-insulating GaAs substrate, and a substrate obtained by epitaxially growing an n-type semiconductor layer thereon as the first conductive semiconductor layer 22 is used. A structure in which a buffer layer is sandwiched between the base substrate 21 and the first conductive semiconductor layer 22 may be adopted. Furthermore, the base substrate 21 may be an n-type GaAs substrate, and a substrate obtained by epitaxially growing an n-type semiconductor layer as the first conductive semiconductor layer 22 via a buffer layer and an insulating layer may be used (FIG. 11A). ).

  Then, in the first conductive semiconductor layer 22 of the semiconductor substrate, the second conductive impurity is diffused in an array region that becomes the light emitting unit 11 as an optical element. For example, Zn (zinc) is formed from the diffusion source layer 72 by a method such as selective diffusion from the openings 71 opened in an array to be the light emitting portions 11 on a diffusion mask also used as the interlayer insulating film 23 formed on the semiconductor substrate. A second conductivity type semiconductor impurity such as is diffused (FIGS. 11B to 12G). In this case, a diffusion source layer 72 and an annealing cap layer 73 containing a second conductivity type semiconductor impurity are formed and diffusion annealing is performed. As a result, a diffusion region of the second conductivity type impurity is formed as an array region to be the light emitting section 11 (FIG. 13H).

  Next, a region corresponding to the zigzag separating portion 19 for separating the first conductive semiconductor layer 22 into two is formed. The separation portion 19 is formed by etching the first conductive semiconductor layer 22 to a depth that reaches at least the base substrate 21 or the insulating layer below the first conductive semiconductor layer 22. Etching is performed, for example, by wet etching using a perhydrophosphoric acid-based etchant. Therefore, the first conductive semiconductor layer 22 is electrically insulated in a zigzag shape (FIG. 13 (i)). Next, after forming the interlayer insulating film 23, openings corresponding to the light emitting portion 11, the first conduction type semiconductor contact electrode 12, the common contact electrode 17 and the like are formed in the interlayer insulating film 23 (FIG. 14 (j)). ).

  Finally, a second conductivity type semiconductor contact electrode is formed for good connection to the first conductivity type semiconductor contact electrode 12 and the second conductivity type semiconductor portion to be the light emitting portion 11. In this case, the first conduction type semiconductor contact electrode 12 and the second conduction type contact electrode are formed through the opening 71 of the interlayer insulating film 23 that also serves as a diffusion mask, and contacts are respectively taken. The metal wiring layers such as the first conductive semiconductor contact electrode 12, the second conductive semiconductor contact electrode, the individual wiring, the anode bonding pad 14, and the cathode bonding pad 16 are made of the same material and are formed simultaneously. The metal wiring layer includes an adhesion layer 31, a first wiring layer 32, and a second wiring layer 33. In this case, AuGeNi / Au or AuGe / Ni / Au is used as the material of the first wiring layer 32 and the second wiring layer 33, that is, the electrode material. Further, sintering is performed in order to connect the first conductive semiconductor layer 22 and the second conductive semiconductor layer to the electrode material satisfactorily (FIG. 14 (k)).

  Next, the operation of the LED array chip 42a configured as described above will be described.

  In the LED array chip 42a in the present embodiment, as shown in FIG. 1, the cathodes of the odd-numbered light emitting portions 11 are all connected to the cathode bonding pad 16 as the same cathode wiring layer, and the even-numbered light emitting portions. All the 11 cathodes are connected to the cathode bonding pad 16 as the same cathode wiring layer. Further, the individual wirings of the adjacent odd-numbered light emitting units 11 and the individual wirings of the even-numbered light emitting units 11 are connected to the anode bonding pad 14 as the same anode wiring layer.

  Therefore, the anode bonding pad 14 and the cathode bonding pad 16 are electrically selected, and desired light emission is caused by flowing a forward current from the second conduction type (P) side to the second conduction type (N) side. The part 11 can be turned on.

  For example, when the leftmost light emitting unit 11 is lit, the leftmost anode bonding pad 14 is selected, the cathode bonding pad 16 to which the cathode of the odd numbered light emitting unit 11 is connected is selected, and the selected anode bonding pad is selected. A forward current may be passed between 14 and the cathode bonding pad 16. When the even-numbered, that is, 2n-th light emitting section 11 is lit from the left end, the n-th anode bonding pad 14 is selected from the left end, and the cathode bonding pad 16 to which the cathode of the even-numbered light emitting section 11 is connected. And a forward current may be passed between the selected anode bonding pad 14 and cathode bonding pad 16.

  As described above, in the present embodiment, Ti having a thickness of 5 to 500 [Å] is provided between the interlayer insulating film 23 and the metal wiring layer formed of the first wiring layer 32 and the second wiring layer 33. An adhesion layer 31 made of is formed. Therefore, the contact characteristics between the anode wiring layer and the cathode wiring layer as the metal wiring layer and the interlayer insulating film 23 are improved. As a result, since the anode wiring layer and the cathode wiring layer can be formed simultaneously in the same process, it is possible to prevent the occurrence of defects such as inter-wiring insulation defects due to particles or pattern defects on the surface of the semiconductor substrate. In addition, the cost can be reduced.

  In addition, this invention is not limited to the said embodiment, It can change variously based on the meaning of this invention, and does not exclude them from the scope of the present invention.

It is a top view which shows the structure of the LED array chip in embodiment of this invention. It is a top view which shows the structure of the conventional LED array chip. It is a figure which shows the structure of the other conventional LED array chip. It is a figure which shows the example of the defect in the conventional LED array chip. 1 is a diagram illustrating a configuration of an image forming apparatus main body in an embodiment of the present invention. It is a figure which shows the principal part structure of the LED print head in embodiment of this invention. It is sectional drawing of the ED array chip | tip in embodiment of this invention. It is a principal part expanded sectional view of the LED array chip in embodiment of this invention. It is a figure which shows the relationship between the film thickness of the contact | adherence layer in embodiment of this invention, and contact resistance. It is a table | surface which shows the relationship between the film thickness of the contact | adherence layer in embodiment of this invention, contact resistance, and adhesive force. It is a 1st figure which shows the manufacturing process of the LED array chip in embodiment of this invention. It is a 2nd figure which shows the manufacturing process of the LED array chip in embodiment of this invention. It is a 3rd figure which shows the manufacturing process of the LED array chip in embodiment of this invention. It is a 4th figure which shows the manufacturing process of the LED array chip in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Light emission part 12 1st conductivity type semiconductor contact electrode 13 Anode electrode layer 14 Anode bonding pad 15 Cathode electrode layer 16 Cathode bonding pad 17 Common contact electrode 23 Interlayer insulation film 31 Adhesion layer 32 1st wiring layer 33 2nd wiring layer 40 LED Print head 42 Print substrate 42a LED array chip 43 Rod lens array 44 Lens holder 50 Image forming apparatuses 51a, 52a, 53a, 54a Photosensitive drum

Claims (8)

(A) a semiconductor substrate;
(B) an interlayer insulating film formed on the semiconductor substrate and having contact holes opened to the semiconductor substrate;
(C) one end of which is connected to the contact hole and the other end of which forms a bonding pad;
(D) A semiconductor device comprising an adhesion layer provided between the interlayer insulating film and the metal wiring layer and made of Ti having a thickness of 5 to 500 [Å]. The semiconductor device according to claim 1, wherein the interlayer insulating film is made of SiN. The semiconductor device according to claim 1, wherein the metal wiring layer is made of a gold alloy containing Ge. The semiconductor device according to claim 3, wherein the gold alloy is AuGeNi. The semiconductor device according to claim 1, wherein the semiconductor substrate is a compound semiconductor substrate containing Ga as a main component, and an LED is formed as the semiconductor element. The cathode electrode and anode electrode formed on the main surface, and further comprising a cathode wiring layer and an anode wiring layer formed of the same metal by the same process and connected to the cathode electrode and the anode electrode. Semiconductor device. The semiconductor device according to claim 5 or 6 forms an LED array chip in which LEDs are arranged in a row, and the LED array chip is mounted on a printed board by die bonding and wire bonding, and is fixed by a holder. An LED head, wherein a system is arranged to face the LED array chip. 8. An image forming apparatus, wherein the LED head according to claim 7 is disposed to face an image carrier.

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