JP2006252768A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce penalty in an erroneous page by inputting and outputting required data with accuracy in a clock synchronization type semiconductor storage device having multiple banks. <P>SOLUTION: The device is equipped with: a read means, responding to a read operation directive signal, for choosing a row responding to a first address signal, choosing a column responding to a second address signal, and reading the data of the chosen cell outside the device; and a data validity signal output means for outputting the data validity signal (/DV) indicating the validity of the data read from the read means outside the device responding to the read directive signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to a clock synchronous semiconductor memory device that inputs and outputs data in synchronization with a clock signal, and more particularly to a multi-bank semiconductor memory device having a plurality of banks therein.

  In recent years, a microprocessor (MPU) has become multifunctional, and a large amount of data can be processed at high speed. In response to this, the dynamic random access memory (hereinafter referred to as DRAM) used as the main memory has increased in storage capacity with the progress of its fine technology. However, the operation speed of the DRAM cannot follow the operation speed of the MPU, and the problem that the access time and cycle time of the DRAM become a bottleneck and degrade the performance of the entire processing system has become prominent. In order to prevent the performance of the processing system from degrading, a high-speed memory called a cache memory, which is usually composed of a static random access memory (SRAM), is arranged between the DRAM and the MPU. Data / instructions frequently used by the MPU are stored in the cache memory, and data / instructions are transferred between the MPU and the cache memory. The DRAM is accessed only when there is no instruction / data requested to be accessed by the MPU in the cache memory. Since instructions / data required by the MPU are stored in the cache memory in advance with a high probability, the DRAM access frequency is greatly reduced, and a reduction in the operating speed of the processing system can be prevented.

  However, since the SRAM used for the cache memory is more expensive than the DRAM, the configuration in which the cache memory is arranged is not suitable for a relatively inexpensive device such as a personal computer. For this reason, it is required to improve the performance of the processing system using an inexpensive DRAM. One answer to this is a synchronous DRAM (synchronous DRAM: hereinafter referred to as SDRAM) in which a DRAM is operated in synchronization with a clock signal which is a system clock, for example, and data is transferred in synchronization with the clock signal. What has been devised.

  In this SDRAM, an operation mode instruction signal is given in the form of a command (a combination of a plurality of control signal states) in synchronization with a clock signal. In the SDRAM, according to this command, a plurality of bits (for example, 8 bits; per 1 IO) are simultaneously selected, and the plurality of bits simultaneously selected are sequentially output in synchronization with the clock signal. Also at the time of data writing, the write data applied in synchronization with the clock signal is sequentially taken and simultaneously written into the selected memory cell in a predetermined sequence.

  In this SDRAM, external control signals constituting a command in synchronization with the rising edge of a clock signal, that is, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE, and address signals and write signals are written. Capture internal data and execute internal operations. Data input / output timing margin that takes into account skew (timing deviation) of control signals and address signals, etc. by taking external data in synchronization with the clock signal and outputting data in synchronization with the clock signal Therefore, the internal operation start timing can be accelerated, the cycle time can be shortened, and high-speed access is possible.

  Also, in a processing system such as an image processing system, data bits at successive data addresses are accessed sequentially, and the processing system frequently accesses multiple bits at successive memory locations due to the locality of the processing. There is. Therefore, by performing data input / output in synchronization with the clock signal, the continuous access time can be made the same as that of the clock signal, and the average access time can be made comparable to that of the SRAM.

  In SDRAM, the concept of a plurality of banks is further introduced. That is, in the SDRAM, a plurality of banks are provided inside. The activation and deactivation (precharge) of these banks can be performed almost independently of each other.

  In a standard DRAM, a precharge operation must be performed whenever a new row is selected. In DRAM, internal signal lines are dynamically driven, and each signal line needs to be held at a predetermined potential level during precharging. This precharge usually requires a time called RAS precharge time tRP (because each internal signal line needs to be returned to a predetermined potential level). In the standard DRAM, it is called RAS-CAS delay time tRCD and requires time. That is, it is necessary to perform a column selection operation in accordance with column address strobe signal / CAS after row address strobe signal / RAS is applied and the row of memory cells is surely selected. The column address strobe signal / CAS needs to be returned to the inactive state when the column selection operation is completed. Therefore, when a new page (memory cell row) is selected, RAS precharge time tRP and RAS-CAS delay time tRCD are required. For this reason, the cycle time of the standard DRAM is almost twice the access time. It becomes. However, when a plurality of banks are provided as in the SDRAM, one bank is activated and another bank is precharged (inactive) while accessing the activated bank. ), This other precharged bank can be accessed without waiting for the RAS precharge time tRP, so that this bank can be alternately or sequentially activated / precharged (deactivated). ), The RAS precharge time tRP can be apparently eliminated, and high-speed access is possible. If the other bank is precharged and activated when one bank is accessed, data can be written / read alternately to these banks, and the RAS precharge time tRP and RAS can be read. -Loss time due to CAS delay time tRCD can be eliminated, and data can be written / read at high speed.

  In the above-described conventional SDRAM, a bank is configured with a memory array (memory mat) as a unit. This memory array (memory mat) has a plurality of memory blocks, and in one memory array, each memory block is driven to a selected state or an inactive state when the corresponding memory array is activated. It cannot be activated / deactivated independently. Therefore, in the case of a conventional SRAM, the number of banks is limited to the number of memory arrays (memory mats), and the number of banks is small (usually four banks are the maximum). This is because a standard DRAM array structure is used as an array structure in the SDRAM. In the standard DRAM, the row / column decoder is divided and arranged corresponding to each memory array (memory mat). This is because these row / column decoders can be driven independently for each memory array (memory mat).

  Consider the use of a conventional SDRAM having a plurality of banks as the main memory of a processing system. All the banks of the SDRAM are activated simultaneously, and the row (page) of memory cells is held in the selected state in each bank. That is, a sense amplifier provided corresponding to each column of memory cells is used as a pseudo cache. When the data / instruction requested by the MPU is not stored in the cache memory (at the time of a cache miss), it is determined whether or not the data / instruction requested by the MPU exists on the selected page of the SDRAM (page hit / miss judgment) ). When a page hit occurs, the corresponding page is accessed to transfer the data / instruction block (cache block) to the cache memory, and the access requested data / instruction is transferred to the MPU (during read access). Therefore, at the time of a page hit, it is only required to select and read a block of data / instruction from the page, and data required after the CAS access time ta (CAS) (or CAS latency) has elapsed. / Instructions can be transferred to the cache memory and MPU (during read access).

  On the other hand, in the case of a page miss, the bank storing the requested data / instruction is once driven to the precharged state (inactive state), and then the page storing the required data / instruction is selected and subsequently accessed. The block containing the requested data / instruction is transferred to the cache memory. Therefore, when a page miss occurs, in the SDRAM, bank precharge, bank activation, and column selection operation from the selected page are required, and RAS precharge time tRP, RAS-CAS delay time tRCD. The required data / instruction is transferred from the SDRAM to the cache memory after the sum of the CAS access time ta (CAS) (or CAS latency) has elapsed. During this period, the MPU is in a wait state.

  Therefore, when used as the main memory of a conventional multi-bank SDRAM, since the number of banks is small, the number of selected pages is small (same as the number of banks), the page hit rate is small, and page misses are small. There was a problem that the penalty of time (wait time of MPU) became large.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a novel structure having a plurality of banks capable of increasing the page hit rate.

  Another object of the present invention is to provide a semiconductor memory device having a plurality of banks capable of accurately inputting / outputting (writing / reading) necessary data.

  Still another object of the present invention is to provide a semiconductor memory device having a plurality of banks using an array structure similar to that of a standard DRAM.

  A semiconductor memory device according to the present invention includes a memory array having a plurality of memory cells arranged in a matrix, and activated in response to an array activation instruction signal, and selects a row of the memory array according to a first address signal The row selection means for performing the operation and the read operation instruction signal are activated, and a column of the memory array is selected according to the second address signal applied simultaneously with the read operation instruction signal, and the memory cell on the selected column is selected. Read means for reading data to the outside of the apparatus, and data valid signal output for outputting to the outside of the apparatus a data valid signal indicating that the data read from the read means is valid in response to the read operation instruction signal Means.

    The signal indicating that valid data is output is preferably set to a level different from that in the standby state.

  Instead of this, preferably, a signal indicating that valid data is output in a cycle prior to a clock cycle in which valid data is output is activated.

  Alternatively, the valid data output instruction signal is preferably activated while valid data is being output.

  In place of this, preferably, a signal indicating that valid data is output is output in a one-shot pulse form.

  Preferably, the parity bit is used, and in the standby state (when valid data is not output), all the data output nodes are set in a state where a parity error exists.

  By outputting a signal indicating that the valid data is output to the outside when the valid data is output, the external device can know the timing at which the valid data is output accurately. Therefore, when valid data is output, a signal indicating that valid data is output is output to an external device, so that the external device can reliably capture valid data.

  If a signal set to a level different from that in the standby state is output as a signal indicating that this valid data is output, the valid data output is reliably exhibited even in a high-speed processing system having a binary level input / output interface. be able to.

  In addition, if a signal indicating that valid data is output in a cycle prior to the clock cycle in which valid data is output is activated, an external device can capture the valid data with a margin. .

  Further, if the valid data output instruction signal is activated while valid data is being output, the external device can reliably fetch the valid data.

  If a signal indicating that valid data is output is output in the form of a one-shot pulse, the external device can reliably output valid data by generating this one-shot pulse in synchronization with the clock signal. Can be recognized.

  In the standby state (when valid data is not output) using the parity bit, if the data output nodes are all set to a state where a parity error exists, an extra output pin terminal (output node) and It is possible to make an external device recognize that valid data has been output without using a circuit.

  FIG. 1 schematically shows a whole structure of a semiconductor memory device according to the present invention. In FIG. 1, a semiconductor memory device includes memory blocks MB # 0-MB # N each having a plurality of memory cells arranged in a matrix of rows and columns, and sense amplifiers arranged between these memory blocks. Bands SA # 1 to SA # N, sense amplifier band SA # 0 provided outside memory block MB # 0, and sense amplifier band SA # N + 1 provided adjacent to the outside of memory block MB # N are included. The structure of the sense amplifier band will be described in detail later. These sense amplifier bands SA # 1 to SA # N are shared by adjacent memory blocks. The selected memory block is connected to the corresponding sense amplifier band, and the non-selected memory block paired with the selected memory block is disconnected from the corresponding sense amplifier band.

  Corresponding to memory blocks MB # 0-MB # N, array drive circuits DR # 0-DR # N for activating / deactivating each memory block are provided, and sense amplifier bands SA # 0-SA # Corresponding to each of # N + 1, sense / connection control circuits SID # 0-SID # N + 1 for controlling activation / inactivation of sense amplifiers included in the sense amplifier band are provided. Each of array drive circuits DR # 0-DR # N includes a row decoder and a word line driver for generating a control signal related to the row selection operation of the corresponding memory block and performing the row selection operation when activated. These array drive circuits DR # 0 to DR # N are activated / deactivated independently of each other, and each is provided with a signal latch circuit such as a row address latch circuit, although not clearly shown.

  Each of sense / connection control circuits SID # 0-SID # N + 1 activates a sense amplifier included in a corresponding sense amplifier band in response to a sense activation signal applied from a corresponding array drive circuit. As will be described, the connection / separation control between the memory block and the sense amplifier band, the local IO bus (data input / output bus provided in each memory block), and the global IO bus (data provided in common to all memory blocks) A connection control circuit for controlling connection with the input / output bus).

  The semiconductor memory device further includes a command latch 2 that latches a command CM applied from the outside of the device in synchronization with the clock signal P, and a bank address latch that latches a bank address signal applied from the outside in synchronization with the clock signal P. 4, an address latch 6 that latches an externally applied address signal in synchronization with the clock signal P, a command decoder 8 that decodes a command latched by the command latch 2, and an activation signal from the command decoder 8 And a bank decoder 10 which decodes the bank address BA latched by the bank address latch 4 and generates a bank designation signal for designating the addressed memory block.

  The command CM may be an individual control signal such as a normal row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable / WE, for example, and an operation mode in combination of a plurality of control signal states. May be specified. The command decoder 8 decodes this command to identify the designated operation mode, and generates a control signal required according to the identified operation mode. An output signal of command decoder 8 is transmitted to array drive circuits DR # 0 to DR # N via internal control bus 13, and a bank designation signal from bank decoder 10 is sent to array drive circuit DR # via bank designation bus 14. 0-DR # N and sense / connection control circuits SID # 0-SID # N + 1. The internal address signal latched by address latch 6 is transmitted to array drive circuits DR # 0-DR # N via internal address bus 15.

  Command decoder 8 is provided corresponding to each of array drive circuits DR # 0-DR # N, and has a configuration in which each command decoder is selectively activated in accordance with a bank selection signal output from bank decoder 10. May be.

  In the configuration shown in FIG. 1, memory blocks MB # 0-MB # N included in memory array 1 are driven to an active / inactive state independently of each other in accordance with array drive circuits DR # 0-DR # N. Therefore, memory blocks MB # 0-MB # N can each be used as a bank. That is, when one memory block MB # i is in an active state, another memory block MB # j can be driven to an active state, and can be driven to an inactive state (precharge state). Therefore, in each of memory blocks MB # 0 to MB # N, by setting a row (word line) of memory cells in a selected state, more pages can be selected as compared with a conventional SDRAM configuration. The page hit rate can be improved.

  FIG. 2 schematically shows a configuration of the array drive circuit shown in FIG. FIG. 2 shows a configuration of array drive circuit DR # i provided in memory block MB # i (i = 0 to N). Referring to FIG. 2, array drive circuit DR # i receives a row activation control signal ACT, an array deactivation instruction signal PRG and a bank designation signal Bai supplied from a command decoder and generates various internal control signals. 20 and a row latch 22 that takes in and latches an internal address signal AD applied from the address latch 6 shown in FIG. 1 in response to an address latch instruction signal RALi from the row control circuit 20, and generates an internal row address signal. A row decoder 24 which is activated in response to a row decoder enable signal RDEi from the row control circuit 20 and generates a signal for designating a row of a memory block by decoding an internal row address signal applied from the row latch 22; The output signal of the row decoder 24 and the row-related control circuit 20 It includes word driver 26 for driving the word line WL to a selected state corresponding to the row that is addressed in response to the lead wires driving signal RXTi.

  Memory block MB # i is arranged corresponding to each row of memory cells, and is arranged corresponding to each word line WL to which memory cell MC of each corresponding row is connected, and each column of memory cells, Indicates a bit line pair BL, / BL to which the memory cells MC of the corresponding column are connected. In FIG. 2, one word line WL and a pair of bit lines BL, / BL are included. Bit lines BL and / BL are bit lines that precharge and equalize bit lines BL and / BL to a predetermined potential (intermediate potential) in response to a bit line equalize instruction signal BLEQ supplied from row-related control circuit 22. A precharge / equalize circuit BPE is provided. Next, the operation of the array drive circuit shown in FIG. 2 will be described with reference to the timing chart shown in FIG.

  At time t0, an array activation instruction command (hereinafter referred to as an active command) ACT is applied in synchronization with clock signal P. The determined state of this command may be either the rising edge or the falling edge of the clock signal P. Simultaneously with this active command ACT, a bank address BA and an address AD are given. This active command ACT is decoded by command decoder 8, and internal array operation activation instruction signal φACT is activated. On the other hand, the bank decoder is activated under the control of the command decoder 8, decodes the applied bank address, and drives the bank designation signal Bai to the selected state.

  Row-related control circuit 20 first activates row address latch instruction signal RALi in accordance with internal array activation instruction signal φACT and selected (active) bank designation signal Bai. As a result, the row latch 22 once enters the through state and then enters the latch state, and holds the internal address signal in the determined state. Next, the row decoder 24 is activated in response to the row decode enable signal RDEi from the row control circuit 20, and decodes the applied internal row address signal. On the other hand, row-related control circuit 20 inactivates bit line equalize instruction signal BLEQi, which has been in the active state, in accordance with internal array activation instruction signal φACT and bank designation signal Bai in the selected state. Charge / equalize circuit BPE is deactivated. As a result, the bit lines BL and / BL are brought into a floating state at the intermediate precharge potential.

  Next, the word line drive signal RXTi from the row control circuit 20 is activated at a predetermined timing, and the word driver 26 follows the word line selection signal (row designation signal) output from the row decoder 24 and the word line drive signal RXTi. The selected word line WL is driven to the selected state. As a result, the storage data of the memory cell MC is transmitted to the bit line BL (or / BL), and a potential difference corresponding to the storage information of the memory cell MC is generated in the bit lines BL and / BL. Next, a sense amplifier described later is activated, and a minute potential difference between the bit lines BL and / BL is amplified.

  In this state, a column selection operation is then performed, and data writing / reading is performed.

  At time t1, an array deactivation instruction command (hereinafter referred to as a precharge command) PRG is given together with bank address BA. Command decoder 8 decodes the precharge command again, and activates internal array deactivation instruction signal φPRG. The bank decoder 10 is activated under the control of the command decoder, and the bank address designation signal Bai is activated. Next, row-related control circuit 20 deactivates word line drive signal RXTi (the sense amplifier is deactivated before that), and then deactivates row decoder enable signal RDEi and row address latch instruction signal RALi. Activated. The row latch 22 maintains the latched state. Row-related control circuit 20 activates bit line equalize instruction signal BLEQi, and bit lines BL and / BL are precharged and equalized to an intermediate potential by bit line precharge / equalize circuit BPE.

  By selectively activating array drive circuits DR # 0-DR # N according to bank designation signal Bai, each memory block can be driven independently of each other.

  FIG. 4 schematically shows a configuration of the sense amplifier band shown in FIG. FIG. 4 representatively shows sense amplifier bands SA # n and SA # n + 1 related to memory block MB # n. Memory block MB # n includes a plurality of word lines WLn0 to WLnM and a plurality of bit lines BLn1, / Bln1, BLn2, / BLn2, BLn3, / Bln3 and BLn4, / BLn4. This bit line pair is alternately connected to sense amplifier circuits included in sense amplifier bands SA # n and SA # n + 1 on both sides. That is, bit line pair BLn1, / BLn1 is connected to sense amplifier SAb1 of sense amplifier band SA # n + 1 via bit line isolation gate BTGn1, and bit lines BLn2, / BLn2 are sensed via bit line isolation gate BTGn2. Connected to sense amplifier circuit SAa1 in amplifier band SA # n. Bit lines BLn3, / BLn3 are connected to sense amplifier circuit SAb2 of sense amplifier band SA # n + 1 via bit line isolation gate BTGn3. Bit lines BLn4, / Bln4 are connected to sense amplifier circuit SAi2 of sense amplifier band SA # n via bit line isolation gate BTGn4. The conduction of the even-numbered bit line isolation gates BTGn2, BDTn4,... Is controlled by the bit line isolation control signal BLI2n. The conduction / non-conduction of the odd-numbered bit line isolation gates BTGn1, BTGn3,... Is controlled by the bit line isolation control signal BLI2n + 1.

  Odd-numbered bit lines BLa1, / BLa1, / BLa3, / BLa3 of memory block MB # n-1 are connected to sense amplifier circuits SAa1 and SAa2 via bit line isolation gates BTGa1, BTGa3, respectively. The bit line isolation gates BTGa1 and BTGa3 are controlled to be conductive / non-conductive by a bit line isolation control signal BLI2n-1. Even-numbered bit lines BLb2, / BLb2, BLb4, / BLb4 of memory block MB # n + 1 are connected to sense amplifier circuits SAb1, SAb2 via bit line isolation gates BTGb2, BTGb4. Bit line isolation gates BTGb2, BTGb4,... Are controlled to be conductive / non-conductive by a bit line isolation control signal BLI2n + 2.

  By sharing this sense amplifier band between two adjacent memory blocks, the area occupied by the sense amplifier band can be reduced compared to a configuration in which a sense amplifier is provided for each memory block. Also, by alternately connecting the bit line pairs of memory block MB # n to the sense amplifier bands on both sides, the pitch of the sense amplifier circuits in the sense amplifier band is made twice the pitch of the bit line pairs. It can be easily arranged.

  FIG. 5 shows a specific configuration of the sense amplifier circuit shown in FIG. FIG. 5 shows a configuration of a sense amplifier circuit included in one sense amplifier band. In FIG. 5, bit line pairs connected to sense amplifier circuits included in the same sense amplifier band are indicated by bit lines BL0, / BL0 and BL1, / BL1.

  In FIG. 5, the sense amplifier circuit is activated in response to a bit line equalize instruction signal BLEQn, precharges a corresponding bit line pair (BL0, / BL0 or BL1, / BL1) to a predetermined intermediate potential VBL, and Precharge / equalize circuit PE to be equalized and activated in response to sense amplifier activation signals SONn and / SOPn, the potentials of corresponding bit line pairs (BL0, / BL0 or BL1, / BL1) are differentially set. The sense amplifier SA (SA0 or SA1) to be amplified is turned on in response to the column selection signal CSL (CSL0 or CSL1) given from the column decoder, and the corresponding bit line pair (BL0, / BL0 or BL1, / BL1) is connected. Column select gate IOG (IOG0 or IOG) connected to local IO lines LIOn, / LIOn ) Including the. A signal line for transmitting column selection signal CSL (CSL0 or CSL1) is arranged to extend over all the memory blocks.

  FIG. 5 shows a configuration in which only one bit line pair is selected and connected to a local IO line (local IO bus) in accordance with a column selection signal from a column decoder. However, a configuration in which a plurality of bits (a plurality of pairs of bit lines) are simultaneously selected and connected to a plurality of pairs of local IO lines may be used.

  Bit line precharge / equalize circuit PE is turned on in response to bit line equalize instruction signal BLEQn, and transmits nbit MOS transistors Tr1 and Tr2 having a predetermined intermediate potential precharge potential VBL to the corresponding bit line. It includes an n-channel MOS transistor Tr3 that conducts in response to line equalize instruction signal BLEQn and electrically short-circuits the corresponding bit line.

  Sense amplifier SA (SA0 or SA1) is cross-coupled to p-channel MOS transistors PT2 and PT3 that are cross-coupled to drive the high-potential bit line potential of the corresponding bit line pair to the power supply potential level. N channel MOS transistors NT2 and NT3 for driving the low potential bit line of the bit line pair to the ground potential level, and p channel MOS transistors which are made conductive in response to sense amplifier activation signal / SOPn and cross-coupled. P channel MOS transistor PT1 for activating the sense amplifier portion (P sense amplifier) to be activated, and n channel MOS transistors NT2 and NT3 which are turned on in response to sense amplifier activation signal SONn and are cross-coupled. N for activating the sense amplifier (N sense amplifier) portion Including the Yaneru MOS transistor NT1.

  Column select gate IOG (IOG0 or IOG1) is turned on in response to column select signal CSL (CSL0 or CSL1), and n channel MOSs connect corresponding bit lines BL and / BL to local IO lines LIOn and / LIOn, respectively. Transistors Tra and Trb are included.

  Local IO lines LIOn and / LIOn are provided only for the corresponding memory blocks, and are arranged along the word line extending direction. Local IO lines LIOn and / LIOn are connected to global IO lines GIO and / GIO via bank selection switch BSW which is turned on in response to bank selection signal φBA. Global IO lines GIO, / GIO (global IO bus GIOB) are provided in common for all memory blocks MB # 0-MB # N. Therefore, only the local IO lines provided for the selected memory block are connected to global IO bus GIOB.

  FIG. 6 is a diagram showing a configuration of a portion for generating bank selection signal φBA (φBAn). This bank selection signal generator is included in sense / separation control circuit SID (SID # 0-SID # N) shown in FIG. In FIG. 6, bank selection signal generation unit 30 includes an OR gate 32 that receives bank designation signal Ban and adjacent bank designation signal Bam, and an AND gate 34 that receives timing signal φCD and the output signal of OR gate 32. Bank selection signal φBAn is output from AND gate 34. Bank designation signal Bam designates a memory block adjacent to memory block MB # n and designates memory block MB # n-1 or MB # n-1.

  A set of bank designation signals for designating memory blocks sharing the sense amplifier band is applied to the OR gate 32. Timing signal φCD is activated to an H level at a predetermined timing in accordance with this column selection operation start instruction signal when a data write operation or a data read operation is designated and a column selection operation is performed.

  FIG. 7 is a diagram showing an example of the configuration of the timing signal φCD generator shown in FIG. In FIG. 7, command decoder 8a sets timing signal φCD to H level for a predetermined period in accordance with read command READ designating a data read operation or write command WRITE designating a data write operation. Timing signal φCD is applied commonly to memory blocks MB # 0-MB # N. The read command and the write command may be given as a combination of a row address strobe signal / RAS and a column address strobe signal / CAS.

  FIG. 8 shows a structure of a portion generating bit line isolation instructing signals BLI2n and BLI2n-1 shown in FIG. This bit line isolation control signal generating portion is included in sense / isolation control circuit SID (SID # 0-SID # N) shown in FIG. FIG. 8 shows a configuration of a separation signal generator provided for memory block MB # n. In this sense / isolation control circuit, SID # n includes an isolation timing generation circuit 38a for generating bit line isolation instruction signal BLI2n-1, and an isolation timing generation circuit 38b for generating bit line isolation instruction signal BLI2n.

  Isolation timing generation circuit 38a includes an AND circuit 40 that receives bank designation signal Ban and array activation instruction signal φACT, an AND circuit 42 that receives bank designation signal Ban and array deactivation instruction signal (precharge instruction signal) φPRG, It includes a set / reset flip-flop 44 that receives the output signal of AND circuit 40 at set input S and receives the output signal of AND circuit 42 at reset input R. Bit line isolation instruction signal BLI2n-1 is output from complementary output / Q of set / reset flip-flop 44. Isolation timing generation circuit 38b receives bank designation signal Ban-1, array activation instruction signal φACT and array deactivation instruction signal φPRG, and outputs bit line isolation instruction signal BLI2n. Separation timing generation circuits 38a and 38b have the same configuration.

  In the configuration shown in FIG. 8, when memory block MB # n is selected, bit line isolation instruction signal BLI2n-1 is set to the L level. On the other hand, bit line isolation instruction signal BLI2n is maintained at the H level. Selected memory block MB # n is connected to sense amplifier band SA # n.

  In the standby state, isolation instruction signals BLI2n-1 and BLI2n output from isolation timing generation circuit 38b are both at the H level, and memory blocks MB # n-1 and MB # n sharing sense amplifier band SA # n. Are both connected to sense amplifier band SA # n. Each column of the memory block is precharged to the intermediate potential VBL by the bit line precharge / equalize circuit included in the sense amplifier band.

[Embodiment 1]
FIG. 9 shows an operation of the semiconductor memory device according to the first embodiment of the present invention. In FIG. 9, the active command is applied when the row address strobe signal / RAS is at the L level when the clock signal P rises and the column address strobe signal / CAS is at the H level. The read / write command is applied when the row address strobe signal / RAS is at the H level and the column address strobe signal / CAS is at the L level at the rising edge of the clock signal P. Next, the operation will be described.

  In the operation timing chart shown in FIG. 9, a specific memory bank is not shown. In the selected memory bank, the control signal changes as shown in FIG.

  An active command is given at time T1. Accordingly, at time T2, bit line equalize instruction signal BLEQ is rendered inactive at L level. As a result, the bit line precharge / equalize circuit included in the sense amplifier band provided corresponding to the selected memory block is deactivated. If the bit line equalize instruction signal applied to each sense amplifier band is configured so that the equalize / precharge operation is completed when one of the two memory blocks sharing the sense amplifier band is selected. It can be easily generated by taking the logical sum of the bank designation signals for the memory blocks sharing the sense amplifier band.

  Next, at time T3, a row selection operation is performed in the selected memory block, and the potential of the selected word line WL rises.

  At time T4, sense amplifier activation signal SON is activated, and a sense amplifier (N sense amplifier) composed of n-channel MOS transistors included in a sense amplifier band provided corresponding to the selected memory block operates. Then, at time T5, sense amplifier activation signal / SOP is set to the active L level. Thereby, the minute potential generated in each bit line BL, / BL due to the rise of the potential of the selected word line WL at time T3 is detected, amplified and latched. Here, FIG. 9 shows, as an example, potential changes of the bit lines BL and / BL when the selected memory cell holds L level data. With these series of operations, the operation of the row selection system is completed.

  At time T6, a read / write command is given. In accordance with this read / write command, the column selection operation starts, the timing signal φCD is output from the command decoder 8a shown in FIG. 7, and accordingly, the bank designation signal φBA for the selected memory block is set to the H level for a predetermined period (see FIG. 6). ). As a result, the local IO lines LIO and / LIO provided for the selected memory block are connected to the global IO lines GIO and / GIO. In this state, both the global IO line pair and the local IO line pair maintain the precharge state.

  At time T7, the column decoder is activated in accordance with this read / write command, decodes the applied address signal, and raises the column selection signal line CSL to H level. Thus, memory cell data (latched by the sense amplifier) in the selected memory block is transmitted onto global IO lines GIO and / GIO via local IO lines LIO and / LIO. Memory cell data read to global IO lines GIO, / GIO is output via a preamplifier and an output buffer (not shown). When a write command is applied, data is written into the selected memory cell via the global IO lines GIO, / GIO, local IO lines LIO, / LIO and the sense amplifier band by a write driver (not shown).

  By using a signal related to column selection as a signal for controlling the connection between the local IO line and the global IO line, even when a plurality of banks are simultaneously selected, data collision on the global IO bus Does not occur. When this local IO line and global IO line are connected in accordance with a control signal from the row-related control circuit, if the memory bank is in the selected state, the output signal from the row-related control circuit is in the active state, and therefore the local IO line The line and the global IO line are in a connected state. In this case, therefore, data is read from one memory block on the global IO line. In this state, when another bank is accessed, the data in the newly accessed memory bank collides with the data in the previously read memory block, and accurate data reading cannot be performed.

  However, as described in the first embodiment, the local IO line and the global IO line are connected using the control signal related to the column selection, so that only when data is written / read to / from the memory bank. The IO lines LIO, / LIO and the global IO lines GIO, / GIO can be connected, and even when a plurality of memory banks are simultaneously selected, there is no data collision on the global IO line. Data can be read out.

  After writing / reading of data, local IO lines and global IO lines are precharged / equalized to a predetermined potential when the column selection operation is completed.

  When the column decoder is provided in common for memory blocks MB # 0-MB # N, column selection signal CSL is applied in common to all memory blocks. However, since the data of these memory blocks is only transmitted on the local IO lines LIO and / LIO at most and not transmitted to the global IO lines GIO and / GIO, data collision is prevented.

  As described above, in a configuration in which each memory block of a memory array having a shared sense amplifier configuration is used as a bank, connection between a local IO line provided only for each memory block and a global IO line provided in common for the memory block Is generated using a control signal related to the column selection operation, even when a plurality of banks are simultaneously selected, there is no data collision on the global IO line, and it is accurate. Data can be written / read out.

[Embodiment 2]
FIG. 10 shows a structure of a main portion of the semiconductor memory device according to the second embodiment of the present invention. In FIG. 10, array drive circuit DR # n-1 for driving memory block MB # n-1, array drive circuit DR # n for activating / deactivating memory block MB # n, A portion of sense / separation control circuit SID # n for driving sense amplifier band SA # n provided between memory blocks MB # n-1 and MB # n is shown. Sense / separation control circuit SID # n includes sense amplifier activation signal SONn for sense amplifier band (SA # n) in accordance with sense amplifier activation signals applied from both array drive circuits DR # n-1 and DR # n. Sense drive circuit 52 for outputting / SOPn.

  A precharge control circuit 50 is provided for preventing competition between sense amplifier bands for array drive circuits DR # n-1 and DR # n. Precharge control circuit 50 includes means for storing a memory block (bank) using a corresponding sense amplifier band (SA # n), and array activation provided from array drive circuits DR # n-1 and DR # n. In response to the rise of one of the activation instruction signals ractn-1 and ractn, the bank designation signal Ban-1 or Ban is compared with the stored bank address information, and a signal PR indicating the comparison result is output. This signal PR is activated when the corresponding sense amplifier band is in an active state and a memory block different from the memory block to which the sense amplifier band is connected is newly designated. Array drive circuits DR # n-1 and DRn return the activated array to the precharge state in response to activation of signal PR. After returning from the precharge state, the array activation operation of the newly addressed memory block and the connection between the sense amplifier band and the memory block are performed.

  FIG. 11 schematically shows a configuration of array drive circuit DR # n shown in FIG. Array drive circuit DR # n-1 has the same configuration.

  Array drive circuit DR # n receives a bank designation signal Ban, an array activation instruction signal φACT, an array precharge instruction signal φPRG and a signal PR, and outputs a row selection operation activation signal ract. A row selection drive circuit 62 that outputs RALn, RDen, BLIn, and BLEQ as a control signal that is activated in response to the row selection operation activation signal ract and drives a circuit related to row selection, and this row selection drive. An RXT generation circuit 64 that outputs a word line drive timing signal RXTn at a predetermined timing in accordance with an output signal of the circuit 62, and a sense amplifier activation signal SAn after a predetermined period in response to activation of the word line drive timing signal RXTn and A sense activation signal generation circuit 66 for outputting SAp is included. Sense amplifier activation signals SAn and SAp output from sense activation signal generation circuit 66 are applied to sense drive circuit 52 shown in FIG. Sense drive circuit 52 outputs sense amplifier activation signals SONn and / SOPn in accordance with sense activation signals SAn and SAp applied from one of array drive circuits DR # n-1 and DR # n.

  FIG. 12 is a diagram showing an example of the configuration of row selection activation circuit 60 shown in FIG. 12, row selection activation circuit 60 includes an AND circuit 70 that receives bank designation signal Ban and array activation instruction signal φACT, an AND circuit 72 that receives bank designation signal Ban and array precharge instruction signal φPRG, and AND circuit 70. Set / reset flip-flop 74 set in response to the rise of the output signal of AND gate 72 and reset in response to the rise of the output signal of AND gate 72, and signal ractn and signal from output Q of set / reset flip-flop 74 A gate circuit 76 for receiving PR is included. Gate circuit 76 operates as a buffer when signal PR is at the L level, and outputs row selection operation activation signal ract according to signal ractn output from flip-flop 74. When signal PR is set to H level, array row selection operation start instruction signal ract from gate circuit 76 is set to L level.

  When signal ract falls to L level, a precharge operation is performed in which memory block MB # n is deactivated. Therefore, when the precharge control circuit 50 shown in FIG. 10 indicates contention in the sense amplifier band, the active memory block using this sense amplifier is driven to the precharge state. After the activated memory block is driven to the precharged state, the addressed memory block is activated.

  FIG. 13 is a diagram showing an example of the configuration of precharge control circuit 50 shown in FIG. In FIG. 13, precharge control circuit 50 includes a one-shot pulse generation circuit 50aa for generating a one-shot pulse signal that is kept at an H level for a predetermined period in response to the rise of row selection operation start instruction signal ractn-1. One shot pulse generation circuit 50ab for generating a one shot pulse having a predetermined time width in response to the rise of signal ractn, OR circuit 50b for receiving the output signals of one shot pulse generation circuits 50aa and 50ab, and a bank designation signal An inverter 50c that receives Ban-1; an AND circuit 50d that receives the bank designation signal Ban and the output signal of the inverter 50c; an OR gate 50e that receives the bank designation signals Ban-1 and Ban; an output signal of the OR gate 50e and the OR circuit AND gate receiving 50b output signal 50f, an inverter 50g that receives the output signal of AND gate 50f, and an active state when the output signal of inverter 50g is at L level and the output signal of AND gate 50f is at H level, and the output signal of AND circuit 50d is Inverted three-state inverter buffer 50h, delay circuit 50i that delays the output signal of three-state inverter buffer 50h for a predetermined time, latch circuit 50j that inverts and latches the output signal of delay circuit 50i, and output signal of latch circuit 50j Inverter 50k for inverting the output signal, 2-input EXOR circuit 50l receiving the output signal of inverter 50k and the output signal of 3-state inverter buffer 50h, and the output signals of row selection operation start instruction signals ractn-1 and ractn and EXOR circuit 50l 3-input AND circuit 50m No.

  A signal PR is output from the AND circuit 50m. Next, the operation of the precharge control circuit shown in FIG. 13 will be described.

  When memory block MB # n-1 or MB # n is designated, a one-shot pulse is generated from one-shot pulse generating circuit 50aa or 50ab, and the output signal of OR circuit 50b is set to the H level. When memory block MB # n-1 or MB # n is designated, one of bank designation signals Ban-1 or Ban is at H level, and the output signal of OR gate 50e is at H level. As a result, the three-state inverter buffer 50h is activated to invert the output signal of the AND circuit 50d. When bank designation signal Ban-1 is at L level and bank designation signal Ban is at H level, the output signal of AND circuit 50d is at H level. Conversely, when the bank designation signal Ban-1 is at the H level and the bank designation signal Ban is at the L level, the AND circuit 50d outputs an L level signal.

  Therefore, when the memory block using the latest sense amplifier band is memory block MB # n-1, L level ("0") is stored in latch circuit 50j, and the output signal of inverter 50k is accordingly H When the memory block MB # n is at the level (“1”) and uses the sense amplifier band most recently, the L level signal is latched in the latch circuit 50j, and the output signal of the inverter 50k is accordingly Set to H level. A three-state inverter buffer 50h inverts the output signal of the AND circuit 50d. Therefore, when memory block MB # n is designated, the output signal of tristate inverter buffer 50h is at L level, and when memory block MB # n-1 is designated, the output signal of tristate inverter buffer 50h is at H level. It becomes. Therefore, when the memory block that previously used the sense amplifier band is different from the memory block that newly uses the sense amplifier band, the logic of the signal applied to the input of the EXOR circuit 50L is different, and the output of this EXOR circuit 50l The signal becomes H level. On the other hand, when the same memory block continuously uses the sense amplifier band, the output signal of EXOR circuit 50l is at L level. The AND circuit 50m receives the operation start signals ractn-1 and ractn, and detects that the competition of the sense amplifier bands has occurred. Therefore, for example, when memory block MB # n is designated after memory block MB # n-1 is deactivated using the sense amplifier band, generation of this signal PR is surely prohibited. be able to.

  In accordance with the signal PR, the row selection operation activation signal ract applied to the internal row selection drive circuit 62 is held in an inactive state for the delay time of the delay circuit 50i, so that in the shared sense amplifier band. It is possible to prevent contention and drive the other memory block to the active state after returning one memory block to the precharged state. The delay time of the delay circuit 50i may be set to about the RAS precharge time tRP.

  FIG. 14 is a diagram showing another configuration of the precharge control circuit. 14, precharge control circuit 50 includes an AND circuit 78 that receives row selection operation start instruction signals ractn and ractn-1, a delay circuit 79 that delays an output signal of AND circuit 78 for a predetermined time, and an output of delay circuit 79. A gate circuit 80 for receiving the signal and the output signal of AND circuit 78 is included. The gate circuit 80 sets the output signal PR to H level when the output signal of the delay circuit 79 is L level and the output signal of the AND circuit 78 is H level.

  Signals ractn and ractn-1 are both set to the H level. This indicates that the sense amplifier bands are competing. Therefore, when the output signal of AND circuit 78 rises to the H level, signal PR can be raised to the H level, but the competition in the sense amplifier band can be easily detected. The delay time of the delay circuit 79 is about the RAS precharge time tRP. As a result, as in the configuration shown in FIG. 13, contention in the sense amplifier band can be reliably prevented.

  FIG. 15 shows another structure of row selection activation circuit 60 shown in FIG. 15, in addition to the configuration shown in FIG. 12, row selection activation circuit 60 further receives AND gate 77 receiving sense amplifier activation signal SAn and precharge signal PR, and output signals of AND circuits 72 and 77. An OR circuit 79 is included. The output signal of OR circuit 79 is applied to reset input R of set / reset flip-flop 74. Other configurations are the same as those shown in FIG. 12, and corresponding portions are denoted by the same reference numerals. In the configuration shown in FIG. 15, when the sense amplifier activation signal SAn is in the active state, the signal PR is set to the H level, and when the sense amplifier band indicates competition, the flip-flop 74 is reset via the OR circuit 79. Then, the row selection operation activation signal ract is set to L level. Therefore, when another memory block is addressed in the state where the sense amplifier band is used first, the memory block which should be made the non-selected state again after the precharge operation is activated. Can be prevented.

  As described above, according to the second embodiment of the present invention, when memory blocks sharing a sense amplifier band are simultaneously selected, this is detected and the memory block previously selected is selected. Since it is configured to be driven to the inactive state, data competition in the sense amplifier band is prevented, and data can be detected and amplified reliably.

[Embodiment 3]
FIG. 16 shows a structure of a main portion of the semiconductor memory device according to the third embodiment of the present invention. 16, an OR circuit 80 that receives signals PR0 to PRn and a one-shot pulse generation circuit 81 that generates a one-shot pulse having a predetermined pulse width in response to a rise of the output signal of OR circuit 80 are provided. . Signals PR0 to PRn correspond to output signal PR from the precharge control circuit for each memory block shown in the second embodiment. That is, when any of the signals PR0 to PRn rises to H level, it indicates that access competition in the sense amplifier band has occurred in the semiconductor memory device, and the precharge operation of the competing memory block is executed internally. . When this precharge operation is performed, command input inhibition signal INHT is output from one-shot pulse generation circuit 81 and output to the outside of the apparatus. The pulse width of the one-shot pulse generation circuit 81 is a RAS precharge time tRP and a RAS access period tRAS. The RAS access period is a time required until the word line is driven to the selected state in the memory block and the data of the memory cells in the selected row is detected and amplified and latched by the sense amplifier. By outputting the command input inhibition signal INHT to the outside of the device during this period, the external device recognizes that a sense amplifier band conflict has occurred, and is in a wait state during this period.

  As shown in FIG. 16, when the conflict detection signals PR0 to PRn in the sense amplifier band are activated, the command input inhibition signal INHT is output to the outside of the apparatus, thereby confirming that the competition in the sense amplifier band has occurred outside the apparatus. Knowing that it can prevent you from entering another command before the previously given command is fully executed, and if you give a read command after giving an active command, for example, The required data can be read out.

[Embodiment 4]
FIG. 17 shows a structure of a main portion of the semiconductor memory device according to the fourth embodiment of the present invention. In the configuration shown in FIG. 17, an active read command ACTR is newly used as a command related to row selection. When active read command ACTR is applied, row selection operation and column selection operation are continuously performed. That is, the active read command ACTR is a combination of the read command READ and the active command ACT.

  In FIG. 17, row-related command decoder 100 receives active command ACT, precharge command PRG and active read command ACTR, and outputs array activation instruction signal φACT, precharge operation instruction signal φPRG, and read operation activation signal φACTr. To do. Array activation instructing signal φACT is activated when active command ACT or active read command ACTR is applied. Active read command φACTr is activated only when active read command ACTR is applied.

  Internal signal φACTr is applied to column selection control system via delay circuit 102. Delay circuit 102 is formed of, for example, a counter that counts clock signals, delays signal φACTr for a predetermined period (a time corresponding to the RAS-CAS delay time), and outputs internal read operation instruction signal φREADA.

  The column selection control system includes a column command decoder 104 that decodes a read command READ and a write command WRITE, an OR circuit 105 that receives an internal read operation instruction signal φREAD from the column command decoder and a signal φREADA from the delay circuit 102, It includes a column selection control circuit 106 which receives an output signal φACTR of OR circuit 105 and internal write operation activation signal φACTW from column-related command decoder 104 and generates a control signal related to the column selection operation.

  This column selection control circuit 106 activates a column address latch instruction signal CAL for giving a timing for latching a column address, a column decoder enable signal CDE for enabling a column decoder, a preamplifier enable signal PAE for enabling a preamplifier, and a writing circuit. The write driver enable signal WDE to be activated and the output enable signal OE for activating the output buffer are sequentially activated. Preamplifier enable signal PAE and output buffer enable signal OE are activated when internal write operation activation signal φACTR is activated. Write driver enable signal WDE is activated when write operation instruction signal φACTW is activated.

  This column selection control system further responds to the rise and fall of signal PR, and pulse generation circuit 106 that outputs a signal that is kept at a high level for a certain time in response to the rise of array activation instruction signal φACT. A pulse generation circuit 108 for generating a pulse signal and an OR circuit 110 for receiving the output signals of the pulse generation circuits 106 and 108. The pulse width output from the pulse generation circuit 106 is the RAS-CAS delay time tRCD, and has substantially the same active time as the delay time of the delay circuit 102. The pulse width of the pulse signal output from the pulse generation circuit 108 is the sum of the RAS precharge time tRP and the RAS-CAS delay time tRCD. An output signal of the OR circuit 110 is applied to the column selection control circuit 106 as a column related inhibition signal CINT. The column selection control circuit 106 is inhibited from operating when the column inhibition signal CINT is at H level.

  FIG. 18 shows a structure of a portion related to the column selection operation of the semiconductor memory device according to the present invention. In FIG. 18, column address latch 120 takes in and latches a given address in accordance with column address latch instruction signal CAL, and generates an internal column address signal. Column decoder 122 is activated in response to column decoder enable signal CDE, decodes an internal column address signal applied from column address latch 120, and outputs a column selection signal CSL according to the decoding result.

  As described in the first embodiment, the connection between the local IO bus LIOB and the global IO bus GIOB is executed under the control of a control signal from the column selection control circuit.

  The data input / output system is activated in response to the activation of the preamplifier enable signal PAE, and is activated in response to the preamplifier 124 that amplifies data on the global IO bus GIOB and the output buffer enable signal OE. An output buffer 126 for buffering the data amplified by the above to generate output data Q, an input buffer 127 for buffering write data D applied from the outside to generate internal write data, and a write driver enable signal A write driver 128 that amplifies internal write data applied from input buffer 127 in response to activation of WDE and transmits the amplified data to global IO bus GIOB is included.

  FIG. 19 is a diagram showing an example of the configuration of the column selection control circuit 106 shown in FIG. 19, column selection control circuit 106 includes an OR gate 130a receiving internal read operation instruction signal φACTR and internal write operation instruction signal φACTW, and a gate circuit 130b receiving an output signal of OR gate 130a and column inhibit signal CINT. In response to activation of the output signal of gate circuit 130b, decode control circuit 132 for outputting column address latch instruction signal CAL and column decoder enable signal CDE, a gate for receiving internal read operation instruction signal φACTR and column inhibit signal CINT Circuit 134, output control circuit 136 for activating preamplifier enable signal PAE and output buffer enable signal OE for a predetermined period in response to the rise of the output signal of gate circuit 134, internal write operation instruction signal φACTW, and column inhibit signal CI Includes a gate circuit 138 which receives the T, the write control circuit 139 to active state for a predetermined period of write driver enable signal WDE responsive at a predetermined timing the activation of the output signal of the gate circuit 138.

  Gate circuits 130b, 134, and 138 are disabled when column inhibit signal CINT is at the H level and output an L level signal. Internal read operation instruction signal φACTR and internal write operation instruction signal φACTW may each be generated from a set / reset flip-flop. These set / reset flip-flops may be reset in response to the precharge signal φPRG. As shown in FIG. 19, the operation of the column selection control circuit 106 is prohibited during the active state of the column prohibition signal CINT (see FIG. 17) (during the H level), and is completely detected and amplified by the sense amplifier band. The column selection operation and the data write / read operation before the operation are performed are prohibited.

  FIG. 20A is a diagram showing an example of a configuration for 1-bit data of the output buffer 126 shown in FIG. 20A, output buffer 126 includes an inverter 140 receiving internal read data intD read from the preamplifier, an AND circuit 142 receiving internal read data intD and output buffer enable signal OE, and an output buffer enable signal OE. An AND circuit 144 that receives the output signal of inverter 140, an n-channel MOS transistor 146 that conducts when the output signal of AND circuit 142 is at H level and outputs a power supply voltage level signal as read data Dout (Q), and AND It includes an n-channel MOS transistor 148 that conducts when the output signal of circuit 144 is at the H level and outputs read data Dout (Q) at the ground voltage level.

  When output buffer enable signal OE is at L level, AND circuits 142 and 144 both generate an L level output signal, MOS transistors 146 and 148 are both non-conductive, and read data Dout is in an output impedance state. When output buffer enable signal OE is set to H level, AND circuits 142 and 144 operate as buffers, and read data Dout corresponding to internal read data intD is output to the outside of the apparatus.

  FIG. 20B shows a configuration of the output buffer enable signal generation unit. This output buffer enable signal generator is included in column selection control circuit 106 shown in FIG. In FIG. 20B, the output buffer enable signal generating portion counts in response to the rise of the output signal of gate circuit 150 receiving internal read operation activation signal φACTR and column inhibit signal CINT, and the predetermined output signal. An output latency counter 152 that generates an output enable signal OE that becomes H level after the elapse of the period is included. The output latency counter 152 sets the output buffer enable signal OE to the H level for a burst period set in advance or determined by a command.

  As shown in FIG. 17, internal read operation activation signal φACTR is activated to an H level when read command READ or active read command ACTR is applied. The sense amplifier competition detection signal PR is set to the H level for a predetermined period (tRP) when competition in the sense amplifier band occurs. During this time, the output signal of the gate circuit 150 is at the L level. Note that the column selection control circuit 106 shown in FIG. 17 starts the internal operation after the column inhibition signal CINT is set to the L level. Normally, when a read command or a write command is given, it is given after the RAS-CAS delay time tRCD has elapsed. Even when an active command is subsequently given, it is given after the RAS precharge period has elapsed.

  Therefore, during normal operation, output latency counter 152 starts a count operation in accordance with activation of internal read operation activation signal φACTR and deactivation of column inhibit signal CINT (in this case, sense amplifier band conflict detection signal PR). Is L level). On the other hand, if there is contention in the sense amplifier band, the output latency counter 152 starts counting after the column inhibit signal CINT is deactivated after the contention in the sense amplifier band is completed. Here, it is assumed that internal read operation instruction signal φACTR is held at the H level during the read operation period. Therefore, output buffer enable signal OE gives the timing at which read data is accurately output from this semiconductor memory device.

  FIG. 21 shows a structure of an effective data signal output unit used in the fourth embodiment of the present invention. This valid data signal output unit indicates that data requested by an external device (processor) has been reliably output when sense amplifier band contention occurs or in the normal operation mode.

  In FIG. 21, an effective data signal output unit responds to activation of output latency counter 154 which starts a count operation in response to activation of read operation instruction signal φREAD shown in FIG. 17, and activation of active read command detection signal φACTr. The output latency counter 156 that starts the counting operation, the OR circuit 158 that receives the output signals of the output latency counters 154 and 156, the inverter 160 that receives the output buffer enable signal OE, the output signal of the inverter 160, and the output of the OR circuit 158 An AND circuit 162 that receives the signal, conducts when the output signal of AND circuit 162 is at H level, n channel MOS transistor 164 that drives data valid signal / DV to H level of the power supply voltage level, and output buffer enable signal OE H level N channel MOS transistor 166 which is rendered conductive at the time of discharging and discharges data valid signal / DV to the ground potential level.

  The output latency counter 154 counts the same latency period as that of the output latency counter 152 shown in FIG. On the other hand, output latency counter 156 counts the latency period that is the sum of the latency periods of output latency counters 162 and 154 and the delay period of delay circuit 102 shown in FIG. The OR circuit 158 outputs a signal CO according to a predetermined latency period in which valid data is output after a read command or an active read command is given. Therefore, when contention in the sense amplifier band occurs, that is, when an active read command is given, valid data may not be output even if signal CO is set to H level after a predetermined latency elapses. Therefore, the use of the data valid signal / DV indicates that the requested data is accurately output to the processing device (processor) outside the device.

  FIG. 22 is a timing chart showing operations of the output buffer and the data valid signal output unit shown in FIGS. Hereinafter, the output sequence of the data valid signal will be described with reference to FIG. Here, FIG. 22 shows an operation when the active read command ACTR is given.

  At time t1, active read command ACTR is applied to bank BA0 (memory block MB # 0). In accordance with active read command ACTR, an access operation is performed on memory block MB # 0 designated by bank address BA0. In accordance with this active read command, internal active read instruction signal φACTr is activated, and output latency counter 165 shown in FIG. 21 starts counting. After a predetermined period, signal CO from OR circuit 158 is set to the H level. The When no contention occurs in the sense amplifier band, signal PR is at L level and signal CINT is also at LL level. Therefore, output latency counter 152 shown in FIG. 20B is also counted according to internal read operation instruction signal φACTR. The operation is performed, and the output buffer enable signal OE is output after a predetermined period.

  The latency period of the output latency counter 156 is the same as the latency period of the output latency counter 152 and the delay period of the delay circuit 102 shown in FIG. Therefore, signals CO and OE are set to the H level in substantially the same period. When signals CO and OE are both at L level, MOS transistors 164 and 166 shown in FIG. 21 are both nonconductive, and data valid signal / DV is in a high impedance state. When output buffer enable signal OE attains H level, MOS transistor 166 shown in FIG. 21 is turned on, while MOS transistor 164 is in a non-conductive state, and data valid signal / DV is driven to the L level of the ground potential level. The Thereby, the processing device outside the device knows that valid data is output. The output buffer enable signal OE is set to the H level during a period normally called “burst length”, and data is sequentially output in synchronization with the clock signal P during this period. This active read command ACTR does not instruct a precharge operation. Therefore, memory block MB # 0 is in an active state. In this state, at time t2, active read command ACTR is applied according to bank address BA1. Here, it is assumed that the time between times t1 and t2 is set to a period in which read data collision does not occur in consideration of CAS latency and burst length. Therefore, necessary data is sequentially read from memory block MB # 0 designated by bank address BA0, and after a long period of designated burst, signals CO and OE attain L level, and output data Dout and data valid signal / Both DVs are in a high impedance state.

  At time t2, active read command ACTR is applied according to bank address BA1 in the active state of memory block MB # 0. Bank address BA1 designates memory block MB # 1 sharing sense amplifier band SA # 1 with memory block MB # 0. In this state, as described above, precharging of memory block MB # 0 is performed. After the precharge of memory block MB # 0 designated by bank address BA0 is completed, the memory block designated by bank address BA1 is activated. Outside the apparatus, it is not recognized that the contention of the sense amplifier band is occurring (it can be known by the command input inhibition signal for the period shown in FIG. 16), and valid data is output after a predetermined latency elapses. Cannot determine whether or not.

  In this case, according to the active read command, the output signal of the output latency counter 156 shown in FIG. 21 becomes H level, and accordingly the signal CO becomes H level after a predetermined period. However, during this period, since the sense amplifier conflict detection signal PR is at the H level for a predetermined period, the output buffer enable signal OE from the output latency counter 152 is maintained at the L level via the column prohibition signal CINT. In this state, as shown in FIG. 21, MOS transistor 166 is non-conductive, while MOS transistor 164 is turned on in response to the rise of signal CO, and data valid signal / DV is set to the H level. . Therefore, an external processor monitors that this data valid signal / DV is at the H level, and recognizes that no valid data is output due to competition of the sense amplifier band (precharge wait state).

  When precharge of memory block MB # 0 designated by bank address address BA0 is completed and memory block MB # 1 designated by bank address BA1 is activated and column selected, the output shown in FIG. The output buffer enable signal OE from the latency counter 152 becomes H level, and valid data is output at time t4. When output buffer enable signal OE attains H level, MOS transistor 166 shown in FIG. 21 is rendered conductive, and data valid signal / DV is set to L level. Therefore, the processor outside the storage device can recognize that valid data is output from time t4 by monitoring this data valid signal / DV. As a result, even when a sense amplifier band conflict occurs, the processing device outside the storage device can accurately capture the required data.

  Such a sense amplifier contention does not occur when a read command is given. In this case, since output latency counter 152 shown in FIG. 20B and output latency counter 154 shown in FIG. 21 operate at substantially the same timing, output buffer enable signal OE and signal CO are at the H level at substantially the same timing. Active state. Therefore, even when a read command is given, it can be recognized that valid data has been output accurately.

  In the above-described fourth embodiment, data valid signal / DV is set to L level when data required by the processor (expected data) is being output, and in a precharge wait state due to contention in the sense amplifier band. However, in the precharge wait state, signal / DV may be set to L level, and signal / DV may be set to H level during the expected data output period. The valid data signal / DV is in a high impedance state in the standby state (a period other than the data output period indicated by the latency and the actual data output period), and this high impedance state indicates whether the data is valid / invalid. Absent.

  As described above, according to the fourth embodiment of the present invention, since the data valid signal output unit is provided, the external device can accurately detect the conflict in the sense amplifier band in the semiconductor memory device. You can capture the data you need.

[Embodiment 5]
FIG. 23 shows a structure of the data valid signal output portion of the semiconductor memory device according to the fifth embodiment of the present invention. In FIG. 23, the output latency counter 152a outputs the data valid enable signal OEF at a timing that is one or two clock cycles faster than the output buffer enable signal OE. Data valid signal enable signal OEF is applied to inverter 160 and MOS transistor 166. Other configurations are the same as those shown in FIG.

  FIG. 24 is a timing chart showing the operation of the data valid signal output unit shown in FIG. At time t1, bank address BA and active read command ACTR are applied. In this case, it is during normal operation, and no contention in the sense amplifier band occurs. In this state, valid data is output according to the output buffer enable signal OE from time t3. The data valid enable signal OEF is activated at a timing one clock cycle faster than the output buffer enable signal OE, and the data valid signal / DV is set to L level accordingly. When the burst long period elapses, the data valid signal / DV is set to the high impedance state at time t4. Valid data is also output at the next time t5. The external processor detects the number of data to be read based on the burst length. Therefore, when the valid data signal / DV is activated, valid data can be taken from the next clock cycle. Therefore, valid data can be taken in after one clock cycle has elapsed since the signal / DV is notified that valid data is output, and a time margin for fetching data can be secured. Can be taken in by an external device.

  When active read command ACTR and bank address BA1 are applied at time t4, sense amplifier band competition occurs, and memory block MB # 0 designated by bank address BA0 is inactivated. In this case, since the data to be output is not yet prepared in the period in which the valid data is output, the signal OE remains at the L level (the output latency counter 152a has not completed the count-up operation), and the valid data is output. Data signal / DV is driven to H level by MOS transistor 164. As a result, the external device recognizes that the bank has been precharged due to competition of the sense amplifier band, and maintains the wait state.

  When precharging of the competing bank is completed, the bank to be accessed is selected, and necessary data is read, first, at time t6, the enable signal OEF is set to the H level, and the valid data signal / DV is set to L level. Next, valid data is sequentially output in a clock cycle starting from time t7.

  In this way, by setting the data valid signal / DV to the L level active state one or more cycles before, an external device can reliably take in valid data with a margin.

  FIG. 25 schematically shows a structure of output latency counter 152a shown in FIG. In FIG. 25, an output latency counter 152a is activated in response to a signal given from the gate circuit 150 shown in FIG. 20B, and count circuit 152aa that counts the clock signal P, and a count-up signal from the count circuit 152aa. The clock signal P is started up according to cua, counts the clock signal P, and keeps the output buffer enable signal OE at H level until the count value reaches a predetermined value, and responds to the count-up signal cuf from the count circuit 152aa And a count circuit 152ac that counts the clock signal P and drives the enable signal OEF to the H level until the count value reaches a predetermined value.

  The number of clock cycles counted by the count circuit 152aa is the number of output latencies, and the number of clock cycles counted by the count circuits 152ab and 152ac is the number of clock cycles defined by the burst length. Therefore, count circuits 152ab and 152ac drive clock cycle period signals OE and OEF defined by the burst length to H level according to the count-up instruction signal from count circuit 152aa, respectively. The count-up signal cuf output from the count circuit 152aa may be activated at a timing (clock cycle) faster than the count-up signal cua that is activated after the output latency has elapsed.

  As described above, according to the fifth embodiment of the present invention, the data valid signal is activated in the cycle before the clock cycle in which valid data is output. Can take in.

[Embodiment 6]
FIG. 26 schematically shows a structure of an effective data output unit according to the sixth embodiment of the present invention. 26, the one-shot pulse generator 155 that generates a one-shot pulse COP according to the signal CO from the gate 158 shown in FIG. 21 and the one-shot pulse according to the output buffer enable signal OE from the output latency counter 152. A one-shot pulse generator 159 for generating a pulse OEP is provided. One-shot pulse generators 155 and 159 have the same configuration. In FIG. 26, the configuration of the one-shot pulse generator 159 is representatively shown.

  The one-shot pulse generator 159 is set in response to the rise of the pulse generation circuit 160 and a pulse generation circuit 160 that generates a pulse signal having a predetermined time width according to the output buffer enable signal OE. Includes a set / reset flip-flop 162 that is reset in response to. A pulse signal OEP is output from the output Q of the flip-flop 162. Pulse signal COP is applied to one input of AND circuit 162, and AND circuit 162 receives pulse signal OEP via inverter 160 at the other input. Pulse signal OEP is also applied to the gate of MOS transistor 166. MOS transistor 164 receives an output signal of AND circuit 162.

  FIG. 27 is a timing chart showing the operation of the valid data signal output unit shown in FIG. Also in the operation sequence shown in FIG. 27, when active read command ACTR and bank address BA0 are applied at time t1, normal access is performed, and bank address BA1 and active read command ACTR are applied at time t2. Suppose that a sense amplifier band conflict sometimes occurs. In this case, activation of the memory bank (memory block) and selection of the memory cell are performed according to command ACTR applied at time t1, and pulse signals COP and OEP rise to H level at time ta. In this state, MOS transistor 66 is rendered conductive and data valid signal / DV falls to the L level.

  On the other hand, in the case of the active read command applied at time t2, a sense amplifier band conflict has occurred, and the memory block specified by bank address BA0 is precharged. In this case, at time t3, the pulse signal COP from the one-shot pulse generator 155 is set to the H level. On the other hand, pulse signal OEP is at L level, the output signal of AND circuit 162 is at H level, MOS transistor 164 is turned on, and data valid signal / DV is at H level.

  At time t4, an access operation is performed in accordance with active read command ACTR and bank address BA, and when valid data is output, pulse signal OEP is at H level, MOS transistor 166 is rendered conductive, and data valid signal / DV is L level.

  As shown in FIG. 27, even if the data valid signal / DV is output in the form of a one-shot pulse, the data valid signal is in the H level, L level, or high impedance state. A standby state can be indicated. The external device recognizes in advance the number of data to be read based on the burst length data.

  In the configuration shown in FIG. 26, data valid signal / DV is at the L level in the form of a one-shot pulse in the clock cycle in which valid data is output. In this case, the pulse signal OEP may be activated in a cycle prior to the clock cycle in which valid data is output. Similarly, the pulse signal COP is configured to be generated in the same clock cycle as the pulse signal OEP. The data valid signal / DV becomes H level one clock cycle before the elapse of a predetermined latency number. Therefore, since the validity / invalidity of the data can be always recognized one to several clock cycles before the data is taken in, the determination timing when the data is valid and invalid can be made the same, and the load of the external device is It is reduced.

[Embodiment 7]
FIG. 28 is a timing chart showing a data valid signal output sequence according to the seventh embodiment of the present invention. In the timing chart shown in FIG. 28, data valid signal / DV is at the H level in the standby state, and is at the L level when valid data is output. The operation sequence is the same as that described in the previous embodiment. That is, data valid signal / DV is set to H level when valid data is not output. On the other hand, when valid data is output at time t2 in accordance with active read command ACTR applied at time t1, data valid signal / DV is set to L level. When the active read command ACTR is applied again at time t2, valid data is output from time t4, and no valid data is output at time t3 from a predetermined output latency, the data valid signal / DV is at time t3. It is held at the H level and set to the L level when valid data is output from time t4.

  By setting the data valid signal / DV to a binary state of H level and L level, this configuration can also be applied to a processing system using a high-speed interface such as GTL (Ganning transceiver logic).

  FIG. 29 is a diagram showing a configuration of a valid data signal output unit that generates data valid signal / DV shown in FIG. In FIG. 29, the valid data signal output portion includes an n-channel MOS transistor 172 that is turned on in response to output buffer enable signal OE and drives output node 171 to the L level. Output node 171 is coupled to processor PU via signal line 173. A pull-up resistor Ru is connected to the signal line 173. The processor PU includes a comparator for determining the input signal level, which compares the reference voltage Vref and the potential on the signal line 173 in the input buffer unit. In the standby state, that is, when valid data is not output, output buffer enable signal OE is at L level, and MOS transistor 172 is in an off state. In this state, the signal line 173 is driven to the H level by the pull-up resistor Ru. On the other hand, when valid data is output, the output buffer enable signal OE becomes H level, the MOS transistor 172 becomes conductive, and the signal line 173 is driven to L level. As a result, the data valid signal / DV can be output in the form of a binary signal.

  FIG. 30 shows a structure of a modification of the seventh embodiment of the present invention. In FIG. 30, the data valid signal output unit is turned on when inverter 174 that inverts output buffer enable signal OE and the output signal of inverter 174 are at L level, and p channel MOS that drives output node 171 to the power supply voltage level. Transistor 175 is included. Output node 171 is coupled to processor PU via signal line 173. The signal line 173 is provided with a pull-down resistor Rd. The input buffer of the processor PU compares the reference voltage Vref with the potential on the signal line 173 to determine the logic level of the input signal.

  In the standby state and when valid data is not output, output buffer enable signal OE is at L level, and the output signal of inverter 174 is at H level. Therefore, MOS transistor 175 is non-conductive, and node 171 and signal line 173 are driven to the L level of the ground potential level by pull-down resistor Rd. On the other hand, when valid data is output, the output buffer enable signal OE becomes H level, the output signal from the inverter 174 becomes L level accordingly, and the MOS transistor 175 becomes conductive. Thereby, the data valid signal DV transmitted on the signal line 173 is set to the H level. Therefore, in the configuration shown in FIG. 30, a data valid signal DV is generated which is L level in the standby state and H level when valid data is output, and whether or not valid data is output is determined by this binary level. I can know.

  29 and 30 may be configured such that the data valid signal is determined to be in the valid data output instruction state in the clock cycle before valid data is output. These MOS transistors 172 and 175 may be configured to drive the signal line 173 to the L level or the H level in the form of a one-shot pulse.

  As described above, according to the seventh embodiment of the present invention, since it is configured to output a binary level data valid signal, even in a processing system using a high-speed interface, the time point at which valid data is accurately output is determined. The external device processor can be informed and the external device can accurately capture valid data.

[Embodiment 8]
FIG. 31 shows a structure of the data output unit according to the eighth embodiment of the present invention. In FIG. 31, the data output unit includes read amplification circuit 180 for amplifying 9-bit data read from the selected memory block in parallel, and internal read data iD0 to iD7 and iD8 read from read amplification circuit 180. An output circuit 182 that outputs in accordance with the output buffer enable signal OE is included. The internal read data iD8 is a parity bit. Therefore, the valid data D0 to D7 and the parity bit D8 are output in parallel to the outside.

  FIG. 32 is a diagram illustrating a configuration of an output buffer for 1-bit data included in the output circuit 180. In FIG. 32, the output buffer includes an inverter 183 receiving internal read data iDj, an AND circuit 184 receiving the output signal of inverter 183 and output buffer enable signal OE, and an output node 185 in response to the output signal of AND circuit 184. Includes an n channel MOS transistor 186 for driving to the ground potential level. Read data Dj is output to node 185 and applied to the processor. Output node 185 is coupled to pull-up resistor Ru. It is assumed that the parity bits are determined so that the number of high-level bits of the data D0 to D8 is an even number in a normal state. In the standby state, output buffer enable signal OE is at L level, MOS transistor 186 is non-conductive, and output node 185 is set to H level by pull-up resistor Ru. Therefore, the data D0 to D7 and the parity bit D8 are all at the H level, and the number of the H level data bits is an odd number. By monitoring this number by the processor, it is determined that a parity error state has occurred and no valid data has been output. When valid data is output, data D0-D8 changes to H level or L level according to the internal read data. In this state, since no parity error has occurred, the processor determines that valid data is being output.

  FIG. 33 is a timing chart representing a data read sequence according to the eighth embodiment of the present invention. Hereinafter, the data output sequence will be described with reference to FIG. When active read command ACTR is applied at time t1 and bank address BA0 is applied, data D0 to D7 and parity bit D8 are all at H level until valid data is output at time ta. In this state, the processor determines that it is a parity error state and that valid data is not output. When output buffer enable signal OE is activated and valid data is output at time ta, data D0 to D8 change according to internal read data iD0 to iD8, respectively.

  Therefore, in this state, the parity is accurately determined, and the processor determines that valid data has been output. However, in the standby state, that is, when valid data is not output, all the data D0 to D8 are set to indicate a parity error state, and when valid data is output, the parity error is canceled. That is, when bank address BA1 and active read command ACTR are applied at time t2 and no valid data is output at time t3, data D0 to D8 are all at the H level and are in a parity error state. Therefore, the processor does not take in data in this state. When valid data is output at time t4, the parity error is canceled (the internal read data is normal data), the processor determines that valid data has been output, and starts taking in data.

  FIG. 34 shows a structure of a modification of the eighth embodiment of the present invention. In FIG. 34, the configuration of a 1-bit output buffer included in the output circuit 182 is shown. 34, the output buffer conducts when NAND circuit 190 receives internal read data iDj and output buffer enable signal OE, and the output signal of NAND circuit 190 is at L level, and outputs an H level signal to output node 185. P channel MOS transistor 192 to be included. The output node 185 is provided with a pull-down resistor Rd. In the configuration shown in FIG. 30, when valid data is not output, that is, when output buffer enable signal OE is at L level, the output signal of NAND circuit 190 is at H level, and MOS transistor 192 is in a non-conductive state. Output node 185 is driven to the L level. On the other hand, when output buffer enable signal OE is at H level and valid data is output, NAND circuit 190 acts as an inverter. When internal read data iDj is at L level, MOS transistor 192 is turned off. When the internal read data iDj is at the H level, the output signal of the NAND circuit 190 is at the L level, the MOS transistor 192 is turned on, and the data Dj from the output node 185 is at the H level. Level.

  In the configuration shown in FIG. 30, data output node 185 is driven to the L level in the standby state (when no valid data is output), and is driven to the potential level corresponding to the internal read data when valid data is output. Is done. Therefore, when a parity error is determined when there are an odd number of L-level data bits among the nine data bits D0 to D8, the data bits D0 to D8 are in a standby state (when no valid data is output). Are all at L level, and the number of L level data is an odd number, which is a parity error state. By monitoring this state, the processor determines that valid data is not output.

  In the eighth embodiment of the present invention, one of the configurations shown in FIGS. 32 and 34 may be used according to the parity error determination method in the processing system used.

  According to the eighth embodiment of the present invention, when parity bits are included, all these data bits are held in a state where a parity error exists in the standby state (when no valid data is output). Therefore, it is not necessary to use an extra valid / invalid instruction circuit, and it is possible to notify a processor as an external device of the timing at which valid data is output without causing an increase in data output nodes (terminals).

[Other application examples]
In the above description, a clock synchronous semiconductor memory device is described, and a multi-bank DRAM is described. However, the configuration for notifying an external device of the state in which valid data is output can also be used in a standard DRAM. The output buffer enable signal OE may be output to the outside of the apparatus.

  The present invention can be applied to a clock synchronous semiconductor memory device having a plurality of banks.

1 schematically shows an entire configuration of a semiconductor memory device according to the present invention. FIG. FIG. 2 is a diagram schematically showing a configuration of an array drive circuit shown in FIG. 1. FIG. 3 is a timing chart showing the operation of the array drive circuit shown in FIG. 2. FIG. 2 is a diagram schematically showing a configuration of a memory block and a sense amplifier band shown in FIG. 1. FIG. 5 is a diagram more specifically showing a configuration of a sense amplifier band shown in FIG. 4. FIG. 6 is a diagram schematically showing a configuration of a control circuit for connecting a local IO bus and a global IO bus shown in FIG. 5. It is a figure which shows schematically the structure of the part which generate | occur | produces the control signal shown in FIG. FIG. 6 schematically shows a configuration of a bit line isolation signal generator shown in FIG. 5. FIG. 6 is a timing chart showing an operation of the semiconductor memory device according to the first embodiment of the present invention. FIG. 11 schematically shows a structure of a main portion of a semiconductor memory device according to the second embodiment of the present invention. FIG. 11 schematically shows a configuration of the array drive circuit shown in FIG. 10. FIG. 12 schematically shows a configuration of a row selection activation circuit shown in FIG. 11. FIG. 12 schematically shows a configuration of a sense drive circuit shown in FIG. 11. It is a figure which shows schematically the structure of the example of a change of Embodiment 2 of this invention. It is a figure which shows schematically the structure of the example of a change of the row selection active circuit in Embodiment 2 of this invention. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 3 of this invention. FIG. 14 schematically shows a configuration of a column selection unit in a semiconductor memory device according to a fourth embodiment of the present invention. 1 schematically shows a structure of a data input / output unit of a semiconductor memory device according to the present invention. FIG. FIG. 18 schematically shows a configuration of a column selection control circuit shown in FIG. 17. (A) shows the configuration of the output buffer shown in FIG. 18, and (B) schematically shows the configuration of the output control circuit shown in FIG. It is a figure which shows roughly the structure of the principal part of the data storage device according to Embodiment 4 of this invention. FIG. 22 is a timing chart showing the operation of the circuit shown in FIGS. 20 and 21. It is a figure which shows the structure of the effective data signal output part of Embodiment 5 of this invention. FIG. 24 is a timing chart showing the operation of the circuit shown in FIG. 23. It is a figure which shows schematically the other structure of the data effective signal output part according to Embodiment 5 of this invention. It is a figure which shows roughly the structure of the data effective signal output part according to Embodiment 6 of this invention. FIG. 27 is a timing chart showing the operation of the data valid signal output unit shown in FIG. 26. It is a timing chart figure which shows the operation | movement of the data effective signal output part according to Embodiment 7 of this invention. It is a figure which shows schematically the structure of the data effective signal output part which implement | achieves the operation | movement timing shown in FIG. It is a figure which shows roughly the structure of the example of a change of the data effective signal output part according to this invention. It is a figure which shows roughly the structure of the data effective signal output part according to Embodiment 8 of this invention. FIG. 32 is a diagram showing a configuration of a 1-bit portion of the output circuit shown in FIG. 31. FIG. 32 is a timing chart showing the operation of the output circuit shown in FIGS. 31 and 31. It is a figure which shows the structure of the example of a change of Embodiment 8 of this invention.

Explanation of symbols

  1 memory array, SA # 0 to SA # L + 1 sense amplifier band, MB # 0 to MB # N memory block, DR # 0 to DR # N array drive circuit, SID # 0 to SID # N + 1 sense / separation control circuit, 8 Command decoder, 10 bank decoder, 20 row control circuit, 22 row latch, 21 row decoder, 26 word driver, SAa1, SAa2, SAb1, SAb2 sense amplifier circuit, SA1, SA0 sense amplifier, PE bit line precharge / equalize circuit, LIOn, / LIOn Local IO (input / output) bus, GIO, / GIO global input / output (IO) bus line, GIB global IO bus, BSW memory block selection gate, 30 memory block selection control circuit, 38a, 38b separation timing generation circuit , 50 Recharge control circuit, 52 sense drive circuit, 60 row selection activation circuit, 62 row selection drive circuit, 64 RXT generation circuit, 66 sense activation signal generation circuit, 50j latch circuit, 100 row command decoder, 102 delay circuit, 104 columns System command decoder, 105 OR circuit, 106 column selection control circuit, 126 output buffer, 136 output control circuit, 152, 154, 156, 152a, 152, 154, 156 output latency counter, 164, 166 n-channel MOS transistor, 172 n Channel MOS transistor, 175 p channel MOS transistor, 186 n channel MOS transistor, 192 p channel MOS transistor.

Claims (6)

A memory array having a plurality of memory cells arranged in a matrix;
A row selecting means activated in response to an array activation instruction signal and selecting a row of the memory array according to a first address signal;
A reading means which is activated in accordance with a read operation instruction signal, selects a column of the memory array in accordance with a second address signal when activated, and reads data of a memory cell on the selected column to the outside of the device; A semiconductor memory device comprising data valid signal output means for outputting a data valid signal indicating that data read from the reading means to the outside of the device is valid in response to an operation instruction signal.   The data valid signal output means holds the data valid signal at a first level when the semiconductor memory device is in a standby state, and is different from the first level when valid data is output from the reading means. 2. The semiconductor memory device according to claim 1, further comprising means for driving the data valid signal to a level of. The semiconductor memory device operates in synchronization with a clock signal,
2. The semiconductor memory according to claim 1, wherein said data valid signal output means includes means for activating said data valid signal in a clock cycle before a clock cycle in which valid data from said data read / output means is output. apparatus.   2. The semiconductor memory device according to claim 1, wherein said data valid signal output means includes means for holding said data valid signal in an active state during an output period of valid data from said data read / output means.   The data valid signal output means includes means for outputting the data valid signal in the form of a one-shot pulse having a constant pulse width that is determined independently of the period of output of the valid data from the data read / output means. The semiconductor memory device according to claim 1. The semiconductor memory device includes means for storing parity bits for error correction,
The read / output means includes means for holding the data output node at the first level when inactive,
The data valid signal output means includes means for activating the read / output means at the same time and outputting a parity bit read from the parity bit storage means, and for outputting the output node from the read / output means during standby. 2. The semiconductor memory device according to claim 1, further comprising means for holding the output data at a level indicating the presence of a parity error.

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