JP2006252647A - Information signal amplitude measurement circuit, optical information recording and/or reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately measure amplitude of an RF information signal read by an optical pickup from an optical disk and to more exactly perform monitoring of amplitude of the RF information signal and adjustment of amplitude of the read signal, etc. <P>SOLUTION: This information signal amplitude measurement circuit is equipped with a comparator 131 for peak detection which binarizes a high frequency information signal read by the optical pickup 112 from the optical disk 111 and to which amplification processing is performed, peak detection circuits (an up counter 132 for peak, a first D/A converter 133) which detect a peak level from the binarized signal, a comparator 134 for bottom detection which binarizes the information signal, bottom detection circuits (an up counter 135 for bottom, a second D/A converter 136) which detect a bottom level from the binarized signal and a subtraction circuit 137 which calculates an amplitude value and supplies output of a subtractor 137 as an information signal amplitude value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an information signal amplitude measurement circuit capable of accurately measuring the amplitude of an RF information signal recorded on an optical recording medium such as an optical disc, and an optical information recording and the like of an optical disc apparatus equipped with the information signal amplitude measurement circuit. The present invention relates to a playback device.

2. Description of the Related Art Conventionally, in an optical disc apparatus that reads and reproduces information data recorded on an optical recording / reproducing optical disc such as a compact disc with an optical pickup using a laser beam, the type or manufacturing of the optical disc to be reproduced There is a problem that the amplitude of the reproduction signal varies depending on the variation of the apparatus and the characteristics of the apparatus.
In particular, recent optical disk devices, such as DVD-ROM drives, play a variety of optical disks (CD, CD-R, CD-RW, DVD 1 layer, DVD 2 layer, DVD-R, DVD-RAM, DVD-RW, etc.). The variation of the amplitude of the reproduction signal is likely to occur.
Therefore, a signal proportional to the level of the information signal read from the disk is taken into the system controller, etc., and the level of the information signal is adjusted accurately, and an amplitude adjustment function is provided to make the information data reproduction ability stable and high performance. It is
In the production of optical pickups, the amplitude of the reproduction signal is an important index for the assembly, adjustment, evaluation, and quality control of the optical pickup. It is important for improvement.

Therefore, a specific conventional example of an optical disc apparatus equipped with this type of information signal amplitude measurement circuit will be described (see Patent Document 1).
FIG. 10 is a block diagram showing a configuration example of a conventional DVD system.
A disc (optical disc) 11 that is a recording medium records binary digital data on a track and is driven to rotate by a disc motor 13. The disk motor 13 is driven and controlled by a disk motor control circuit 24 and a driver 23.
An optical pickup 12 that is a signal extraction means for reading information data recorded on the disk 11 irradiates a track on the rotating disk 11 with a laser beam, reflects off the track on the disk 11, and returns. Information data is read by detecting a change in the amount of light coming and output as an electrical signal.
The information signal read by the optical pickup 12 is a high frequency (RF) analog signal of several hundreds of kHz to several tens of MHz.

This RF signal (information signal) is calculated and amplified by a variable gain RF amplifier (head amplifier) 15. The RF amplifier 15 is controlled by an automatic gain control (AGC) loop so that the RF signal output has a predetermined constant amplitude suitable for signal processing in the subsequent stage. That is, the RF signal (information signal) output from the RF amplifier 15 is A / D converted by the A / D conversion circuit 29, and the peak / bottom detection circuit 30 generates an amplitude signal substantially proportional to the RF signal level. 25.
The system controller 25 checks the RF signal level of various disks targeted by the DVD system, and sets the gain of the RF amplifier 15 so that this level becomes a preset target value.

The RF signal output from the RF amplifier 15 is sliced (binarized) by the data slicing circuit 18, and the binarized data RFDATA is sent to the data PLL (phase locked loop) synchronization separation circuit 19, where A clock PLCK synchronized with the binary data is generated, and demodulated data DATA is obtained.
The clock PLCK and demodulated data DATA are sent to the error correction circuit 20, where the data is written in the correction RAM 21 and subjected to correction processing, and then in the case of a DVD movie, it is sent to the MPEG video decoder & audio decoder processing circuit 22. In the case of a DVD-ROM drive, it is sent to the data buffer 22.
The servo signal output from the RF amplifier 15 is input to the driver 17 via the servo control circuit 16, and the actuator of the optical pickup 12 is driven by the output of the driver 17.
The feed motor 14 drives a sliding actuator for moving the optical pickup 12 in the disk radial direction.

FIG. 11 is a block diagram showing the configuration of the peak / bottom detection circuit 30.
12 is a waveform diagram showing an operation example of the peak / bottom detection circuit shown in FIG. 11. FIG. 12 (a) shows an example of an RF waveform, and FIG. 12 (b) is converted by the A / D converter 29. FIG. 12C shows an example of a waveform after detection by the peak / bottom detection circuit.
In the A / D conversion circuit 29 described above, when the RF signal is converted, the signal is sampled and converted into a digital value completely asynchronously with the RF signal as shown in FIG. Here, the A / D conversion circuit 29 uses a low-speed, inexpensive A / D conversion circuit 29 that samples at a frequency as low as about 1/10 of the RF signal frequency and converts it to a digital value.
The A / D converted data is stored in the A / D data register 44 of the peak / bottom detection circuit 30.

The peak / bottom detection circuit 30 shown in FIG. 11 is divided into a peak detection side and a bottom detection side.
On the peak detection side, the value of the peak counter 42 and the value of the A / D data register 44 are periodically compared in the first comparator 43, and the result is transmitted to the peak counter input control circuit 41. To change.
When the value of the A / D data register 44 is larger than the value of the peak counter 42, the peak counter 42 is counted up for a certain period with a fast clock pulse, and when it is smaller, the peak counter 42 is counted down for a certain period with a later clock pulse. Is done.
As a result, when a large value is stored in the A / D data register 44, the peak detection waveform rapidly increases, and when a small value is stored in the A / D data register 44, the peak detection waveform slowly decreases. .

On the bottom detection side, the second comparator 47 periodically compares the value of the bottom counter 46 with the value of the A / D data register 44, and the result is transmitted to the bottom counter input control circuit 45. Change the value of.
When the value of the A / D data register 44 is smaller than the value of the bottom counter 46, the bottom counter 46 is counted down with a fast clock pulse, and when it is larger, the bottom counter 46 is counted up with a slow clock pulse.
That is, as shown in FIG. 12C, when a small value is stored in the A / D data register 44 in contrast to the peak detection, the bottom detection output suddenly drops and a large value is displayed in the A / D data register. When stored in 44, the bottom detection output slowly rises.
In this way, peak detection and bottom detection are performed, the difference is calculated by the subtractor 48 for calculating the RF amplitude, and the value 49 is read by the system controller 25.

However, as can be seen from the detection waveform of FIG. 12C, the detection waveform varies in a sawtooth shape, and it cannot be said that the true RF amplitude is always maintained.
Although the magnitude of this fluctuation is reduced by slowing the clock pulse to the counter, it is possible to simultaneously detect the RF amplitude with high accuracy and respond to the transient fluctuation of the RF peak / bottom level. Is difficult.
If the amplitude of the RF information signal cannot be measured with high accuracy in this way, there is a possibility that the apparatus cannot be adjusted to an optimal state or cannot be evaluated correctly.
JP 2001-167440 A

  As described above, the conventional optical disc apparatus cannot measure the amplitude of the RF information signal read from the optical disc by the optical pickup with high accuracy, and cannot adjust the optical disc apparatus to an optimum state or correctly evaluate it. There was a problem.

  Therefore, the present invention provides an information signal amplitude measuring circuit and an optical information recording and / or reproducing apparatus capable of measuring the amplitude of an RF information signal read from an optical recording medium with high accuracy regardless of the signal level. Objective.

  In order to achieve the above object, an information signal amplitude measuring circuit according to the present invention has an input means for inputting a high-frequency information signal read from an optical recording medium by an optical pickup and subjected to amplification processing, and input by the input means. Corresponding to the peak comparison means for comparing the information signal with the variable reference value for peak detection, the peak counter for performing the counting operation according to the comparison result of the peak comparison means, and the count value output of the peak counter Peak reference value update means for supplying a variable reference value to the peak comparison means, bottom comparison means for comparing an information signal input by the input means with a variable reference value for bottom detection, and the bottom comparison means And a variable reference value corresponding to the output of the bottom counter. And bottom reference value updating means for supplying to the comparison means, and having a calculating means for calculating the amplitude value of the information signal using the count value output and the peak counter by the bottom counter.

  The optical information recording and / or reproducing apparatus of the present invention includes an optical pickup that reads a signal from an optical recording medium, and a high-frequency amplifier that amplifies and calculates a high-frequency signal read by the optical pickup to generate a high-frequency information signal A circuit, an information signal amplitude measuring circuit for measuring the amplitude of the information signal generated by the high frequency amplifier circuit, and a notification device for notifying the amplitude value measured by the information signal amplitude measuring circuit. An amplitude measurement circuit compares an information signal input by the input means with an input means for inputting a high-frequency information signal read from the optical recording medium by an optical pickup and amplified, and a variable reference value for peak detection. A peak comparison unit, a peak counter that performs a counting operation in accordance with a comparison result of the peak comparison unit, and the peak Peak reference value update means for supplying a variable reference value corresponding to the count value output of the counter to the peak comparison means, and bottom comparison for comparing the information signal input by the input means with a variable reference value for bottom detection Means, a bottom counter that performs a counting operation according to the comparison result of the bottom comparison means, and a bottom reference value update means that supplies a variable reference value corresponding to the output of the bottom counter to the bottom comparison means And calculating means for calculating an amplitude value of the information signal using count value output from the peak counter and the bottom counter.

  The optical information recording and / or reproducing apparatus according to the present invention includes an optical pickup that reads a signal from an optical recording medium, and a variable gain that amplifies and calculates a high-frequency signal read by the optical pickup to generate a high-frequency information signal. Type high frequency amplifier circuit, information signal amplitude measuring circuit for measuring the amplitude of the information signal generated by the high frequency amplifier circuit, and comparing the amplitude value measured by the information signal amplitude measuring circuit with a predetermined set value And a control device that controls the gain of the high-frequency amplifier circuit according to the comparison result, and the information signal amplitude measurement circuit is read from the optical recording medium by an optical pickup and subjected to amplification processing. An input means for inputting a signal, and a peak comparison means for comparing an information signal input by the input means with a variable reference value for peak detection; A peak counter for performing a counting operation in accordance with a comparison result of the peak comparison means; a peak reference value updating means for supplying a variable reference value corresponding to the count value output of the peak counter to the peak comparison means; A bottom comparison unit that compares an information signal input by the input unit with a variable reference value for bottom detection, a bottom counter that performs a counting operation according to a comparison result of the bottom comparison unit, and the bottom counter The amplitude value of the information signal is calculated using a reference value updating means for supplying a reference value corresponding to the output to the bottom comparing means, and a count value output from the counter for the peak and the counter for the bottom. And an arithmetic means.

According to the information signal amplitude measuring circuit of the present invention, the information signal read from the optical recording medium is compared with the variable reference value by the peak comparing means and the bottom comparing means, and the comparison result is used as the peak counter and the bottom counter. While counting with the counter, the count value output is used to update the variable reference value, and it is fed back to the peak comparison means and the bottom comparison means so as to follow the maximum amplitude value of the information signal. The amplitude of the information signal read from the optical recording medium can be correctly measured regardless of the signal level.
In the information signal amplitude measuring circuit of the present invention, when a momentary abnormal value occurs in the information signal input by the input unit, the correcting unit corrects the count values of the peak counter and the bottom counter caused by the abnormal value. Therefore, it is possible to correct an abnormal amplitude such as noise and perform a correct amplitude measurement. This correction means can be realized, for example, by using a simple means that periodically reverses the count operation of the peak counter and the count operation of the bottom counter by a predetermined count value.

In the optical information recording and / or reproducing apparatus of the present invention equipped with the information signal amplitude measuring circuit as described above, the amplitude value measured accurately can be notified and used for adjustment work of the optical pickup, etc. Automatic adjustment of the signal amplitude and the like can be performed accurately, contributing to the improvement of the reliability and reproduction capability of the player and the drive, and further the effect of adjusting and evaluating the optical pickup more accurately.
Further, in the optical information recording and / or reproducing apparatus of the present invention equipped with the information signal amplitude measuring circuit as described above, the accurately measured amplitude value is compared with a predetermined set value, and according to the comparison result. The gain of the high-frequency amplifier circuit can be controlled, the gain of the read signal amplitude can be appropriately controlled, high-quality information output can be performed, and the value of the apparatus can be increased.

In order to achieve the above object, the present invention provides a peak detection circuit used in an information signal amplitude measurement circuit that binarizes a high-frequency information signal read from an optical disk by an optical pickup and amplified as a non-inverting input. And a counter for counting up the binarized signal as a clock, and a D / A converter for D / A converting the value of the counter, and the D / A converted analog signal is input to the inverting input of the comparator. I tried to do it.
Further, in the bottom detection circuit used for the information signal amplitude measurement circuit, a high-frequency information signal read from the optical disc by the optical pickup and amplified is used as an inverting input to binarize the binarized signal. A counter that counts down as a clock and a D / A converter that D / A converts the value of the counter are provided, and the D / A converted analog signal is used as a non-inverting input of the comparator.
The information signal amplitude measurement circuit includes the above-described peak detection circuit and bottom detection circuit that receive the amplified high-frequency information signal read from the optical disc by the optical pickup and includes a counter built in each of them. And a subtractor for calculating the difference between the values, and the output of the subtractor is used as the amplitude of the RF information signal.

In the optical disk device of the present invention, an optical pickup for reading information from the optical disk, a high-frequency amplifier circuit that amplifies and calculates a high-frequency signal read by the optical pickup to generate a high-frequency information signal, and the high-frequency signal The information signal amplitude measuring circuit described above for processing the information signal generated by the amplifier circuit, informing the adjustment operator of the optical pickup of the amplitude value measured by the information signal amplitude measuring circuit, and the characteristics of the optical pickup Assisted in optimal adjustment.
Another optical disk apparatus of the present invention is an optical pickup for reading information from an optical disk, and a variable gain type high frequency signal that amplifies and calculates a high frequency signal read by the optical pickup to generate a high frequency information signal. Compare the amplitude value measured by the amplification circuit, the above-described information signal amplitude measurement circuit that processes the information signal generated by the high-frequency amplification circuit, and the information signal amplitude measurement circuit with a predetermined set value, And a control system for controlling the gain of the variable gain type high frequency amplifier circuit according to the result.

FIG. 1 is a block diagram showing Example 1 of the present invention, and shows a schematic configuration of a DVD system as an example of an optical disk apparatus using an information signal amplitude measuring circuit according to an embodiment of the present invention.
In this DVD system, a disc (optical disc) 111 as a recording medium has binarized digital data recorded on a track and is driven to rotate by a disc motor 113. The disk motor 113 is driven by a disk motor control circuit 124 and a driver 123.
An optical pickup 112, which is a signal extraction means for reading information data recorded on the disk 111, irradiates a track on the rotating disk 111 with a laser beam and reflects it back from the track on the disk 111. Information data is read by detecting a change in the amount of light coming and output as an electrical signal. The information signal read by the optical pickup 112 is, for example, a high frequency (RF) analog signal of several MHz.
A variable gain RF amplifier (head amplifier) 115 calculates and amplifies the output signal of the optical pickup 112, and outputs a focus error signal, a tracking error signal, an RF signal (information signal), and the like. The RF amplifier 115 is controlled by an automatic gain control (AGC) loop so that the RF signal output has a predetermined constant amplitude suitable for signal processing in the subsequent stage.
That is, the RF signal (information signal) output from the RF amplifier 115 is first sent to the RF amplitude detection circuit 126, and the RF amplitude is detected.
The system controller 125 checks the amplitudes of the RF signals of the various disks targeted by the DVD system, sets the gain of the RF amplifier 115 so that this value becomes the reference level held inside, and sets the RF signal amplitude. Control to be constant.

The RF signal output from the RF amplifier 115 is sliced (binarized) by the data slice circuit 118, and this binarized signal is sent to the synchronization signal separation circuit 119, where it is synchronized with the binarized signal. A clock PLCK is generated and demodulated data DATA is obtained.
The clock PLCK and the demodulated data DATA are sent to the error correction circuit 120, where the data is written in the correction RAM 121 and subjected to correction processing. Then, in the case of a DVD movie, it is sent to the MPEG video decoder & audio decoder processing circuit 122. In the case of a DVD-ROM drive, it is sent to the data buffer 122.
Further, in the optical disk device intended for adjustment / evaluation of the pickup 112, the data slice circuit 118 may be omitted thereafter.
The servo system signals (focus error signal and tracking error signal) output from the RF amplifier 115 are input to the driver 117 via the servo control circuit 116, and the actuator (focus) of the optical pickup 112 is output by the driver 117 output.・ Drive actuators and tracking actuators.
The feed motor 114 drives a sliding actuator for moving the optical pickup 112 in the disk radial direction.

FIG. 2 is a block diagram showing an example of the RF amplitude detection circuit 126 shown in FIG.
As shown in FIG. 2, the RF amplitude detection circuit 126 of the present embodiment includes a first analog comparator (peak comparison means) 131, a peak up counter 132, and a first D / A converter (peak reference value update means) 133. , A second analog comparator (bottom comparison means) 134, a bottom up counter 135, a second D / A converter (bottom reference value update means) 136, and a digital subtractor (calculation means) 137.
3 is a waveform diagram for explaining an example of the operation of the RF amplitude detection circuit shown in FIG. 2, FIG. 3 (a) shows a typical waveform of the RF signal, and FIG. 3 (b) shows detection of the detection circuit. The waveform is shown.

The detection operation according to this embodiment is performed as follows.
First, the RF signal enters the non-inverting input of the first analog comparator 131 and is compared with the output of the first D / A converter 133 entering the inverting input.
The comparison result of the first analog comparator 131 is input as the count clock of the peak up counter 132. When the output of the first analog comparator 131 changes from logic 0 to logic 1, the value of the peak up counter 132 is incremented by one. The
Further, the first D / A converter 133 always converts the value of the peak up counter 132 to analog, and inputs it to the inverting input of the first analog comparator 131 as a peak reference variable reference value.
That is, when the RF signal crosses the analog level generated by D / A converting the value held by the peak up counter 132 upward, the first analog comparator 131 generates a count pulse to the peak up counter 132. The value of the peak up counter 132 is incremented by one.
By such an operation, the analog level to be compared with the RF signal in the first analog comparator 131 gradually increases. Finally, when the analog level to be compared is slightly higher than the maximum value of the RF signal, the peak up counter 132 The count-up operation is not performed, and at that time, the peak up counter 132 holds a value approximately the same as the peak level of the RF signal as a digital value, and the first D / A converter 133 holds it as an analog value.

On the other hand, the RF signal also enters the inverting input of the second analog comparator 134 and is compared with the output of the second D / A converter 136 that enters the non-inverting input.
The comparison result of the second analog comparator 134 is input as the count clock of the bottom down counter 135. When the output of the second analog comparator 134 changes from logic 0 to logic 1, the value of the bottom down counter 135 is -1.
Further, the second D / A converter 136 always converts the value of the bottom down counter 135 to analog, and inputs it to the non-inverting input of the second analog comparator 134 as a variable reference value for bottom detection.
That is, when the RF signal crosses downward the analog level generated by D / A converting the value held by the bottom down counter 135, the second analog comparator 134 generates a count pulse to the bottom down counter 135. The value of the bottom down counter 135 is decremented by -1.

By such an operation, the analog level to be compared with the RF signal in the second analog comparator 134 is gradually reduced. Finally, when the analog level to be compared is slightly lower than the minimum value of the RF signal, the bottom down counter 135 The countdown operation is not performed, and at that time, the bottom down counter 135 holds a value almost the same as the bottom level of the RF signal as a digital value, and the second D / A converter 136 holds it as an analog value.
The digital subtractor 137 can calculate the RF amplitude data 138 by calculating the difference value between the latest peak data and bottom data detected as described above. The function of the digital subtractor 137 can also be realized by subtraction processing using time division of an adder / subtracter built in the system controller 125.

Next, Example 2 of the present invention will be described. The overall configuration shown in FIG. 1 is common to the second embodiment.
FIG. 4 shows an example of the waveform of the RF information signal when the disk 111 is damaged or the amplitude varies. Waveforms indicated by A and B in the figure are generated instantaneously corresponding to the scratched portion of the disk 111, or generated due to external noise. Further, the RF signal amplitude is small on the right side of each of the waveforms A and B.
If the above-described RF amplitude detection circuit 126 is simply used in a state where there are these abnormal values and amplitude fluctuations, there is a possibility that correct results of peak data and bottom data cannot be obtained.
Accordingly, a second embodiment in which a function (correcting means) that does not respond to an instantaneously generated abnormal value signal and responds to amplitude fluctuations caused by the reproduction position or rotation of the disc will be described below.

FIG. 5 is a block diagram showing an example of the RF amplitude detection circuit 126 in the second embodiment.
As shown in FIG. 5, the RF amplitude detection circuit 126 according to the second embodiment includes a first clock generator 141, a second clock generator 142, a first count controller 143, a first analog comparator 145, and a peak up counter 144. , First D / A converter 146, second analog comparator 147, second count controller 148, bottom up counter 149, second D / A converter 150, and digital subtractor 151.
Here, the first clock generator 141 generates a clock having a period similar to that of the RF signal, and the second clock generator 142 generates a clock having a period 10 times longer than the period of the first clock generator 141. It is what happens.
FIG. 6 shows a detection waveform of the RF amplitude detection circuit shown in FIG.

The detection operation in the present embodiment is performed as follows.
First, the RF signal enters the non-inverting input of the first analog comparator 145 and is compared with the output of the first D / A converter 146 entering the inverting input.
The comparison result of the first analog comparator 145 is input to the first count controller 143, and logically calculated by the first count controller 143 together with the output of the first clock generator 141 and the output of the second clock generator 142, for peak use The counter 144 is controlled. The value of the peak counter 144 is always sent to the first D / A converter 146 and D / A converted.
The output of the second clock generator 142 may be generated by dividing the output of the first clock generator 141.

The peak counter 144 is controlled by the first count controller 143 as follows.
First, when the output of the first analog comparator 145 changes from logic 0 to logic 1, it is stored, and when the output of the first clock generator 141 that generates a clock having the same period as the RF signal changes, the peak The counter 144 is incremented by 1, and the memory in which the output of the first analog comparator 145 changes from logic 0 to logic 1 is erased.
In the absence of this storage, the peak counter 144 is not incremented by one even if the output of the first clock generator 141 changes.
Note that the output of the first clock generator 141 serves to convey the count timing of the peak counter 144. Only when the output of the first clock generator 141 changes from logic 0 to logic 1, the peak counter 144 is used. May count. Further, the peak counter 144 may perform the counting operation only when the logic 1 changes to the logic 0.

Further, when the output of the second clock generator 142 that generates a clock having a cycle longer than 10 times the cycle of the first clock generator 141 changes, the peak counter 144 is preferentially decremented by -1. That is, when the RF signal crosses an analog level generated by D / A converting the value held by the peak up counter 144 upward, the first clock generator 141 counts up the peak counter 144.
Regardless of the magnitude of the RF signal, it is periodically counted down with a change in the output of the second clock generator 142.
Note that the output of the second clock generator 142 serves to convey the countdown timing of the peak counter 144, and only when the output of the second clock generator 142 changes from logic 0 to logic 1, May count down. The peak counter 144 may count down only when the logic 1 changes to the logic 0.

By such an operation, the analog level to be compared with the RF signal in the first analog comparator 145 is gradually increased, and when the analog level to be compared slightly exceeds the maximum value of the RF signal, the count-up operation of the peak counter 144 is At that time, the peak counter 144 holds a value almost the same as the peak level of the RF signal as a digital value, but is periodically -1 by the output of the second clock generator 142. The peak level of the RF signal will fall again, and a count-up operation will occur again.
Therefore, the value of the peak counter 144 repeats +1 and −1 around the peak level of the RF signal. When the peak level of the RF signal decreases due to factors such as the rotation of the disk, the count-down operation increases more than the count-up operation, and the value of the peak counter 144 decreases.
The speed of the decrease is adjusted by the period of the output of the second clock generator 142 depending on how much the response speed is obtained with respect to the fluctuation of the peak level of the RF signal.

Further, the RF signal is input to the inverting input of the second analog comparator 147 and compared with the output of the second D / A converter 150 that is input to the non-inverting input.
The comparison result of the second analog comparator 147 is input to the second count controller 148, and logically calculated by the second count controller 148 together with the output of the first clock generator 141 and the output of the second clock generator 142, The counter 149 is controlled. The value of the bottom counter 149 is always sent to the second D / A converter 150 and D / A converted.

The bottom counter 149 is controlled by the second count controller 148 as follows.
First, when the output of the second analog comparator 147 changes from logic 0 to logic 1, it is stored, and when the output of the first clock generator 141 that generates a clock having the same period as the RF signal changes, The counter 149 is decremented by 1, and the memory in which the output of the second analog comparator 147 changes from logic 0 to logic 1 is erased.
When there is no memory, even if the output of the first clock generator 141 changes, the bottom counter 149 is not decremented by 1.
The output of the first clock generator 141 serves to transmit the count timing of the bottom counter 49. Only when the output of the first clock generator 141 changes from logic 0 to logic 1, the bottom counter 149 is used. May count. Further, the bottom counter 149 may perform the counting operation only when the logic 1 changes to the logic 0.

When the output of the second clock generator 142 changes, the bottom counter 149 is preferentially incremented by one. That is, when the RF signal crosses the analog level generated by D / A converting the value held by the bottom up counter 149 downward, the first clock generator 141 counts down the bottom counter 149.
Regardless of the magnitude of the RF signal, it is periodically counted up as the output of the second clock generator 142 changes.
The output of the second clock generator 142 serves to convey the count-up timing of the bottom counter 149, and only when the output of the second clock generator 142 changes from logic 0 to logic 1, 149 may count up.
Further, the bottom counter 149 may count up only when the logic 1 changes to the logic 0.

By such an operation, the analog level to be compared with the RF signal in the second analog comparator 147 gradually decreases, and when the analog level to be compared is slightly lower than the minimum value of the RF signal, the count-down operation of the bottom counter 149 is performed. At that time, the bottom counter 149 holds a value almost the same as the bottom level of the RF signal as a digital value. However, since it is periodically incremented by the output of the second clock generator 142, the bottom of the RF signal The level will be exceeded again and a countdown action will occur again.
Therefore, the value of the bottom counter 149 repeats +1 and −1 around the bottom level of the RF signal.
When the bottom level of the RF signal increases due to factors such as disk rotation, the count-up operation increases more than the count-down operation, and the value of the bottom counter 149 increases. The speed of this increase is adjusted by the period of the output of the second clock generator 142 depending on how much the response speed is obtained with respect to the fluctuation of the bottom level of the RF signal.
In the second embodiment, the digital subtractor 151 calculates the RF amplitude data 152 by calculating the difference value between the latest peak data and the bottom data, as in the digital subtractor 137 of the first embodiment.

FIG. 7 is a block diagram showing in detail the configuration of a part of the RF amplitude detection circuit according to the second embodiment. The first count controller 143, the peak counter 144, the second count controller 148, and the bottom part shown in FIG. 3 is a specific circuit example of a counter 149. In FIG. 7, the same reference numerals are assigned to configurations common to the peak detection side and the bottom detection side.
FIG. 8 is a timing chart showing an operation example of the circuit shown in FIG.

Hereinafter, a detailed operation example will be described based on these drawings.
First, on the peak detection side, when the output of the first analog comparator 145 changes from logic 0 to logic 1, the output of the first D-type flip-flop 171 becomes logic 1, and the first clock generator 141 to be generated next. The output of the second D-type flip-flop 172 becomes logic 1 at the rising edge of the output CLK1. Then, the count permission input of the peak counter 180 becomes logic 1 through the OR gate 176, and the count operation of the peak counter 180 is permitted. If the output of the inverter 181 is logic 1, the peak counter at the falling edge of CLK1. 180 is incremented by one.
The first D-type flip-flop 171 is reset through the inverter 173 at the rising edge of CLK1, the output returns to logic 0, and the next output of the first analog comparator 145 is prepared for the change from logic 0 to logic 1.

In addition, when the output of the second clock generator 142 that generates a clock having a cycle longer than 10 times the cycle of the first clock generator 141 changes from logic 0 to logic 1, the next rising edge of CLK1 occurs. The output of the third D-type flip-flop 174 becomes logic one. Then, the count direction input of the peak counter 180 becomes logic 0 through the AND gate 179 and the inverter 181, and the count operation of the peak counter 180 is changed in the down direction. At the same time, the count operation is permitted through the OR gate 176, and the peak counter 180 is decremented by -1 at the next falling edge of CLK1.
Further, at the next rising edge of CLK1, the output of the fourth D-type flip-flop 175 becomes logic 1, and the output of the AND gate 179 becomes logic 0 through the inverter 178. Return the count operation to the up direction. At the same time, the permission of the count operation is canceled through the OR gate 176.

Thus, when the rising edge of the output of the first analog comparator 145 occurs, the peak counter 180 counts up in synchronization with the output of the first clock generator 141, and the output of the second clock generator 142 is output. When the rising edge occurs, the peak counter 180 counts down in synchronization with the output of the first clock generator 141.
Since the period of the first clock generator 141 is approximately the same as that of the RF signal, the count-up operation of the peak counter 180 is performed quickly and follows the rise in the peak of the RF signal. However, suddenly generated noise is merely incremented by +1 at most, so it hardly follows the peak rise due to noise.
On the other hand, since the output cycle of the second clock generator 142 is 10 times longer than that of the RF signal, the countdown operation of the peak counter 180 is slow and maintains a state that is not much different from the peak level of the RF signal. The count value slightly increased by noise can be returned to the peak level of the true RF signal.

Further, the circuit on the bottom detection side has a configuration in which the inverter 181 on the peak detection side is eliminated.
Accordingly, when the rising edge of the output of the second analog comparator 147 occurs, the bottom counter 180 counts down in synchronization with the output of the first clock generator 141, and the output of the second clock generator 142 increases. When an edge occurs, the peak counter 180 counts up in synchronization with the output of the first clock generator 141.
Since the period of the first clock generator 141 is approximately the same as that of the RF signal, the count-down operation of the bottom counter 180 is performed quickly and follows the bottom of the RF signal. However, suddenly generated noise is only followed by a count value of at most −1, so it hardly follows the bottom drop due to noise.
On the other hand, the output cycle of the second clock generator 142 is 10 times longer than that of the RF signal, so the count-up operation of the bottom counter 180 is slow and maintains a state that is not much different from the bottom level of the RF signal. The count value slightly reduced by noise can be returned to the bottom level of the true RF signal.
Note that the logic gates 174, 175, 177, 178, and 179 shown in FIG. 7 have the same configuration and are functionally the same in each of the peak detection circuit and the bottom detection circuit, and thus can be shared.

Next, Embodiment 3 of the present invention will be described. The overall configuration shown in FIG. 1 is common to the second embodiment.
FIG. 9 is a block diagram showing an example of the RF amplitude detection circuit 126 in the third embodiment.
The RF amplitude detection circuit 126 of the third embodiment is obtained by replacing the digital amplitude subtraction circuit 151 with an analog subtraction circuit 61 with respect to the RF amplitude detection circuit 126 of the second embodiment.
The inputs of the analog subtraction circuit 161 are the output of the first D / A converter 146 and the output of the second D / A converter 150.
Such a configuration is advantageous particularly when the system controller has an analog input interface.
Since other configurations and effects are the same as those in the second embodiment, description thereof is omitted.

Although the embodiments of the present invention have been described above, the specific circuit configuration and numerical values of the embodiments are merely examples, and the present invention is not limited to the configurations of the embodiments. For example, as long as the function of the present invention can be realized, the combination of the circuit elements described in each drawing can be changed. In addition, numerical values such as a clock used for the count operation can be appropriately changed in accordance with necessary operation characteristics.
In the above-described embodiments, the information signal amplitude measurement circuit has been mainly described. However, as a function of the optical disk device, a device including a notification device that notifies the amplitude value measured by the information signal amplitude measurement circuit, or an information signal The optical disk may be provided with a control device that compares the amplitude value measured by the amplitude measurement circuit with a predetermined set value and controls the gain of the high-frequency amplifier circuit according to the comparison result. By applying the present invention to an apparatus, the functions of the present invention can be used more effectively.
The present invention can also be widely applied to apparatuses that handle optical recording media other than optical disks.

1 is a block diagram illustrating an optical disc device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of an RF amplitude detection circuit provided in the optical disc apparatus shown in FIG. 1. It is explanatory drawing which shows the detection waveform of RF amplitude detection circuit shown in FIG. It is explanatory drawing which shows the abnormal waveform which arose in RF information signal. It is a block diagram which shows the structure of the RF amplitude detection circuit provided in the optical disk apparatus of Example 2 of this invention. It is explanatory drawing which shows the detection waveform of RF amplitude detection circuit shown in FIG. FIG. 6 is a block diagram showing in detail the configuration of a part of the RF amplitude detection circuit shown in FIG. 5. 8 is a timing chart illustrating an operation example of the circuit illustrated in FIG. 7. It is a block diagram which shows the structure of the RF amplitude detection circuit provided in the optical disk apparatus of Example 3 of this invention. It is a block diagram which shows the conventional optical disk apparatus. It is a block diagram which shows the structure of the RF amplitude detection circuit provided in the optical disk apparatus shown in FIG. It is explanatory drawing which shows the detection waveform of RF amplitude detection circuit shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 111 ... Optical disk, 112 ... Pickup, 125 ... System controller, 126 ... RF amplitude detection circuit, 131 ... 1st analog comparator, 132 ... Peak up counter, 133 ... 1st D / A converter, 134 2nd analog comparator, 135 up counter for bottom, 136 2nd D / A converter, 137 digital subtractor.

Claims (18)

Input means for inputting a high-frequency information signal read from the optical recording medium by an optical pickup and amplified;
Peak comparison means for comparing the information signal input by the input means with a variable reference value for peak detection;
A peak counter that performs a counting operation according to the comparison result of the peak comparison means;
Peak reference value update means for supplying a variable reference value corresponding to the count value output of the peak counter to the peak comparison means;
A bottom comparison means for comparing the information signal input by the input means with a variable reference value for bottom detection;
A bottom counter that performs a counting operation according to a comparison result of the bottom comparison means;
A bottom reference value update means for supplying a variable reference value corresponding to the output of the bottom counter to the bottom comparison means;
An arithmetic means for calculating an amplitude value of the information signal using a count value output by the peak counter and the bottom counter;
An information signal amplitude measuring circuit comprising:   And a correction unit that corrects the count values of the peak counter and the bottom counter caused by the abnormal value when an instantaneous abnormal value is generated in the information signal input by the input unit. The information signal amplitude measuring circuit according to claim 1.   3. The information signal amplitude measuring circuit according to claim 2, wherein the correcting means is means for periodically reversing the counting operation of the peak counter and the counting operation of the bottom counter by a predetermined count value.   First clock generating means for generating a first clock for determining the timing for executing the counting operation of the peak counter and the bottom counter, and a second clock for determining the timing for executing the correcting operation of the correcting means are generated. 3. The information signal amplitude measuring circuit according to claim 2, further comprising a second clock generating means, wherein a period of the second clock is larger than a period of the first clock.   5. The information signal amplitude measuring circuit according to claim 4, wherein the second clock has a period 10 times that of the first clock.   5. The information signal amplitude measuring circuit according to claim 4, wherein the second clock is a divided signal of the first clock. An optical pickup for reading a signal from the optical recording medium;
A high frequency amplifier circuit for amplifying and calculating a high frequency signal read by the optical pickup to generate a high frequency information signal;
An information signal amplitude measuring circuit for measuring the amplitude of the information signal generated by the high-frequency amplifier circuit;
A notification device for notifying the amplitude value measured by the information signal amplitude measurement circuit,
The information signal amplitude measurement circuit includes:
Input means for inputting a high-frequency information signal read from the optical recording medium by an optical pickup and amplified;
Peak comparison means for comparing the information signal input by the input means with a variable reference value for peak detection;
A peak counter that performs a counting operation according to the comparison result of the peak comparison means;
Peak reference value update means for supplying a variable reference value corresponding to the count value output of the peak counter to the peak comparison means;
A bottom comparison means for comparing the information signal input by the input means with a variable reference value for bottom detection;
A bottom counter that performs a counting operation according to a comparison result of the bottom comparison means;
A bottom reference value update means for supplying a variable reference value corresponding to the output of the bottom counter to the bottom comparison means;
An arithmetic means for calculating an amplitude value of the information signal using a count value output by the peak counter and the bottom counter;
An optical information recording and / or reproducing apparatus comprising:   And a correction unit that corrects the count values of the peak counter and the bottom counter caused by the abnormal value when an instantaneous abnormal value is generated in the information signal input by the input unit. The optical information recording and / or reproducing apparatus according to claim 7.   9. The optical information recording and / or reproducing apparatus according to claim 8, wherein the correcting means is means for periodically reversing the counting operation of the peak counter and the counting operation of the bottom counter by a predetermined count value.   First clock generating means for generating a first clock for determining the timing for executing the counting operation of the peak counter and the bottom counter, and a second clock for determining the timing for executing the correcting operation of the correcting means are generated. 9. The optical information recording and / or reproducing apparatus according to claim 8, further comprising a second clock generating means, wherein a period of the second clock is larger than a period of the first clock.   11. The optical information recording and / or reproducing apparatus according to claim 10, wherein the second clock has a period 10 times that of the first clock.   11. The optical information recording and / or reproducing apparatus according to claim 10, wherein the second clock is a frequency-divided signal of the first clock. An optical pickup for reading a signal from the optical recording medium;
A variable gain type high frequency amplifier circuit that amplifies and calculates a high frequency signal read by the optical pickup to generate a high frequency information signal;
An information signal amplitude measuring circuit for measuring the amplitude of the information signal generated by the high-frequency amplifier circuit;
A control device that compares the amplitude value measured by the information signal amplitude measurement circuit with a predetermined set value and controls the gain of the high-frequency amplifier circuit according to the comparison result;
The information signal amplitude measurement circuit includes:
Input means for inputting a high-frequency information signal read from the optical recording medium by an optical pickup and amplified;
Peak comparison means for comparing the information signal input by the input means with a variable reference value for peak detection;
A peak counter that performs a counting operation according to the comparison result of the peak comparison means;
Peak reference value update means for supplying a variable reference value corresponding to the count value output of the peak counter to the peak comparison means;
A bottom comparison means for comparing the information signal input by the input means with a variable reference value for bottom detection;
A bottom counter that performs a counting operation according to a comparison result of the bottom comparison means;
A bottom reference value update means for supplying a variable reference value corresponding to the output of the bottom counter to the bottom comparison means;
An arithmetic means for calculating an amplitude value of the information signal using a count value output by the peak counter and the bottom counter;
An optical information recording and / or reproducing apparatus comprising:   And a correction unit that corrects the count values of the peak counter and the bottom counter caused by the abnormal value when an instantaneous abnormal value is generated in the information signal input by the input unit. The optical information recording and / or reproducing apparatus according to claim 13.   15. The optical information recording and / or reproducing apparatus according to claim 14, wherein the correcting means is means for periodically reversing the counting operation of the peak counter and the counting operation of the bottom counter by a predetermined count value.   First clock generating means for generating a first clock for determining the timing for executing the counting operation of the peak counter and the bottom counter, and a second clock for determining the timing for executing the correcting operation of the correcting means are generated. 16. The optical information recording and / or reproducing apparatus according to claim 15, further comprising a second clock generating means, wherein a period of the second clock is larger than a period of the first clock.   17. The optical information recording and / or reproducing apparatus according to claim 16, wherein the second clock has a period 10 times that of the first clock.   17. The optical information recording and / or reproducing apparatus according to claim 16, wherein the second clock is a divided signal of the first clock.

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