JP2006252282A - Data processing module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the destruction of transmission data and the overwrite of reception data from being caused by the rewrite of a CPU with respect to a buffer in a standby state. <P>SOLUTION: This data processing module connected to a multiple master type network includes: a message buffer 3 which is sectioned into a prescribed number of buffers, to which an address is imparted to each buffer, and which can store a message in each buffer; preparation information holding parts 6 provided for the prescribed number corresponding to each buffer for holding preparation information for reporting whether or not the transmission or reception is ready; and masking circuit parts 7 provided for the prescribed number corresponding to each buffer for masking the input of write signals from the CPU to the message buffer 3 when the preparation information indicates that the transmission or the reception is ready. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data processing module.

  In recent years, multi-master communication protocols have attracted attention as communication protocols. Multi-master communication protocol is characterized in that when the bus is released, any of a plurality of communication nodes connected to the bus can transmit data on the bus, and the system is highly flexible. There is. Such a multi-master communication protocol is used as a serial communication protocol between ECUs (electronic control units) in an automobile, and can be easily increased or decreased in communication nodes. In addition to the automobile field, it is also promising as a communication protocol in fields such as FA (Factory Automation), ships, and medical equipment.

  FIG. 8 is a block diagram schematically showing the configuration of a conventional CAN. The CAN modules 11, 1 n, and 16 are communication nodes, and can be connected to the CAN bus via the CAN transceiver 60. The CAN bus constitutes a subnetwork. Each CAN module 11, 1 n, 16 can send and receive messages to and from the CPU 51 via the CPU I / F (interface) 40. The CAN module 19 can selectively receive only messages.

  The CAN modules 11, 1 n, and 16 include a message handling unit 2, a message buffer 3, a CAN protocol transmission layer 4, and a mask set 5. The message handling unit 2 performs a process of storing the received message in the message buffer 3 (a buffer at a predetermined address thereof), a process of selecting a message that is a transmission candidate from the messages stored in the message buffer 3, and the like. The message buffer 3 is a buffer capable of storing a predetermined number of messages, and is divided into a predetermined number of buffers, and an address is given to each buffer (see FIG. 9). The message is information arranged in the order of an identifier (ID), a control field (control segment), and a message body (see FIG. 9). In addition to the message, each buffer stores preparation information (RDY) indicating whether the message handling unit 2 is ready for transmission or reception (see FIG. 9). The preparation information (RDY) indicates that the message handling unit 2 is ready for transmission or reception when the level is “1”, and is ready for transmission or reception for the message handling unit 2 when the level is “0”. Indicates that it has not been completed. A clock signal for synchronizing data and signals is inverted and input to the message buffer 3 (see FIG. 9). The CAN protocol transmission layer 4 transmits / receives data to / from the CAN transceiver according to the CAN protocol. The mask set 5 is used when a predetermined part (for example, a part of ID) of a message is masked.

JP-A 61-195453

  However, in the conventional CAN module, for example, even when the preparation information (RDY # n) in the buffer at address #n is level “1”, the write (for data) from the CPU to the buffer at address #n is performed. When a signal is input (accessed by the CPU), data (message) can be written by the CPU (see FIG. 10). For this reason, when the CPU erroneously writes new data to the buffer (overwriting), there is a risk of transmitting the new data written at the time of transmission, and based on erroneous received data. There was a risk of misjudgment of receiving and storing. In other words, even in a buffer that is in a ready state (preparation complete) and in a state in which transmission or reception can be controlled by the message handling unit, the CPU can freely rewrite, so the message handling unit tries to perform transmission or reception processing. There is a problem that the rewriting by the CPU is performed even when the data is transmitted, and the transmission data is destroyed or the reception data is overwritten.

  In the conventional CAN module, for example, when a write signal (for RDY) is input from the CPU to the preparation information (RDY # n) in the buffer at the address #n, the rewriting by the CPU is performed at any timing. However, it was possible (see FIG. 11 for an example in which RDY is rewritten from 1 to 0). Therefore, when the timing conflicts with the transmission load or reception storage operation by the message handling unit, there is a possibility that the correspondence between the preparation information (RDY) in the buffer and the data (message) cannot be maintained.

  The above problem occurs because the message output from the message buffer to the CAN bus and the message writing from the CPU to the message buffer are performed asynchronously.

  In a first aspect of the present invention, a data processing module connected to a multi-master network is partitioned into a predetermined number of buffers, an address is given to each buffer, and a message is sent to each buffer. A message buffer that can be stored, a predetermined number corresponding to each buffer, a preparation information holding unit that holds preparation information for informing whether transmission or reception is ready, and the buffer A mask circuit unit that masks the input of a write signal from the CPU to the message buffer when the preparation information indicates that the preparation is ready for transmission or reception. The write signal is a signal transmitted from the CPU and the buffer Characterized in that it is a signal for writing data into.

  In a second aspect of the present invention, a data processing module connected to a multi-master network is partitioned into a predetermined number of buffers, an address is given to each buffer, and a message is sent to each buffer. A message buffer that can be stored, a predetermined number corresponding to each buffer, a preparation information holding unit that holds preparation information for informing whether transmission or reception is ready, and message handling A second mask circuit unit that masks the input of a second write signal from the CPU to each of the preparation information holding units when receiving a state signal from the unit, A signal sent from the message handling unit before the transmission load or reception storage A signal indicating a state in which any or all of the message buffers are being accessed, and the second write signal is a signal transmitted from the CPU and stored in the preparation information holding unit relating to a predetermined address. It is a signal for writing preparation information.

  In a third aspect of the present invention, a data processing module connected to a multi-master network is partitioned into a predetermined number of buffers, an address is given to each buffer, and a message is sent to each buffer. A message buffer that can be stored, a predetermined number corresponding to each buffer, a preparation information holding unit that holds preparation information for informing whether transmission or reception is ready, and the preparation A predetermined number is provided corresponding to each information holding unit, and when receiving the second state signal related to the corresponding address from the message handling unit, the preparation information holding unit related to the corresponding address is received from the CPU. A third mask circuit portion for masking the input of the second write signal of The state signal 2 is a signal transmitted from the message handling unit, and is a signal indicating a state in which the buffer associated with a predetermined address of the message buffer is being accessed in order to perform transmission load or reception storage, The second write signal is a signal transmitted from the CPU and is a signal for writing the preparation information in the preparation information holding unit related to a predetermined address.

  In a fourth aspect of the present invention, a data processing module connected to a multi-master network includes a plurality of buffers each having an area in which an ID is set and an area in which message data corresponding to the ID is written. A message buffer, a preparation information holding circuit provided corresponding to the plurality of buffers, in which information indicating completion of preparation is written in a buffer for which ID setting has been completed among the plurality of buffers, and the preparation information holding A message handling unit that transmits message data written in the message buffer indicating that the circuit is ready on the bus; and the CPU that writes the ID to the message buffer and writes the ready information to the preparation information holding circuit And the preparation information holding circuit indicates completion of preparation. Sometimes, characterized in that it comprises a first gate circuit for inhibiting the writing of the message data from the CPU.

  According to the present invention (Claim 1-3), since the CPU does not rewrite data by mistake to a buffer at a predetermined address in a message buffer ready for transmission or reception, it is possible to transmit impossible data. , Never receive on the premise of incorrect settings.

  According to the present invention (claims 2 and 4), during the period from the start to the completion of processing (transmission load or reception storage) of the message handling unit, the message handling unit is ready for transmission or reception. When it is shown that the data is ready (level “1”), data can be safely read from and written to the corresponding buffer.

  According to the present invention (Claims 3 and 5), writing of the preparation information (RDY) of the address to be transmitted or received can be individually prohibited, so that the data relating to the address to be transmitted or received Even when the message handling unit is transmitting or receiving (message), it is possible to write the preparation information (RDY) of an address that is not a target of transmission or reception, and appropriate protection becomes possible.

  According to the present invention (Claims 6 and 7), by adding a gate circuit, it is possible to prevent overwriting of the message buffer by the CPU and to prevent destruction of data being transmitted or received. be able to.

(Embodiment 1)
A data processing module according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram schematically showing a configuration of a CAN device including a CAN module (data processing module) according to Embodiment 1 of the present invention. FIG. 2 is a block diagram schematically showing a detailed configuration of the CAN module (data processing module) according to the first embodiment of the present invention.

  The CAN device 100 is a device in which a CAN module (data processing module), a CPU 51, a RAM 52, and a peripheral circuit 53 are configured in one chip (see FIG. 1).

  The CAN module is a data processing module for processing data, and includes a message handling unit 2, a message buffer 3, a CAN protocol transmission layer 4, a mask set 5, a preparation information holding unit 6, and a mask circuit unit 7. (See FIG. 1 and FIG. 2).

  The message handling unit 2 performs processing for storing a received message in a buffer associated with a predetermined address of the message buffer 3, processing for selecting a message that is a transmission candidate from the messages stored in the message buffer 3, and the like (FIG. 1). reference). Here, the message is information arranged in the order of an identifier (ID), a control field (control segment), and a message body (see FIG. 2). The identifier is an identifier (ID) indicating the message priority. The control field (control segment) is information for designating whether or not it is a transmission request message and the message body length (see FIG. 2).

  The message buffer 3 is a buffer capable of storing a predetermined number of messages (see FIG. 1), and is divided into a predetermined number of buffers (corresponding to a mailbox), and an address is given to each buffer. (See FIG. 2). Each buffer does not store preparation information (RDY) indicating whether the message handling unit 2 is ready for transmission or reception. A clock signal for synchronizing data and signals is inverted and input to the message buffer 3 (see FIG. 2).

  The CAN protocol transmission layer 4 transmits / receives data to / from the CAN transceiver according to the CAN protocol (see FIG. 1).

  The mask set 5 is used when a predetermined part (for example, a part of ID) of a message is masked (see FIG. 1). For example, assuming that the ID is binary 4-bit data and the message with ID 1100 is assigned to the buffer with address #n of the message buffer 3 having the buffers with addresses # 0 to 31, the upper 2 bits are used. By applying a mask, messages of 0000, 0100, and 1000 other than 1100 are used to be stored in the buffer of address #n.

  The preparation information holding unit 6 is a part for holding preparation information (RDY), and an address is assigned corresponding to each buffer (see FIG. 2). Here, the preparation information (RDY) is information for notifying the message handling unit 2 whether or not preparation for transmission or reception has been completed, and is transmitted or received to the message handling unit 2 at the level “1”. The message handling unit 2 is not ready for transmission or reception when the level is “0”. The preparation information (RDY) held in the preparation information holding unit 6 is input to the mask circuit unit 7.

  The mask circuit unit 7 is a circuit unit for masking the input of a write signal (for data) from the CPU 51 to the message buffer 3 when the preparation information (RDY) is being prepared for transmission or reception (level “1”). (See FIG. 2). Here, the write signal is a signal transmitted from the CPU 51 and is a signal for accessing to write data (message) in a buffer at a predetermined address of the message buffer 3. Note that the mask circuit unit 7 can input a write signal (for data) from the CPU 51 to the message buffer 3 when the preparation information (RDY) is not being prepared for transmission or reception (level “0”). To do.

  The peripheral circuit 53 includes, for example, an I / O circuit, is connected to various sensors (not shown) and a display device (not shown) provided outside the CAN device 100, and is an interface between the outside and the inside. I do.

  The CPU 51 performs processing of taking out data from various sensors (not shown) via the I / O and executing desired processing using the RAM 52 and writing data in the message buffer 3 (see FIG. 1). When the CPU 51 performs a process of writing data to the message buffer 3, the CPU 51 outputs a write signal (for data) to the message buffer 3 (see FIG. 2). The CPU 51 retrieves the message written in the message buffer 3 and executes a desired process, and then performs a process of transmitting data to a display device (not shown) connected to the outside via the I / O.

  Next, the operation of the data processing module according to the first embodiment of the present invention will be described. FIG. 3 is a timing chart for explaining the operation of the CAN module (data processing module) according to the first embodiment of the present invention. For example, when the preparation information (RDY # n) of the preparation information holding unit 6 corresponding to the buffer of address #n is level “1”, a write signal (for data) is output from the CPU to the buffer. However, since the output signal of the mask circuit section 7 is at level “0”, data is not written by the CPU (see FIG. 3). When the CPU writes to the buffer of address #n, the level of the preparation information (RDY # n) in the preparation information holding unit 6 is set to “0”, and then from the CPU (for data) When the write signal is output, since the output signal of the mask circuit section 7 is at level “1”, data is written by the CPU.

  According to the first embodiment, when the preparation information (RDY) is level “1”, a write signal (for data) is output from the CPU, and the data is written even if the CPU 51 tries to write data to the corresponding buffer. There is no. In addition, consistency between the preparation information (RDY) of the preparation information holding unit 6 and the data (message) of the corresponding message buffer 3 is guaranteed, and the transmission load or reception storage operation can be performed more normally than in the conventional configuration. it can. Furthermore, the possibility that the message buffer 3 is unnecessarily rewritten due to a program runaway or the like is reduced.

(Embodiment 2)
Next, a data processing module according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram schematically showing a detailed configuration of a CAN module (data processing module) according to the second embodiment of the present invention.

  In the first embodiment described above, the output of the preparation information holding unit 6 and the write signal from the CPU are masked by the mask circuit unit 7 and the rewrite of the message buffer is prohibited even when there is a write request from the CPU. However, the preparation information holding unit 6 can be rewritten by the CPU. Therefore, when the CPU writes “0” in the preparation information holding unit 6 and then outputs a write signal, the message handling unit 2 writes the message data taken from the CAN bus to the message buffer 3 or the message buffer. There is a possibility that the contents of the buffer of the message buffer 3 are overwritten by the CPU during the reading (output) of the message data from 3 to the CAN bus. Therefore, in the data processing module according to the second embodiment of the present invention, when the message handling unit 2 writes message data to the message buffer 3 or reads message data from the message buffer 3, the message buffer 3 by the CPU. Prevents overwriting of data stored in.

  The data processing module according to the second embodiment further includes a second mask circuit unit 20 in addition to the configuration of the data processing module according to the first embodiment. When receiving a state signal from the message handling unit (2 in FIG. 1), the second mask circuit unit 20 masks the input of the write signal (for RDY) from the CPU 51 to each preparation information holding unit 6. It is a circuit part. The signal output from the second mask circuit unit 20 is input to each preparation information holding unit 6. Here, the write signal is a signal transmitted from the CPU 51 and is a signal for accessing to write the preparation information (RDY) in the preparation information holding unit 6 having a predetermined address. The state signal is a signal transmitted from the message handling unit (2 in FIG. 1), and accesses any or all of the message buffers (3 in FIG. 1) to perform transmission load or reception storage. This signal is a logical sum of a transmission load state signal indicating that transmission is being loaded by the OR gate 70 and a reception storage state signal indicating that reception is being stored.

  Next, the operation of the data processing module according to the second embodiment of the present invention will be described. FIG. 5 is a timing chart for explaining the operation of the CAN module (data processing module) according to the second embodiment of the present invention. For example, when the preparation information (RDY) of the preparation information holding unit 6 related to the address #n is level “1” during transmission loading or reception storage, the state signal (level “1”) from the message handling unit ) Is output to the preparation information (RDY) for clearing the preparation information (RDY) of the preparation information holding unit 6 related to the address #n from the CPU (level “0”). Even if the write signal for RDY is output, the output signal of the second mask circuit unit 20 is at the level “0”, so the CPU does not rewrite the preparation information (RDY) (see FIG. 5). The same applies even when the preparation information (RDY # n) of the preparation information holding unit 6 is at level “0”. In other words, no matter what level the preparation information (RDY) of each preparation information holding unit 6 is, when the state signal from the message handling unit is output, the CPU of the preparation information holding unit 6 related to a predetermined address Even if a write signal (for RDY) for clearing the preparation information (RDY) (level “0”) is output, the signal output from the second mask circuit unit 20 is level “0”. The preparation information (RDY) of the predetermined address is not rewritten by the CPU. If a write signal is output from the CPU (for RDY) to each preparation information holding unit 6 when the state signal from the message handling unit is not output, the second mask circuit unit 20 Since the output signal is level “1”, any of the preparation information by the CPU can be rewritten.

  According to the second embodiment, the preparation information (RDY) of each preparation information holding unit 6 by the CPU cannot be cleared (level “0”) during transmission loading or reception reception. The buffer whose (RDY) is level “1” cannot be accessed, and the data in the buffer is not rewritten by the CPU. Therefore, during the period from the start to the completion of the processing (transmission load or reception storage) of the message handling unit, the message handling unit is safe against the buffer in the message buffer whose preparation information (RDY) is level “1”. Can read and write data.

(Embodiment 3)
Next, a data processing module according to the third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram schematically showing a detailed configuration of a CAN module (data processing module) according to the third embodiment of the present invention.

  In addition to the configuration of the data processing module according to the first embodiment, the data processing module according to the third embodiment further includes a third mask circuit unit 30. The third mask circuit unit 30 of the data processing module according to the third embodiment is configured with one mask circuit unit as in the second mask circuit unit (20 in FIG. 4) of the data processing module according to the second embodiment. The preparation information holding unit is not masked, but the preparation information holding unit 6 is individually masked. A write signal (for RDY) from the CPU 51 is input to each third mask circuit unit 30. The third mask circuit unit 30 corresponding to the preparation information holding unit 6 of the address # 0 receives each preparation from the CPU 51 when receiving the state signal related to the address # 0 from the message handling unit (2 in FIG. 1). The input of the write signal (for RDY) to the information holding unit 6 is masked. Similarly, the third mask circuit unit 30 corresponding to the preparation information holding unit 6 of the address #n receives the state signal related to the address #n from the message handling unit (2 in FIG. 1) from the CPU 51. The input of the write signal (for RDY) to each preparation information holding unit 6 is masked. Note that the state signal from the message handling unit in the third embodiment is not a signal that is the logical sum of the transmission load state signal and the reception storage state signal, but an individual transmission load state signal or reception storage state signal corresponding to each address. It is.

  Next, the operation of the data processing module according to the third embodiment of the present invention will be described. FIG. 7 is a timing chart for explaining the operation of the CAN module (data processing module) according to the third embodiment of the present invention. For example, during transmission loading or reception storage, as shown in FIG. 7, first, the preparation information (RDY) of the preparation information holding unit 6 relating to the addresses # 0 and #n is level “1”, and the message handling unit When the state signal at address # 0 outputs level “1” and the state signal at address #n outputs level “0”, the CPU receives address # 0 from the CPU for the preparation information (RDY). Assume that a write signal (for RDY) for setting the preparation information (RDY) of the preparation information holding unit 6 related to #n to level “0” is output. In this case, the preparation information (RDY # 0) of the preparation information holding unit 6 related to the address # 0 is not rewritten because the output signal of the third mask circuit unit 30 related to the address # 0 is level “0”. (Still at level “1”). On the other hand, the preparation information (RDY # n) of the preparation information holding unit 6 related to the address #n has the level “1” because the output signal of the third mask circuit unit 30 related to the address #n is the level “1”. To level “0”.

  According to the third embodiment, writing of the preparation information (RDY) of an address to be transmitted or received can be individually prohibited, so that message handling is performed on data (message) related to an address to be transmitted or received. Even when the unit is transmitting or receiving, it is possible to write the preparation information (RDY) of an address that is not a target of transmission or reception, and appropriate protection is possible.

  As described in the first to third embodiments, the gate circuit (the mask circuit unit 7, the mask circuit unit 7, and the reception storage state signal and the transmission load state signal is received using the conventional preparation information holding unit 6). ) Can be prevented from overwriting the message buffer by the CPU, and data being transmitted or received can be prevented from being destroyed.

It is the block diagram which showed typically the structure of the CAN device containing the CAN module (data processing module) which concerns on Embodiment 1 of this invention. It is the block diagram which showed typically the detailed structure of the CAN module (data processing module) which concerns on Embodiment 1 of this invention. It is a timing chart for demonstrating operation | movement of the CAN module (data processing module) which concerns on Embodiment 1 of this invention. It is the block diagram which showed typically the detailed structure of the CAN module (data processing module) which concerns on Embodiment 2 of this invention. It is a timing chart for demonstrating operation | movement of the CAN module (data processing module) which concerns on Embodiment 2 of this invention. It is the block diagram which showed typically the detailed structure of the CAN module (data processing module) which concerns on Embodiment 3 of this invention. It is a timing chart for demonstrating operation | movement of the CAN module (data processing module) which concerns on Embodiment 3 of this invention. It is the block diagram which showed the structure of the conventional CAN typically. It is the block diagram which showed typically the detailed structure of the conventional CAN module. It is a 1st timing chart for demonstrating operation | movement of the conventional CAN module. It is a 2nd timing chart for demonstrating operation | movement of the conventional CAN module.

Explanation of symbols

2 Message handling unit 3 Message buffer 4 CAN protocol transmission layer 5 Mask set 6 Preparation information (RDY) holding unit 7 Mask circuit unit 11, 1n, 16, 19 CAN module (CAN controller)
20 Second mask circuit section 30 Third mask circuit section 40 CPU I / F
51 CPU
52 RAM
53 peripheral circuit 60 CAN transceiver 70 OR gate 100 CAN device

Claims (7)

In a data processing module connected to a multi-master network,
A message buffer that is partitioned into a predetermined number of buffers, an address is given to each buffer, and a message can be stored for each buffer;
A predetermined number corresponding to each buffer, and a preparation information holding unit for holding preparation information for informing whether transmission or reception is ready;
A mask circuit that masks the input of a write signal from the CPU to the message buffer when a predetermined number is provided corresponding to each buffer and the preparation information indicates that transmission or reception is ready And
With
The data processing module, wherein the write signal is a signal transmitted from the CPU and a signal for writing data in the buffer. A second mask circuit unit that masks input of a second write signal from the CPU to each of the preparation information holding units when receiving a state signal from a message handling unit;
The state signal is a signal transmitted from the message handling unit and is a signal indicating a state in which one of the message buffers is being accessed in order to perform transmission load or reception storage,
2. The data processing module according to claim 1, wherein the second write signal is a signal transmitted from the CPU and is a signal for writing preparation information in the preparation information holding unit relating to a predetermined address. . A predetermined number is provided for each of the preparation information holding units, and the preparation information holding for the corresponding address is received from the CPU when receiving a second state signal related to the corresponding address from the message handling unit. A third mask circuit section for masking the input of the second write signal to the section,
The second state signal is a signal transmitted from the message handling unit and indicating a state in which the buffer associated with a predetermined address of the message buffer is being accessed in order to perform transmission load or reception storage. ,
2. The data processing module according to claim 1, wherein the second write signal is a signal transmitted from the CPU and a signal for writing preparation information in the preparation information holding unit related to a predetermined address. . In a data processing module connected to a multi-master network,
A message buffer that is partitioned into a predetermined number of buffers, an address is given to each buffer, and a message can be stored for each buffer;
A predetermined number corresponding to each buffer, and a preparation information holding unit for holding preparation information for informing whether transmission or reception is ready;
A second mask circuit unit that masks input of a second write signal from the CPU to each of the preparation information holding units when receiving a state signal from a message handling unit;
With
The state signal is a signal transmitted from the message handling unit and indicates a state in which any or all of the message buffers are accessed to perform transmission load or reception storage,
The data processing module, wherein the second write signal is a signal transmitted from the CPU, and is a signal for writing preparation information in the preparation information holding unit related to a predetermined address. In a data processing module connected to a multi-master network,
A message buffer that is partitioned into a predetermined number of buffers, an address is given to each buffer, and a message can be stored for each buffer;
A predetermined number corresponding to each buffer, and a preparation information holding unit for holding preparation information for informing whether transmission or reception is ready;
A predetermined number is provided for each of the preparation information holding units, and the preparation information holding for the corresponding address is received from the CPU when receiving a second state signal related to the corresponding address from the message handling unit. A third mask circuit section for masking input of the second write signal to the section;
With
The second state signal is a signal transmitted from the message handling unit and indicating a state in which the buffer associated with a predetermined address of the message buffer is being accessed in order to perform transmission load or reception storage. ,
The data processing module, wherein the second write signal is a signal transmitted from the CPU, and is a signal for writing preparation information in the preparation information holding unit related to a predetermined address. A message buffer comprising a plurality of buffers each having an area in which an ID is set and an area in which message data corresponding to the ID is written;
A preparation information holding circuit provided corresponding to the plurality of buffers, in which information indicating completion of preparation is written to a buffer in which setting of an ID is completed among the plurality of buffers;
A message handling unit for transmitting the message data written in the message buffer indicating that the preparation information holding circuit is ready on the bus;
Writing the ID into the message buffer and writing the preparation completion information into the preparation information holding circuit;
A first gate circuit for prohibiting writing of message data from the CPU when the preparation information holding circuit indicates completion of preparation;
A data processing module comprising:   When the message handling outputs message data on the bus from the buffer selected from the plurality of buffers or when storing message data on the bus in the buffer selected from the plurality of buffers, the CPU A data processing module comprising: a second gate circuit that prohibits the preparation completion clearing of the preparation information holding circuit corresponding to the selected buffer.

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