TWI720565B - Memory controller and data storage device - Google Patents

Abstract

A memory controller coupled to an external memory device for controlling the operations thereof. The memory controller comprises a central processing unit, an interface logic circuit and an arbiter circuit. The central processing unit comprises an internal memory device. The interface logic circuit is coupled to the external memory device and a standard bus. The arbiter circuit is directly coupled to the central processing unit via a static random access memory bus. When the central processing unit has to read predetermined data stored in the external memory device, the central processing unit issues a first request to the interface logic circuit. In response to the first request, the interface logic circuit reads the predetermined data from the external memory device and transmits the predetermined data to the arbiter circuit via the standard bus. The arbiter circuit transfers the predetermined data directly to the central processing unit via the static random access memory bus to write the predetermined data in the internal memory device.

Description

Memory controller and data storage device

The present invention relates to a data processing circuit, in particular to a data processing circuit that can effectively improve system performance.

As the technology of data storage devices has grown rapidly in recent years, many data storage devices, such as memory cards that comply with SD/MMC specifications, CF specifications, MS specifications, and XD specifications, solid state drives, and embedded memory (embedded Multi Media Card, abbreviated as eMMC) and Universal Flash Storage (abbreviated as UFS) have been widely used in a variety of applications. Therefore, effective access control has also become an important issue on these data storage devices.

In order to improve the access performance of the memory device, the present invention proposes a new memory controller architecture, which not only saves circuit area, but also saves the time required for data access and effectively improves system performance.

The present invention provides a memory controller coupled to an external memory device for controlling the operation of the external memory device, and includes a central processing unit, an interface logic circuit, and an arbitration circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to the external memory device and a standard bus. The arbitration circuit is coupled to the standard bus and the central processing unit. The arbitration circuit is directly coupled to the central processing unit through a static random access memory bus. When the central processing unit needs to read a predetermined data stored in an external memory device, the central processing unit sends a first request to the interface logic circuit, and the interface logic circuit reads the predetermined data from the external memory device in response to the first request, and The predetermined data is sent to the arbitration circuit through the standard bus, and the arbitration circuit directly sends the predetermined data to the central processing unit through the static random access memory bus for writing into the internal memory device.

The present invention also provides a data storage device including a non-volatile memory and a memory controller. The memory controller is coupled to the volatile memory for controlling the operation of the non-volatile memory. The non-volatile memory includes a central processing unit, an interface logic circuit and an arbitration circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to the volatile memory and a standard bus. The arbitration circuit is coupled to the standard bus and the central processing unit. The arbitration circuit is directly coupled to the central processing unit through a static random access memory bus. When the central processing unit needs to read a predetermined data stored in the non-volatile memory, the central processing unit sends a first request to the interface logic circuit, and the interface logic circuit reads the predetermined data from the non-volatile memory device in response to the first request Data is sent to the arbitration circuit through the standard bus, and the arbitration circuit directly sends the predetermined data to the central processing unit through the static random access memory bus for writing into the internal memory device.

In order to make the purpose, features and advantages of the present invention more comprehensible, specific embodiments of the present invention are listed below, with the accompanying drawings, and detailed descriptions are as follows. The purpose is to illustrate the spirit of the present invention and not to limit the protection scope of the present invention. It should be understood that the following embodiments can be implemented by software, hardware, firmware, or any combination of the foregoing.

FIG. 1 is a block diagram showing an example of a data storage device according to an embodiment of the invention. The data storage device 100 may include a memory controller 110 and a memory device 120. The memory device 120 may be a non-volatile memory, such as NAND Flash. The memory controller 110 is coupled to the memory device 120 for controlling the operation of the memory device 120 and accessing data stored in the memory device 120.

The data storage device 100 can be further coupled to a host (not shown) for transmitting data and commands to the host, or receiving data and commands from the host. The host can be a mobile phone, a tablet computer, a notebook computer, a navigation machine, or a vehicle-mounted system, etc.

It is worth noting that, to simplify the description, Figure 1 only shows components related to the present invention. However, the implementation of the present invention is not limited to the architecture shown in Figure 1.

Figure 2 shows the architecture of a memory controller. The memory controller 210 can be a controller chip coupled to an external memory device 220. The memory device 220 may include one or more non-volatile memories.

The memory controller 210 may include a central processing unit (CPU) 230, a direct memory access (DMA) device 240, an interface logic circuit 250, a standard bus 260, and a plurality of arbitration circuits 270-1, 270-2, 270-3...270-N, and a plurality of slave memories 280-1, 280-2, 280-3...280-N, where N is a positive integer, and the slave memories can It is a volatile memory, for example, Static Random Access Memory (SRAM).

The direct memory access device 240, the interface logic circuit 250, or other devices (not shown in the figure) that access the slave memory can be regarded as master devices, and the slave memories 280-1, 280-2 , 280-3...280-N can be regarded as a slave/slave. The standard bus 260 is used to provide a transmission interface between the main device and the auxiliary device. The arbitration circuits 270-1, 270-2, 270-3...270-N are respectively coupled to the slave memories 280-1, 280-2, 280-3...280-N for arbitrating each slave memory. More specifically, the arbitration circuit receives requests or commands from one or more master devices through the standard bus 260, and arbitrates the priority of multiple requests or commands, so that multiple master devices request access to the same slave memory at the same time. At the time of the system, it determines which master device's request is to be processed first.

The central processing unit 230 may include a plurality of internal memory devices, for example, an instruction close coupled memory (ICCM) 231 and a data close coupled memory (DCCM) 232 . Among them, ICCM and DCCM can be static random access memory, ICCM 231 can be used to store program codes, and DCCM 232 can be used to store data.

In the architecture shown in FIG. 2, the direct memory access device 240 is used to assist the central processing unit 230 to access the data stored in the memory device 220. For example, when the central processing unit 230 needs to use the data or code stored in the memory device 220, it can issue a read through a command interface (not shown) coupled to the interface logic circuit 250 Request or read request instructions. In response to this request or command, the interface logic circuit 250 reads the data required by the central processing unit 230 from the memory device 220, and writes the data to the slave memory through the standard bus 260 as shown in the transmission path marked 1 in the figure 280-1.

The interface logic circuit 250 may include an Error Correction Code (ECC) engine 251. When the error correction code engine 251 detects an error in the read data, it can read the error data back to the interface logic circuit 250 for error correction through the transmission path marked 2 in the figure, and then correct it. The completed correct data is written back to the slave memory 280-1.

When the data required by the central processing unit 230 has been transmitted, the interface logic circuit 250 can send an interrupt signal to notify the central processing unit 230 (or the central processing unit 230 can continue to actively inquire about the data status). The central processing unit 230 then issues a request or command through a command interface (not shown) coupled to the direct memory access device 240. In response to this request or command, the direct memory access device 240 transfers the data from the slave memory 280-1 to the internal memory device of the central processing unit 230 as shown in the transmission path marked 3 in the figure, for example, ICCM 231 or DCCM 232.

In the architecture shown in FIG. 2, since the data transmission required by the central processing unit 230 must be performed through the direct memory access device 240, it is inefficient. In order to improve the above defects and improve the access performance of the memory device, a new memory controller architecture and data access method are proposed as follows.

FIG. 3 is a block diagram of the memory controller according to an embodiment of the invention. The memory controller 310 can be a controller chip of the data storage device as shown in FIG. 1 and is coupled to an external memory device 320. The memory device 320 may include one or more non-volatile memories.

The memory controller 310 may include a central processing unit 330, an interface logic circuit 350, a standard bus 360, a plurality of arbitration circuits 370-1, 370-2, 370-3...370-N, and a plurality of slave memories 380-2, 380-3...380-N, where N is a positive integer, and the slave memory may be a volatile memory, for example, a static random access memory (SRAM).

The interface logic circuit 350, or other devices (not shown in the figure) that access the slave memory can be regarded as the master, and the slave memories 380-2, 380-3...380-N can be regarded as Secondary device/slave device (slave). The standard bus 360 is used to provide a transmission interface between the main device and the auxiliary device. The arbitration circuits 370-2, 370-3...370-N are respectively coupled to the slave memories 380-2, 380-3...380-N for arbitrating each slave memory. More specifically, the arbitration circuit receives requests or commands from one or more master devices through the standard bus 360, and arbitrates the priority of multiple requests or commands, so that multiple master devices request access to the same slave memory at the same time. At the time of the system, it determines which master device's request is to be processed first.

The central processing unit 330 may include a plurality of internal memory devices, such as ICCM 331-1 and 331-2 for storing program codes, and DCCM for storing data (simplified illustration, not shown in Figure 3, and (Shown in Figure 4), and read-only memory 339. Among them, ICCM and DCCM can be static random access memory.

In the architecture shown in Figure 3, the central processing unit 330 does not include a direct memory access device. According to an embodiment of the present invention, the arbitration circuit 370-1 is directly coupled to the central processing unit 330 through static random access memory buses 390 and 391. The static random access memory buses 390 and 391 are used to provide a transmission interface between the arbitration circuit 370-1 and the central processing unit 330.

When the central processing unit 330 needs to use or read data stored in the memory device 320, for example, program codes, it can issue a read request or read through a command interface (not shown) coupled to the interface logic circuit 350 Fetch request instructions. The interface logic circuit 350 reads the code required by the central processing unit 330 from the memory device 320 in response to this request or command, and transmits the data to the arbitration circuit through the standard bus 360 as shown in the transmission path marked 1 in the figure 370-1. The arbitration circuit 370-1 directly transmits the program code to the central processing unit 330 through the static random access memory bus 390 for writing into the internal memory device ICCM 331-1 or 331-2.

When the interface logic circuit 350 needs to read the data stored in the internal memory device ICCM 331-1 or 331-2, the interface logic circuit 350 sends a read request or read request command to the arbitration circuit 370-1, and the arbitration circuit 370 -1 In response to this request or command, the read data is directly received through the static random access memory bus 391, and then the read data is sent to the interface logic circuit 350 through the standard bus 360.

For example, the interface logic circuit 350 may include an error correction code engine 351. When the error correction code engine 351 detects an error in the read code or data, the arbitration circuit 370-1 can directly receive it from the internal memory device ICCM 331-1 or 331 through the static random access memory bus 391 -2 The read error code or data, and then follow the transmission path marked 2 in the figure, and send the data to the interface logic circuit 350 through the standard bus 360 for error correction. The corrected correct code or data will be transmitted to the arbitration circuit 370-1 through the standard bus 360 following the transmission path marked as 1 in the figure. The arbitration circuit 370-1 then directly transmits the program code to the central processing unit 330 through the static random access memory bus 390 for writing into the internal memory device ICCM 331-1 or 331-2.

According to an embodiment of the present invention, the central processing unit 330 may include a plurality of multiplexers, such as the multiplexers 335, 336, 337, 338 shown in the figure. The multiplexers 335 and 336 can be used to select the source path of the written data. The multiplexers 337 and 338 can be used to select the source path for reading data.

The multiplexers 335 and 336 may respectively include a plurality of input terminals. One input terminal is connected to an internal bus of the central processing unit 330, and the other input terminal is directly connected to the arbitration circuit 370 through the static random access memory bus 390. 1 One of the output interfaces. The output terminal of the multiplexer 335 is coupled to the ICCM 331-1, and the output terminal of the multiplexer 336 is coupled to the ICCM 331-2. The multiplexers 335 and 336 respectively multiplex and transmit data from the CPU internal bus or the static random access memory bus 390 according to a selection signal.

The multiplexers 337 and 338 may respectively include multiple input terminals, one of which is connected to the ICCM 331-1, and the other input is connected to the ICCM 331-2. The output terminal of the multiplexer 337 is directly connected to an input interface of the arbitration circuit 370-1 through the static random access memory bus 391, and the output terminal of the multiplexer 338 is coupled to an internal bus of the central processing unit 330. The multiplexers 337 and 338 respectively multiplex and transmit data from ICCM 331-1 or ICCM 331-2 according to a selection signal.

According to an embodiment of the present invention, the central processing unit 330 may further include logic circuits 333-1, 333-2, 333-3, and 333-4. The logic circuits 333-1 and 333-2 respectively generate a selection signal according to an index for indicating whether an external device (ie, a device other than the central processing unit 330) performs a write operation and the memory location to be written. For example, when the write operation index performed by the external device is set, and the memory location to be accessed falls within the memory address range of ICCM 331-1, the value of the selection signal output by the logic circuit 333-1 can be 1 is used to select the source path for writing data to the external device, for example, the static random access memory bus 390 and the arbitration circuit 370-1 shown in the figure, so that the external device has the write ICCM 331-1 permission. On the other hand, the value of the selection signal output by the logic circuit 333-2 can be 0, which is used to select the source path of writing data as the CPU internal bus, so that the internal device has the authority to write to the ICCM 331-2. According to an embodiment of the present invention, the pointer of the write operation performed by the external device and the information of the memory location accessed can be stored in the central processing unit 330 or the register of the external device.

The logic circuits 333-3 and 333-4 respectively generate a selection signal according to an index for indicating whether the external device performs a read operation and the memory location to be read. For example, when the device to read the internal memory of the CPU is an external device, and the memory location to be accessed falls within the memory address range of ICCM 331-1, the value of the selection signal output by the logic circuit 333-3 can be If it is 0, it is used to select the source path of reading data as ICCM 331-1, so that the external device can read the data of ICCM 331-1. For another example, when the device to read the internal memory of the CPU is an internal device of the CPU, and the memory location to be accessed falls within the memory address range of ICCM 331-2, the output selection of the logic circuit 333-4 The signal value can be 1, which is used to select the source path for reading data as ICCM 331-2, so that the internal device of the CPU can read the data of ICCM 331-2. According to an embodiment of the present invention, the index of the read operation performed by the external device and the information of the memory location to be read can be stored in the central processing unit 330 or the register of the external device.

It is worth noting that although in the above embodiments, the multiplexer selection signal is a one-bit signal, the present invention is not limited to this. Those who know this skill can easily understand that the multiplexers 335, 336, 337, 338 can be expanded to include more than two input terminals, so the corresponding selection signal can be a multi-bit signal.

According to an embodiment of the present invention, the internal memory device of the central processing unit 330, for example, the width of one of the data characters of the ICCM 331-1 and 331-2 shown in the figure is set to be the same as that of the standard bus 360. The character width is the same. In addition, the width of one of the data characters of the static random access memory buses 390 and 391 can also be set to be the same as the width of one of the data characters of the standard bus 360. In this way, the data can be directly written into the internal memory device of the central processing unit 330 without the need for character width conversion. For example, assuming that a data character width of the standard bus 360 is X bits, the internal memory device of the central processing unit 330 and the static random access memory buses 390 and 391 have a data character width in the configuration Time can be set to X bits, and the data depth of the internal memory device of the central processing unit 330 can be set to (M/X) storage units, where M is the number of internal memory devices of the central processing unit 330 The memory capacity, and the data character width X represents that each access of the internal memory device will access X bits of data. In addition, the arbitration circuit 370-1 coupled to the standard bus 360 and the static random access memory bus can perform data conversion between the standard bus interface protocol and the static random access memory bus interface protocol.

In addition, according to an embodiment of the present invention, in addition to setting the data character width of the internal memory device of the central processing unit 330 and the static random access memory bus, other control static random access memory buses 390 and 391 The data character width of the circuit and the encoding/decoding method of the memory address must also be correspondingly set according to a data character width of the standard bus 360.

It is worth noting that, to simplify the description, Figure 3 only shows components related to the present invention. However, the implementation of the present invention is not limited to the architecture shown in Figure 3. For example, the memory controller may further include other host devices not shown in the figure.

FIG. 4 shows a block diagram of a memory controller according to another embodiment of the invention. The structure shown in Fig. 4 is similar to that shown in Fig. 3, except that Fig. 4 shows the DCCMs 332-1 and 332-2 included in the central processing unit 330 for storing data. Therefore, for the description of the same components, refer to the description of FIG. 3, which is not repeated here. In addition, it is worth noting that the components shown in Figures 3 and 4 can be integrated into the same memory controller.

In the architecture shown in Figure 4, the central processing unit 330 does not include a direct memory access device. According to an embodiment of the present invention, the arbitration circuit 370-0 is directly coupled to the central processing unit 330 through static random access memory buses 392 and 393. The static random access memory buses 392 and 393 are used to provide a transmission interface between the arbitration circuit 370-0 and the central processing unit 330.

When the central processing unit 330 needs to use or read the data stored in the memory device 320, it can issue a read request or read request command through a command interface (not shown) coupled to the interface logic circuit 350. The interface logic circuit 350 reads the data required by the central processing unit 330 from the memory device 320 in response to this request or command, and transmits the data to the arbitration circuit 370 through the standard bus 360 as shown in the transmission path marked 1 in the figure. -0. The arbitration circuit 370-0 directly transmits the program code to the central processing unit 330 through the static random access memory bus 392 for writing into the internal memory device DCCM 332-1 or 332-2.

When the interface logic circuit 350 needs to read the data stored in the internal memory device DCCM 332-1 or 332-2, the interface logic circuit 350 sends a read request or read request command to the arbitration circuit 370-0, and the arbitration circuit 370 -0 In response to this request or command, the read data is directly received through the static random access memory bus 393, and then the read data is sent to the interface logic circuit 350 through the standard bus 360.

For example, when the error correction code engine 351 of the interface logic circuit 350 detects an error in the read data, the arbitration circuit 370-0 can directly receive it from the internal memory device through the static random access memory bus 393 The erroneous data read by DCCM 332-1 or 332-2 is then sent to the interface logic circuit 350 through the standard bus 360 as shown by the transmission path marked 2 in the figure for error correction. The corrected correct code or data will be transmitted to the arbitration circuit 370-0 through the standard bus 360 following the transmission path marked as 1 in the figure. The arbitration circuit 370-0 then directly transmits the program code to the central processing unit 330 through the static random access memory bus 392 for writing into the internal memory device DCCM 332-1 or 332-2.

According to an embodiment of the present invention, the central processing unit 330 may include a plurality of multiplexers, such as the multiplexers 345, 346, 347, and 348 shown in the figure. The multiplexers 345 and 346 can be used to select the source path of the written data. The multiplexers 347 and 348 can be used to select the source path of the read data.

The multiplexers 345 and 346 may respectively include multiple input terminals, one of which is connected to an internal bus of the central processing unit 330, and the other input is directly connected to the arbitration circuit 370 through the static random access memory bus 392. One of 0 output interface. The output terminal of the multiplexer 345 is coupled to the DCCM 332-1, and the output terminal of the multiplexer 346 is coupled to the DCCM 332-2. The multiplexers 345 and 346 respectively multiplex and transmit data from the CPU internal bus or the static random access memory bus 392 according to a selection signal.

The multiplexers 347 and 348 may respectively include multiple input terminals, one of the input terminals is connected to the DCCM 332-1, and the other input terminal is connected to the DCCM 332-2. The output terminal of the multiplexer 347 is directly connected to an input interface of the arbitration circuit 370-0 through the static random access memory bus 393, and the output terminal of the multiplexer 348 is coupled to an internal bus of the central processing unit 330. The multiplexers 347 and 348 respectively multiplex and transmit data from the DCCM 332-1 or DCCM 332-2 according to a selection signal.

According to an embodiment of the present invention, the central processing unit 330 may further include logic circuits 343-1, 343-2, 343-3, and 343-4. The logic circuits 343-1 and 343-2 respectively generate a selection signal according to an index indicating whether an external device (ie, a device other than the central processing unit 330) performs a write operation and the memory location to be written. For example, when the write operation index performed by the external device is set, and the memory location to be accessed falls within the memory address range of DCCM 332-1, the value of the selection signal output by the logic circuit 343-1 can be 1 is used to select the source path for writing data as an external device, for example, the static random access memory bus 392 and the arbitration circuit 370-0 shown in the figure, so that the external device has DCCM 332-1 for writing permission. On the other hand, the value of the selection signal output by the logic circuit 343-2 may be 0, which is used to select the source path of writing data as the CPU internal bus, so that the internal device has the authority to write the DCCM 332-2. According to an embodiment of the present invention, the pointer of the write operation performed by the external device and the information of the memory location accessed can be stored in the central processing unit 330 or the register of the external device.

The logic circuits 343-3 and 343-4 respectively generate a selection signal according to an index for indicating whether the external device performs a read operation and the memory location to be read. For example, when the device to read the internal memory of the CPU is an external device, and the memory location to be accessed falls within the memory address range of DCCM 332-1, the value of the selection signal output by the logic circuit 343-3 can be If it is 0, it is used to select the source path of reading data as DCCM 332-1, so that the external device can read the data of DCCM 332-1. For another example, when the device to read the internal memory of the CPU is an internal device of the CPU, and the memory location to be accessed falls within the memory address range of DCCM 332-2, the output selection of the logic circuit 343-4 The signal value can be 1, which is used to select the source path of reading data as DCCM 332-2, so that the internal device of the CPU can read the data of DCCM 332-2. According to an embodiment of the present invention, the index of the read operation performed by the external device and the information of the memory location to be read can be stored in the central processing unit 330 or the register of the external device.

It is worth noting that although in the above embodiments, the multiplexer selection signal is a one-bit signal, the present invention is not limited to this. Those who know this skill can easily understand that the multiplexers 345, 346, 347, and 348 can be expanded to include more than two input terminals, so the corresponding selection signal can be a multi-bit signal.

According to an embodiment of the present invention, the internal memory device of the central processing unit 330, for example, the data character width of one of the DCCM 332-1 and 332-2 shown in the figure is set to be the same as that of the standard bus 360. The character width is the same. In addition, the width of one of the data characters of the static random access memory buses 392 and 393 can also be set to be the same as the width of one of the data characters of the standard bus 360. In this way, the data can be directly written into the internal memory device of the central processing unit 330 without the need for character width conversion. For example, assuming that a data character width of the standard bus 360 is X bits, the internal memory device of the central processing unit 330 and the static random access memory buses 392 and 393 have a data character width in the configuration Time can be set to X bits, and the data depth of the internal memory device of the central processing unit 330 can be set to (M/X) storage units, where M is the number of internal memory devices of the central processing unit 330 The memory capacity, and the data character width X represents that each access of the internal memory device will access X bits of data. In addition, the arbitration circuit 370-0 coupled to the standard bus 360 and the static random access memory bus can perform data conversion between the standard bus interface protocol and the static random access memory bus interface protocol.

In addition, according to an embodiment of the present invention, in addition to setting the data character width of the internal memory device of the central processing unit 330 and the static random access memory bus, the other control static random access memory buses 392 and 393 The data character width of the circuit and the encoding/decoding method of the memory address must also be correspondingly set according to a data character width of the standard bus 360.

It is worth noting that, to simplify the description, Figure 4 only shows components related to the present invention. However, the implementation of the present invention is not limited to the architecture shown in Figure 4. For example, the memory controller may further include other host devices not shown in the figure.

As mentioned above, compared to the architecture shown in Figure 2, in the architectures of Figures 3 and 4, the use of a direct memory access device and at least one slave memory is omitted. In this way, not only the circuit area can be saved, but also the time required for data access can be saved by reducing the movement of data to the slave memory, and the system performance can be effectively improved. In addition, since the architectures in Figures 3 and 4 are simpler than the architecture shown in Figure 2, the complexity of the circuit can also be reduced, effectively reducing hardware costs.

The term "coupling" in the specification of the present invention generally refers to various direct or indirect electrical connection methods. Although the present invention is disclosed as above in the preferred embodiment, it is not intended to limit the scope of the present invention. Anyone who is familiar with the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100‧‧‧Data storage device; 110, 210, 310‧‧‧Memory Controller; 120, 220, 320‧‧‧Memory device; 230, 330‧‧‧ central processing unit; 240‧‧‧Direct memory access device; 250, 350‧‧‧ interface logic circuit; 260, 360‧‧‧ standard bus; 270-1, 270-2, 270-3, 270-N, 370-0, 370-1, 370-2, 370-3, 370-N‧‧‧Arbitration circuit; 280-1, 280-2, 280-3, 280-N, 380-2, 380-3, 380-N‧‧‧Subordinate memory; 231, 331-1, 331-2, ICCM‧‧‧ instructions are tightly coupled to memory; 232, 332-1, 332-2, DCCM‧‧‧Data is tightly coupled to memory; 251, 351‧‧‧ Error correction code engine; 333-1, 333-2, 333-3, 333-4, 343-1, 343-2, 343-3, 343-4‧‧‧Logic circuit; 335, 336, 337, 338, 345, 346, 347, 348‧‧‧ multiplexer; 390, 391, 392, 393‧‧‧Static random access memory bus.

FIG. 1 is a block diagram showing an example of a data storage device according to an embodiment of the invention. Figure 2 shows the architecture of a memory controller. FIG. 3 is a block diagram of the memory controller according to an embodiment of the invention. FIG. 4 shows a block diagram of a memory controller according to another embodiment of the invention.

100‧‧‧Data storage device

110‧‧‧Memory Controller

120‧‧‧Memory Device

Claims (12)

A memory controller, coupled to an external device, includes: a central processing unit coupled to a standard bus, wherein the central processing unit includes a first internal memory device and a second internal memory device; And an arbitration circuit coupled to the standard bus and the central processing unit, wherein the arbitration circuit is based on a memory address of an access operation performed by the external device to pass through a static random access memory bus Access the first internal memory device or the second internal memory device. For the memory controller described in claim 1, wherein the central processing unit further includes a first logic circuit and a second logic circuit, wherein the first logic circuit and the second logic circuit are based on the external The device executes an index of the access operation and the memory address of the access operation to respectively generate a first selection signal and a second selection signal. The memory controller described in claim 2, wherein: when the indicator for executing the access operation by the external device is set and the memory address accessed by the access operation is located in the first internal When the memory address range of the memory device is within the memory address range, the first logic circuit sets the first selection signal to a high logic state to select the external device as the source path of the first internal memory device, and the second logic circuit The logic circuit sets the second selection signal to a low logic state to set the source path of the second internal memory device as an internal bus of the central processing unit. The memory controller described in item 3 of the scope of patent application, in which: When the indicator for executing the access operation by the external device is not set and the memory address accessed by the access operation is within the memory address range of the first internal memory device, the first logic circuit The first selection signal is set to a low logic state so that the external device can read the first internal memory device, and the second logic circuit is to set the second selection signal to a high logic state to make The internal device of the central processing unit can read the second internal memory device. The memory controller described in claim 4, wherein the central processing unit further includes: a first multiplexer coupled to the first internal memory device, the internal bus and the static random memory Fetching a memory bus for multiplexing data from the internal bus or the static random access memory bus according to the first selection signal; and a second multiplexer coupled to the second internal The memory device, the internal bus and the static random access memory bus are used for multiplexing data from the internal bus or the static random access memory bus according to the second selection signal. For the memory controller described in claim 5, wherein the arbitration circuit is directly connected to an input terminal of the first multiplexer and the second multiplexer through the static random access memory bus The other input. A data storage device includes: a memory controller coupled to an external device, wherein the memory controller includes: a central processing unit including a first memory device and a second memory device; and An arbitration circuit is coupled to the standard bus and the central processing unit, wherein the arbitration circuit is stored through a static random access memory bus according to the memory address of an access operation performed by the external device Take the first internal memory device or the second internal memory device. For the data storage device described in claim 7, wherein the central processing unit further includes a first logic circuit and a second logic circuit, wherein the first logic circuit and the second logic circuit are based on the external device Perform an index of the access operation and the memory address of the access operation to generate a first selection signal and a second selection signal, respectively. The data storage device described in item 8 of the scope of patent application, wherein: when the indicator for executing the access operation by the external device is set and the memory address accessed by the access operation is located in the first internal memory When the memory address range of the physical device is within the range of the memory address, the first logic circuit sets the first selection signal to a high logic state to select the external device as the source path of the first internal memory device, and the second logic The circuit sets the second selection signal to a low logic state to set the source path of the second internal memory device as an internal bus of the central processing unit. The data storage device described in item 9 of the scope of patent application, wherein: when the indicator for executing the access operation by the external device is not set and the memory address accessed by the access operation is located in the first internal When the memory address range of the memory device is within the memory address range, the first logic circuit sets the first selection signal to a low logic state So that the external device can read the first internal memory device, and the second logic circuit sets the second selection signal to a high logic state so that the internal device of the central processing unit can read the second Internal memory device. According to the data storage device described in claim 10, the central processing unit further includes: a first multiplexer coupled to the first internal memory device, the internal bus, and the static random access A memory bus for multiplexing data from the internal bus or the static random access memory bus according to the first selection signal; and a second multiplexer coupled to the second internal memory The body device, the internal bus and the static random access memory bus are used for multiplexing data from the internal bus or the static random access memory bus according to the second selection signal. Such as the data storage device described in claim 11, wherein the arbitration circuit is directly connected to an input terminal of the first multiplexer and the other of the second multiplexer through the static random access memory bus One input.

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