JP2006251862A - Image processing apparatus, image processing method, display controller, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus, an image processing method, a display controller, and an electronic apparatus capable of preventing deterioration of an image after processing. <P>SOLUTION: The image processing apparatus 100 includes a magnification register 10 to be set with an inverse number of a magnification for enlarging or reducing an input image, an accumulator 30 carrying out accumulative adding of inverse numbers of magnification, an initial value setting register 32 to be set with an initial value of the accumulator 30, and a seamless pixel processing part 20 carrying out a enlargement or reduction process of the image on the basis of the inverse number of magnification. When an integer part of the inverse number of magnification is zero, the seamless pixel processing part 20 outputs image data of the image after the enlargement process, and when the integer part of the inverse number of magnification is not zero, the seamless pixel processing part 20 outputs a valid signal specifying whether or not to carry out thinning per each pixel composing the input image on the basis of an accumulative adding result of the accumulator 30, and image data of the image after the reduction process. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image processing device, an image processing method, a display controller, and an electronic apparatus.

  In a portable electronic device incorporating a camera module such as a cellular phone, an image captured by the camera module can be displayed on a screen of an electro-optical device such as a liquid crystal display (LCD) panel. ing. At this time, the size of the captured image is enlarged or reduced in consideration of the screen size of the electro-optical device and the memory capacity for storing the captured image data.

An image processing apparatus that performs such enlargement and reduction of an image is disclosed in Patent Document 1, for example. In this image processing apparatus, the magnification of the image is obtained by using the number of pixels of the image before processing as a divisor and the number of pixels of the image after processing as a dividend. Then, by accumulating the reciprocal of the obtained magnification, an interpolation coefficient for linear interpolation for each pixel of the processed image is obtained.
JP-A-9-326958

  However, in the conventional image processing apparatus, when focusing on the pixel data of the image after the enlargement process or the reduction process, one pixel data of the original image is used as it is, and one that is interpolated from a plurality of pixel data of the original image May be mixed.

  FIG. 19 schematically shows an example of an image after enlargement processing or reduction processing in a conventional image processing apparatus.

  FIG. 19 shows an example of an image after processing when, for example, enlargement processing or reduction processing is performed in the horizontal direction of the image. That is, in FIG. 19, when attention is paid to the pixel data of the processed image, there are a mixture of one in which one pixel data of the original image is used as it is and one that is interpolated from a plurality of pixel data of the original image. When one pixel data of the original image is periodically used as it is, pixels that are not subjected to the interpolation process are emphasized, and a striped pattern appears in the processed image. As a result, the image after processing is deteriorated.

  Therefore, when focusing on the pixel data of the processed image, it is desirable that the image processing apparatus has a function for assuming that all pixel data is interpolated from a plurality of pixel data of the original image.

  In the conventional image processing apparatus, since the number of pixels of the image before and after the processing is set, a divider is required to obtain the reciprocal of the magnification, and the circuit scale increases.

  Further, in the conventional image processing apparatus, it is necessary to compare the cumulative addition result of the reciprocal of the magnification with the count value of the pixel counter. Therefore, as the screen size of the electro-optical device increases, the number of bits required for the pixel counter increases. Furthermore, since the number of bits of the pixel counter is fixed, the upper limit of the image size is fixed, and it may not be possible to cope with the enlargement of the screen size of the electro-optical device.

  Furthermore, in the conventional image processing apparatus, in the firmware (software) for performing the control, in addition to the number of pixels of the image before and after the above-described processing, an operation mode for designating image enlargement or reduction is set. There is a need. When controlling such an image processing apparatus, it is necessary for the firmware to specify error processing, which increases the amount of firmware code.

  FIG. 20A shows an example of firmware code for controlling the conventional image processing apparatus.

  In addition to the parameter for specifying the input image, the parameter for specifying the output image, and the magnification, when it is necessary to specify an operation mode for specifying enlargement or reduction, a flow for instructing the enlargement process to the image processing apparatus and the reduction process It is necessary to include error processing in each of the flows instructing. For this reason, the code amount of the firmware is increased.

  On the other hand, if it is not necessary to set an operation mode for designating image enlargement or reduction in the image processing apparatus, the amount of code of firmware for controlling the image processing apparatus can be greatly reduced.

  FIG. 20B shows an example of firmware code for controlling the image processing apparatus that does not need to set an operation mode for designating image enlargement or reduction.

  In this case, since it is only necessary to specify the parameter for specifying the input image, the parameter for specifying the output image, and the magnification, the error processing is not included in each flow as shown in FIG. As shown in the figure, the amount of firmware code can be reduced.

  As described above, it is desirable that the image processing apparatus need not designate an operation mode every time the magnification is changed, and can perform the image enlargement and reduction processing seamlessly according to the set magnification.

  The present invention has been made in view of the technical problems as described above. The object of the present invention is to mix pixels that use pixel data of the original image as they are and pixels that are interpolated from the pixel data of the original image. It is an object of the present invention to provide an image processing apparatus, an image processing method, a display controller, and an electronic device that can avoid generation of an image that deteriorates.

  A second object of the present invention is an image processing apparatus, an image processing method, and an image processing apparatus capable of executing an image enlargement and reduction process according to a set magnification without reducing the circuit scale and designating enlargement or reduction. To provide a display controller and an electronic device.

In order to solve the above problems, the present invention
An image processing apparatus for enlarging and reducing an input image,
A magnification register in which a reciprocal of a magnification for enlarging or reducing the input image is set;
An accumulator that cumulatively adds the reciprocal of the magnification;
An initial value setting register in which an initial value of the accumulator is set;
A seamless pixel processing unit that performs image enlargement or reduction processing based on the inverse of the magnification,
The accumulator is
After adding the reciprocal of the magnification to the initial value, cumulatively adding the reciprocal of the magnification,
When the integer part of the reciprocal of the magnification is 0, the seamless pixel processing unit outputs pixel data of the image after the enlargement process performed on the input image,
When the integer part of the reciprocal of the magnification is not 0, the seamless pixel processing unit outputs a valid signal that specifies whether or not to thin out the pixel unit constituting the input image based on the cumulative addition result of the accumulator. The present invention relates to an image processing apparatus that outputs and outputs pixel data of an image after reduction processing performed on the input image.

  According to the present invention, since the initial value can be set, the result of cumulative addition of the reciprocal of the magnification based on the initial value can be changed according to the initial value. It is possible to prevent deterioration of the pixel after processing due to enhancement of a pixel that has not been subjected to.

  Further, according to the present invention, it is not necessary to set the number of pixels of the pre-processed image and the post-processed image for the purpose of obtaining the magnification in order to perform the image enlargement process and the reduction process. Can be adopted. Furthermore, the image enlargement process or the reduction process can be performed based on the integer part of the reciprocal of the magnification that is cumulatively added to perform the image enlargement or reduction process. Therefore, it is possible to seamlessly execute image enlargement and reduction processing according to the set magnification without specifying enlargement or reduction for the image processing apparatus. For this reason, for example, as shown in FIG. 20B, the code amount of firmware for controlling the image processing apparatus can be reduced.

  Furthermore, during the reduction process, a valid signal indicating whether or not to decimate in units of pixels can be output. Therefore, the subsequent apparatus of the image processing apparatus can easily decimate pixels based on the valid signal. It becomes possible. Since the image processing apparatus obtains pixel data after reduction processing and generates a valid signal, it is not necessary to generate a valid signal by another means after obtaining pixel data after reduction processing.

In the image processing apparatus according to the present invention,
The seamless pixel processing unit
A filter operation unit that performs a product-sum operation based on pixel data of the input image and an output of the accumulator to generate pixel data after the enlargement process or reduction process,
When the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result is not 0,
The pixel data to be processed by the filter operation unit is updated, and the image after the enlargement process is performed by performing a product-sum operation on the updated pixel data and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result Generate pixel data for
When the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result is 0,
The image after the enlargement processing by performing a product-sum operation on the previous pixel data and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result without updating the pixel data to be processed by the filter operation unit Generate pixel data for
When the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result is not 0,
While decrementing the integer part of the cumulative addition result, without updating the output of the filter operation unit,
When the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result is 0,
The integer part of the addition result of the reciprocal of the magnification and the output of the accumulator is decremented, and the product of the pixel data to be processed by the filter operation unit and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result Pixel data of the image after the reduction process can be generated by performing a sum operation.

  According to the present invention, in addition to the above effects, the image enlargement process and the reduction process based on the cumulative addition result of the reciprocal of the magnification can be realized with substantially the same resource, so the enlargement or reduction is designated for the image processing apparatus. Therefore, it is possible to seamlessly execute image enlargement and reduction processing according to the set magnification.

  Further, according to the present invention, it is not necessary to compare the cumulative addition result of the reciprocal of the magnification with the count value of the pixel counter. Therefore, as the screen size of the electro-optical device increases, the number of bits required for the pixel counter increases. Furthermore, since the number of bits of the pixel counter is fixed, the upper limit of the image size is fixed, and it is possible to avoid the situation where it becomes impossible to cope with the increase in the screen size of the electro-optical device.

The present invention also provides
An image processing apparatus for enlarging and reducing an input image,
A magnification register in which a reciprocal of a magnification for enlarging or reducing the input image is set;
An accumulator that cumulatively adds the reciprocal of the magnification;
An initial value setting register in which an initial value of the accumulator is set;
A seamless pixel processing unit that performs image enlargement or reduction processing based on the inverse of the magnification,
The accumulator is
After adding the reciprocal of the magnification to the initial value, cumulatively adding the reciprocal of the magnification,
When the integer part of the reciprocal of the magnification is 0, the seamless pixel processing unit outputs pixel data of the image after the enlargement process performed on the input image,
When the integer part of the reciprocal of the magnification is not 0, the seamless pixel processing unit relates to an image processing apparatus that outputs pixel data of an image after reduction processing performed on the input image.

  According to the present invention, since the initial value can be set, the result of cumulative addition of the reciprocal of the magnification based on the initial value can be changed according to the initial value. It is possible to prevent deterioration of the pixel after processing due to enhancement of a pixel that has not been subjected to.

  Further, according to the present invention, it is not necessary to set the number of pixels of the pre-processed image and the post-processed image for the purpose of obtaining the magnification in order to perform the image enlargement process and the reduction process. Can be adopted. Furthermore, the image enlargement process or the reduction process can be performed based on the integer part of the reciprocal of the magnification that is cumulatively added to perform the image enlargement or reduction process. Therefore, it is possible to seamlessly execute image enlargement and reduction processing according to the set magnification without specifying enlargement or reduction for the image processing apparatus. For this reason, for example, as shown in FIG. 20B, the code amount of firmware for controlling the image processing apparatus can be reduced.

The present invention also provides
An image processing method for performing enlargement and reduction processing of an input image,
A reciprocal of the magnification for enlarging or reducing the input image is set in the magnification register, and an initial value is set in the initial value setting register.
After adding the reciprocal of the magnification to the initial value, cumulatively adding the reciprocal of the magnification,
When the integer part of the reciprocal of the magnification set in the magnification register is 0, the pixel data of the image after the enlargement process performed on the input image is output,
When the integer part of the reciprocal of the magnification is not 0, based on the cumulative addition result, it is specified whether or not to decimate in units of pixels constituting the input image, and reduction performed on the input image The present invention relates to an image processing method for outputting pixel data of a processed image.

In the image processing method according to the present invention,
When the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result is not 0,
Update pixel data to be processed, and generate pixel data of the image after the enlargement process by performing a product-sum operation on the updated pixel data and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result And
When the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result is 0,
The pixel data of the image after the enlargement process is generated by performing a product-sum operation on the previous pixel data and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result without updating the pixel data to be processed. And
When the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result is not 0,
Decrement the cumulative addition result,
When the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result is 0,
A value obtained by decrementing the reciprocal of the magnification is added to the cumulative addition result, and the reduction processing is performed by performing a product-sum operation on the pixel data to be processed and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result. Later pixel data can be generated.

The present invention also provides
A pixel data input interface to which pixel data of an input image is input;
A first scaler circuit for performing enlargement or reduction processing of the input image input via the pixel data input interface;
A frame buffer for storing the processed data of the first scaler circuit;
A second scaler circuit for performing enlargement or reduction processing of an image represented by pixel data read from the frame buffer;
A driver interface that performs an interface process for outputting the processed data of the second scaler circuit to a display driver that drives the display panel;
At least one of the first and second scaler circuits is:
A horizontal image processing unit for performing enlargement or reduction processing on pixel data in the horizontal direction of the image;
A vertical image processing unit that performs enlargement or reduction processing on pixel data in the vertical direction of the image,
At least one of the horizontal image processing unit and the vertical image processing unit is:
The present invention relates to a display controller including any of the image processing apparatuses described above.

  ADVANTAGE OF THE INVENTION According to this invention, the display controller which can avoid the production | generation of the image which deteriorates by mixing the pixel which uses the pixel data of an original image as it is, and the pixel interpolated from the pixel data of an original image can be provided.

  In addition, according to the present invention, it is possible to provide a display controller capable of reducing the circuit scale and executing image enlargement / reduction processing according to a set magnification without specifying enlargement / reduction.

The present invention also provides
A display panel;
A display controller as described above;
The present invention relates to an electronic device including a display driver that drives the display panel based on image data supplied by the display controller.

  ADVANTAGE OF THE INVENTION According to this invention, the electronic device which can avoid the production | generation of the image which deteriorates by mixing the pixel which uses the pixel data of an original image as it is, and the pixel interpolated from the pixel data of an original image can be provided.

  In addition, according to the present invention, it is possible to provide an electronic device that can execute an image enlargement / reduction process according to a set magnification without reducing the circuit scale and designating enlargement / reduction.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Image Processing Device FIG. 1 is a block diagram showing an outline of the configuration of an image processing device according to this embodiment.

  The image processing apparatus 100 performs image enlargement processing and reduction processing on pixel data of an input image. More specifically, the image processing apparatus 100 includes a magnification setting register 10 and a seamless pixel processing unit 20. In the magnification setting register 10, the reciprocal of the magnification for enlarging or reducing the input image is set. The seamless pixel processing unit 20 performs the enlargement process or the reduction process on the pixel data of the input image according to the inverse of the magnification set in the magnification setting register 10 without specifying the enlargement or reduction. Output pixel data.

  When the integer part of the reciprocal of the magnification set in the magnification setting register 10 is 0, the seamless pixel processing unit 20 outputs pixel data of the image after the enlargement process performed on the input image. When the integer part of the reciprocal of the magnification is not 0, the seamless pixel processing unit 20 outputs the pixel data of the image after the reduction process performed on the input image.

  In this way, the firmware for controlling the image processing apparatus 100 does not need to set the operation mode for specifying the enlargement or reduction of the image while specifying the magnification. Therefore, as shown in FIG. 20B, the amount of firmware code can be greatly reduced.

  The seamless pixel processing unit 20 of the image processing apparatus 100 can include an accumulator 30 that cumulatively adds the reciprocal of the magnification, and an initial value setting register 32 in which an initial value of the accumulator 30 is set. The accumulator 30 adds the reciprocal of the magnification set in the magnification setting register 10 to the initial value set in the initial value setting register 32, and cumulatively adds the reciprocal of the magnification to the addition result. Then, the seamless pixel processing unit 20 (accumulator 30) outputs a valid signal “valid” that specifies whether or not to decimate in units of pixels constituting the input image based on the cumulative addition result of the accumulator 30 during the reduction process. be able to.

  FIG. 2 shows an example of the relationship between the processed pixel data and the valid signal valid.

  The valid signal “valid” changes to H level or L level for each pixel data of each pixel. For example, it indicates that pixel data during a period when the valid signal valid is at the H level is valid, and pixel data during a period when the valid signal valid is at the L level is invalid. Therefore, the circuit that has received the processed pixel data and the valid signal valid from the image processing apparatus 100 can determine whether the pixel data of each pixel should be thinned out by the reduction process based on the valid signal valid. Therefore, in this circuit, pixel data determined to be thinned out based on the valid signal valid can be thinned out from the processed pixel data.

  In FIG. 1, the seamless pixel processing unit 20 can further include a filter calculation unit 40. The filter calculation unit 40 performs a filtering process on the pixel data of the input image using a filter coefficient corresponding to the cumulative addition result of the accumulator 30. The pixel data after the filter process becomes the pixel data after the enlargement or reduction process. That is, the filter calculation unit 40 performs a filter process for interpolating between one or a plurality of pixels with respect to the pixel data of the pixel after the enlargement or reduction process. Therefore, it is desirable that the seamless pixel processing unit 20 further includes a coefficient look-up table (LUT) 50. In this coefficient LUT 50, filter coefficients for performing filter processing are set in advance. Then, by causing the filter coefficient corresponding to the cumulative addition result of the accumulator 30 to be read from the coefficient LUT 50, it is possible to prevent image quality deterioration of the image after the filter processing of the filter calculation unit 40.

1.1 Image Enlargement Process and Reduction Process The contents of the image enlargement process and the reduction process in the present embodiment will be specifically described below.

  FIG. 3 is an explanatory diagram of image enlargement processing and reduction processing in the present embodiment.

  FIG. 3 shows a case where the initial value set in the initial value setting register 32 is “0”. FIG. 3 illustrates a case where processing is performed on these pixels when pixels of the original image are arranged in the horizontal direction (horizontal scanning direction) of the image, but the original image is aligned in the vertical direction (vertical scanning direction) of the image. The same applies when processing is performed on these pixels when the pixels of the image are arranged.

In FIG. 3, horizontal pixels P ₁ , P ₂ , P ₃ , P ₄ , P ₅ ,... Of the original image are arranged in a state where the dot pitch between the pixels is normalized. That is, the distance between each pixel in the horizontal direction of the original image is 1.

In the enlargement process, pixels P _Z1 , P _Z2 ,... Of the image after the enlargement process are generated for the pixels P ₁ , P _{2 ,.} The pixels P _Z1 , P _Z2 ,... Of the image after the enlargement process are not thinned out.

On the other hand, in the reduction process, the pixel _P 1 of the original _{image, P} 2, to ..., pixel _{P S1, P} S2 of the image after the enlargement processing, ... are generated. Since any of the pixels P _S1 , P _S2 ,... Of the image after the reduction process is thinned out, whether or not each of the pixels P _S1 , P _S2 ,. Is specified. As a result, the valid signal valid shown in FIG. 2 is generated.

  Here, a case where the original image is enlarged by 1.5 times will be described. In this case, the reciprocal of the magnification is 2/3 (= 1 / 1.5).

For example, to match the pixel P _Z1 of the image after enlargement processing and the pixel P ₁ of the original image. That is, the position of the pixel P _z1 is 0, and the pixel data of the pixel P _{z1 is} the pixel data of the pixel P ₁ of the original image. This pixel data may be data including gradation data of each RGB color component, or data including a luminance component and two color difference components.

Thereafter, 2/3 is cumulatively added to the assigned value of the pixel _PZ1 .

As a result, first, a value obtained by subtracting 1 from the grant value of the pixel P _Z2 becomes the position of the pixel P _z2. That is, the position of the pixel P _z2 is between the pixels P ₁ and P ₂ of the original image. Therefore, as the interpolation pixel pixel P _Z2, the pixel data is, for example a value obtained by interpolating the pixel data of the pixel P _1, P _2.

  FIG. 4 is an explanatory diagram of pixel data of the interpolation pixel.

In FIG. 4, pixel data of the interpolation pixel P _c is obtained when the position of the processed interpolation pixel P _c with respect to the original image is between the pixels P _a and P _b of the original image. If the position of the interpolation pixel P _c is separated from the pixel Pa by _a distance d (0 ≦ d ≦ 1), the dot pitch between the pixels P _a and P _b is normalized. position of _c will be away from the pixel _{P b} by a distance (1-d).

Here, when the pixel data of the pixel P is represented as D (P), the pixel data D (P _c ) of the interpolation pixel P _c is obtained by the following equation.

D (P _c ) = (1−d) × D (P _a ) + d × D (P _b ) (1)
Accordingly, the pixel data of the interpolation pixel is obtained by a product-sum operation between d as an interpolation coefficient and the pixel data of the original image.

Since the dot pits are normalized, the distance d corresponds to the decimal part of the result of accumulatively adding the reciprocal magnification to obtain the position of the interpolation pixel _Pc . This decimal part is associated with an interpolation coefficient when performing interpolation processing of pixel data.

  Here, the pixel data of the pixel of the processed image is described as being interpolated with the pixel data of two pixels of the original image. However, even if the pixel data of three or more pixels of the original image is interpolated Good.

Since the pixel data of the interpolation pixel is thus obtained, the pixel data D (P _z2 ) of the pixel P _z2 in FIG. 3 is obtained from the pixel data of the pixels P1 and P2 of the original image by the following formula.

D (P _Z2 ) = (1-2 / 3) × D (P ₁ ) + 2/3 × D (P ₂ ) (2)
Subsequently, since the _assigned value of the pixel P _z3 is 2/3 + 2/3 = 1 + 1/3, the pixel data D (P _z3 ) of the pixel P _z3 is obtained from the pixel data of the pixels P2 and P3 of the original image. It is calculated by the formula.

D (P _Z3 ) = (1-1 / 3) × D (P ₂ ) + 1/3 × D (P ₃ ) (3)
Thereafter, similarly, the pixel data of the pixel P _z4 becomes the pixel data of the pixel P ₃ of the original image, and the pixel data of the pixel P _z5 is the value interpolated with the pixel data of the pixels P ₃ and P ₄ of the original image. Become.

  As described above, with the dot pitch between pixels normalized, based on the pixel data of the pixels of the original image and the coefficient corresponding to the decimal part of the result of accumulatively adding the reciprocal of the magnification, Image pixel data can be generated.

  Next, a case where the original image is reduced 2/3 times will be described. In this case, the reciprocal of the magnification is 1.5 (= 1 / (2/3)).

For example, the pixel P _S1 of the image after the reduction process is matched with the pixel P _{1 of the} original image. That is, the position of the pixel P _S1 is 0, and the pixel data of the pixel P _{S1 is} the pixel data of the pixel P ₁ of the original image.

Thereafter, the assigned value of the pixel _PS1 is subtracted by 1, or (1.5-1) is added. In the case of the reduction process, since the reciprocal magnification is a value larger than 1, every time the value assigned to the processed pixel is decremented, interpolation is performed between the next pixels. As a result, when the integer part of the assigned value of the processed pixel is 0, the processed pixel is validated and is interpolated with the pixel data of the pixel of the original image as described above. Then, in order to obtain the next interpolation pixel, (1.5-1) is added to the assigned value of the pixel.

  On the other hand, when the integer part of the assigned value of the processed pixel is 1, the processed pixel is invalidated and the assigned value of the pixel is subtracted by 1 in order to obtain the next interpolation pixel.

Thus, in FIG. 3, first grant value of the pixel _{P S1} is 0, since the pixel is valid, the grant value of the pixel _{P S1} is (1.5-1) is added. As a result, the assigned value of the pixel P _S2 is 0.5, and this value is the position of the pixel P _S2 . That is, the position of the pixel _{P S2} is a between the pixel _P 2, _{P 3} of the original image. For this reason, the pixel P _S2 is an interpolation pixel, and the pixel data is a value obtained by interpolating the pixel data of the pixels P ₂ and P ₃ , for example. Here, it corresponds to the case where d is 0.5 in FIG.

Then, grant value of the pixel _{P S3} becomes 1.0 (= 0.5 + 1.5-1). Since the integer part of this assigned value is 1, the pixel _PS3 is thinned out.

The grant value of the pixel _{P S4} becomes 0.0 (= 1.0-1). For this reason, the pixel _PS4 is effective.

  As described above, the pixel data of the image after the reduction process is obtained by accumulating the reciprocal of the magnification while decrementing the assigned value of the processed pixel while the dot pitch between the pixels is normalized. It is possible to determine whether to generate and process pixel data after thinning.

  FIG. 5 shows an explanatory diagram of an image enlargement process and a reduction process in the present embodiment when an initial value is set in the initial value setting register 32.

  However, in FIG. 5, the same parts as those in FIG. In FIG. 5, it is assumed that the initial value IV set in the initial value setting register 32 is “1/6”. FIG. 5 illustrates a case where processing is performed on these pixels when pixels of the original image are arranged in the horizontal direction (horizontal scanning direction) of the image. The same applies when processing is performed on these pixels when the pixels of the image are arranged.

  Here, a case where the original image is enlarged by 1.5 times will be described. In this case, the reciprocal of the magnification is 2/3 (= 1 / 1.5).

For example, the position of the pixel P _Z1 of the image after the enlargement process is 1/6, and the position of the pixel P _z1 is between the pixels P ₁ and P ₂ of the original image. Therefore, as the interpolation pixel pixel P _Z1, the pixel data is, for example a value obtained by interpolating the pixel data of the pixel P _1, P _2.

Thereafter, 2/3 is cumulatively added to the assigned value of the pixel _PZ1 .

Consequently, the position is next to 5/6 of the pixel _{P Z2,} the position of the pixel _{P z2,} be between the pixel _P 1, _{P 2} of the original image. Therefore, as the interpolation pixel pixel P _Z2, the pixel data is, for example a value obtained by interpolating the pixel data of the pixel P _1, P _2.

Subsequently, 2/3 is cumulatively added to the assigned value of the pixel _PZ2 . As a result, the position of the pixel P _Z3 is 3/2, and the position of the pixel P _z3 is between the pixels P ₂ and P ₃ of the original image. Therefore, a value obtained by subtracting 1 from the grant value of the pixel _{P Z3} becomes the position of the pixel _{P z3.} Therefore, as the interpolation pixel pixel P _Z3, the pixel data is, for example a value obtained by interpolating the pixel data of the pixel P _2, P _3.

Similarly, the pixels P _z4 and P _z5 are interpolated by the pixel data of the original image.

  Next, a case where the original image is reduced 2/3 times will be described. In this case, the reciprocal of the magnification is 1.5 (= 1 / (2/3)).

For example, the position of the pixel P _S1 of the image after the reduction process is 1/6, and the pixel data of the pixel P _S1 is pixel data interpolated by the pixels P ₁ and P2 of the original image.

Thereafter, the assigned value of the pixel _PS1 is subtracted by 1, or (1.5-1) is added.

Thus, in FIG. 5, grant value of the pixel _{P S1} is 1/6, because the pixel is valid, the grant value of the pixel _{P S1} is (1.5-1) is added. As a result, the assigned value of the pixel P _S2 is 2/3, and this value is the position of the pixel P _S2 . That is, the position of the pixel _{P S2} is a between the pixel _P 2, _{P 3} of the original image. For this reason, the pixel P _S2 is an interpolation pixel, and the pixel data is a value obtained by interpolating the pixel data of the pixels P ₂ and P ₃ , for example.

Subsequently, the assigned value of the pixel _PS3 is 7/6. Since the integer part of this assigned value is 1, the pixel _PS3 is thinned out.

The assigned value of the pixel _PS4 is 1/6 (= 7 / 6-1). For this reason, the pixel _PS4 is effective.

  As described above, by giving an initial value when performing cumulative addition, the interpolation ratio of each pixel data of the image after the enlargement process or the reduction process can be changed. As a result, as shown in FIG. 19, in the processed image, it is possible to avoid a situation where one pixel data of the original image is used as it is and one interpolated from a plurality of pixel data of the original image. . As a result, it is possible to prevent a striped pattern from appearing in the processed image and to prevent deterioration of the processed image.

  Hereinafter, a hardware configuration example of the image processing apparatus 100 that realizes such an image enlargement process and reduction process will be described.

1.2 Accumulator FIG. 6 is a block diagram showing a configuration example of the accumulator 30 shown in FIG.

  Here, as shown in FIG. 7, it is assumed that the magnification setting register 10 has a 12-bit configuration, integer data is set in the upper 3 bits, and decimal data is set in the lower 9 bits.

  Accumulator 30 includes a mode determination unit 60. The mode determination unit 60 outputs a mode signal MODE corresponding to the set value of the upper 3 bits of the 12-bit data set in the magnification setting register 10. More specifically, when the set value of the upper 3 bits is 0, the mode determination unit 60 sets the mode signal MODE to L level and designates an enlargement processing mode for performing enlargement processing. On the other hand, when the set value of the upper 3 bits is not 0, the mode determination unit 60 sets the mode signal MODE to H level and designates a reduction processing mode for performing reduction processing.

  The accumulator 30 includes a 12-bit magnification accumulator register 62. The magnification accumulator register 62 is loaded with the initial value IV [11: 0] from the initial value setting register 32 at the time of initialization. The magnification accumulator register 62 receives the cumulative addition result of the reciprocal of the magnification in synchronization with a change point of a pixel clock or line clock (not shown). The pixel clock is a clock in units of pixels arranged in the horizontal direction, and the line clock is a clock in units of line in which one horizontal scanning period is one line.

  The adder 64 adds the reciprocal of the magnification set in the magnification setting register 10 and the value HACCum [8: 0] stored in the magnification accumulator register 62, and outputs the result as AccAddData [11: 0]. A logical OR operation result between AccAddData [9] and the mode signal MODE is output as the shift enable signal ShiftEnable. Therefore, in the reduction processing mode, the shift enable signal ShiftEnable is fixed at the H level. This shift enable signal ShiftEnable is a signal for enabling control of a shift operation for updating pixel data to be processed by the filter calculation unit 40. Therefore, in the enlargement processing mode, when the integer part of HACCum [11: 0] that is the cumulative addition result is not 0, the shift enable signal ShiftEnable becomes H level, and the pixel data to be processed by the filter operation unit is updated. When the integer part of HACCum [11: 0] is 0, the shift enable signal ShiftEnable becomes L level, and the pixel data to be processed by the filter operation part is not updated.

  The 9-bit data of AccAddData [8: 0] is output as 12-bit data by adding “000” to the upper 3 bits in the upper bit adding unit 66.

  On the other hand, the value HACCum [11: 9] stored in the magnification accumulator register 62 is output as 12-bit data by adding “000000000000” to the lower bits in the lower bit adding unit 68. The 12-bit data is added to AccAddData [11: 0] in the adder 70, and then the value of the integer part of the addition result of the adder 70 is decremented in the decrementer 72 and supplied to the selector 74.

  The value HACCum [11: 0] stored in the magnification accumulator register 62 is decremented by the decrementer 76, and the value of the integer part of HACCum [11: 0] is supplied to the selector 74.

  The integer part analysis unit 78 detects whether or not the value HACCum [11: 9] stored in the magnification accumulator register 62 is zero. More specifically, when the integer part analysis unit 78 detects that HACCum [11: 9] is 0, it outputs an H level detection signal, and detects that HACCum [11: 9] is not 0. At this time, an L level detection signal is output. The logical sum operation result of this detection signal and the inverted signal of the mode signal MODE is output as a valid signal valid. Therefore, in the enlargement processing mode, the valid signal valid is fixed at the H level. HACCum [8: 6] is the address LUTadr of the coefficient LUT50. In FIG. 6, only 3 bits are generated as the address of the coefficient LUT 50, but the number of bits is not limited to this. Therefore, it is only necessary to generate the address of the coefficient LUT 50 based on at least a part of the decimal part of the cumulative addition result.

  The detection signal from the integer part analysis unit 78 becomes a selection control signal for the selector 74. That is, the selector 74 selectively outputs the output of the decrementer 76 when the detection signal of the integer part analysis unit 78 is L level. On the other hand, the selector 74 selects and outputs the output of the decrementer 72 when the detection signal of the integer part analysis unit 78 is at the H level. Therefore, in the reduction processing mode, the integer part of the value stored in the magnification accumulator register 62 is decremented until HACCum [11: 9] is not zero. The output of the selector 74 is supplied to the selector 80.

  The selector 80 selects and outputs the output of the upper bit adding unit 66 when the mode signal MODE is L level. The selector 80 selects and outputs the output of the selector 74 when the mode signal MODE is at the H level. The output of the selector 80 is stored in the magnification accumulator register 62.

  Next, the operation of the accumulator 30 shown in FIG. 6 will be described.

  FIG. 8 schematically shows the operation in the enlargement processing mode of the accumulator 30 in FIG.

  In FIG. 8, the same parts as those of FIG.

  When the integer part of the reciprocal of the magnification set in the magnification setting register 10 is 0, the mode signal MODE becomes L level as described above. The adder 64 adds the reciprocal of the magnification and the value HACCum [8: 0] stored in the magnification accumulator register 62. The shift enable signal ShiftEnable is generated by the ninth bit (HACCum [9]) of the addition result. The shift enable signal ShiftEnable is generated based on HACCum [9] because the reciprocal of the multiply-added magnification is smaller than 1 in the enlargement processing mode, so if the least significant bit of the integer part of the cumulative addition result is referred to, This is because it can be determined whether or not the integer part of the addition result is zero.

  The addition result is stored again in the magnification accumulator register 62. Of the values stored in the magnification accumulator register 62, HACCum [8: 6] is output as an address LUTadr for designating the coefficient set in the coefficient LUT50.

  FIG. 9 schematically shows the operation in the reduction processing mode of the accumulator 30 in FIG.

  In FIG. 9, the same parts as those in FIG.

  When the integer part of the reciprocal of the magnification set in the magnification setting register 10 is not 0, the mode signal MODE becomes H level as described above. Adders 64 and 70 add the inverse of the magnification and the value HACCum [11: 0] stored in the magnification accumulator register 62. The value of the integer part of the addition result is decremented by the decrementer 72. On the other hand, the value of the integer part of the value HACCum [11: 0] stored in the magnification accumulator register 62 is decremented by the decrementer 76. Then, depending on whether or not the value HACCum [11: 9] stored in the magnification accumulator register 62 is 0, the output of one of the decrementers 72 and 76 is selected and taken into the magnification accumulator register 62 again.

  HACCum [8: 6] of the magnification accumulator register 62 is output as the address LUTadr of the coefficient LUT50. The valid signal valid is output based on HACCum [11: 9] of the magnification accumulator register 62.

  Therefore, in the reduction processing mode, a valid signal “valid” designating whether or not to thin out pixel by pixel can be output based on the cumulative addition result in the magnification accumulator register 62.

1.3 Coefficient LUT
FIG. 10 is a block diagram showing a configuration example of the coefficient LUT 50 shown in FIG.

The coefficient LUT 50 can include an address decoder 52 and a coefficient memory 54. The address decoder 52 decodes the address LUTadr from the accumulator 30 and designates any storage area of the coefficient memory 54. The coefficient memory 54 holds, for example, 8 (= 2 ³ ) coefficient groups, and outputs the coefficient group designated by the address decoder 52 to the filter calculation unit 40.

  In FIG. 10, the coefficient memory 54 has been described as holding eight sets of coefficients, but it goes without saying that the present embodiment is not limited to the number of sets.

1.4 Filter Operation Unit FIG. 11 is a block diagram showing a configuration example of the accumulator 30, the coefficient LUT 50, and the filter operation unit 40 in FIG.

  11, the same parts as those in FIGS. 1, 6, and 10 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In FIG. 11, the filter calculation unit 40 performs a 4-tap filter process, but the present embodiment is not limited to the number of taps.

  The filter operation unit 40 includes a data buffer and four flip-flops (FF). The four flip-flops constitute a shift register connected in series, and a clock CLK (pixel clock or line clock) is commonly supplied to each flip-flop. When the shift enable signal ShiftEnable from the accumulator 30 becomes H level, pixel data is read from the data buffer, and a shift operation is performed in synchronization with the clock CLK.

  The output of each flip-flop is input to a multiplier. The coefficient LUT 50 outputs coefficient groups h0, h1, h2, and h3 corresponding to the address LUTadr from the accumulator 30. Each coefficient of the coefficient group output corresponding to the address LUTadr is supplied to each multiplier.

  The output of each multiplier is supplied to an adder, and the output of the adder becomes pixel data after interpolation. This interpolated pixel data is pixel data after enlargement processing or reduction processing.

  Here, if the output of each flip-flop is g0, g1, g2, g3, and the output of the adder is D (P), D (P) is expressed by the following equation.

D (P) = g0 × h0 + g1 × h1 + g2 × h2 + g3 × h3 (4)
When the integer part of the reciprocal of the magnification set in the magnification setting register 10 is 0, the image processing apparatus 100 performs an enlargement process on the pixel data of the input image, and the integer part of the reciprocal of the magnification is 0. If not, the reduction process can be performed on the pixel data of the input image.

  FIG. 12 is an explanatory diagram illustrating an example of the enlargement process of the image processing apparatus 100 according to the present embodiment.

  FIG. 12 shows an example in which the enlargement magnification is 2.5 (the reciprocal of the magnification is 0.4) and the initial value is 0. In the enlargement process, all the pixels after the process are effective.

  That is, when the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result of the accumulator 30 is not 0, the image processing apparatus 100 shifts the shift enable signal ShiftEnable as described with reference to FIGS. Is changed to the H level, and the shift operation of the shift register of the filter operation unit 40 in FIG. By doing so, the pixel data to be processed by the filter calculation unit 40 can be updated. Then, a product-sum operation is performed on the pixel data after the update and a coefficient corresponding to at least a part (HACCum [8: 6] in FIG. 8) of the fractional part of the cumulative addition result of the accumulator 30, and the image after the enlargement process The pixel data can be generated.

  Further, when the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result of the accumulator 30 is 0, the image processing apparatus 100 sets the shift enable signal ShiftEnable to L as described with reference to FIGS. By changing the level, the shift operation of the shift register of the filter operation unit 40 in FIG. 11 is set to a disabled state. By doing so, it is not necessary to update the pixel data to be processed by the filter calculation unit 40. Then, a product-sum operation is performed on the pixel data used last time in the filter operation unit 40 and a coefficient corresponding to at least a part of the fractional part (HACCum [8: 6] in FIG. 8) of the accumulator 30 cumulative addition result. Pixel data of the image after the enlargement process can be generated.

  Accordingly, in FIG. 12, when the cumulative addition results are 1.2 and 1.0 (E1, E2, E3, E4), the shift enable signal ShiftEnable is changed to H level, and the pixel data after the shift operation is changed. Pixel data after interpolation is generated. In other cases, the shift enable signal ShiftEnable is changed to the L level, and post-interpolation pixel data is generated using the coefficient corresponding to the position of the new interpolation pixel with respect to the previous pixel data to be processed. ing.

  It goes without saying that the position of the interpolation pixel can be changed by setting the initial value to a value other than zero.

  FIG. 13 is an explanatory diagram illustrating an example of a reduction process of the image processing apparatus 100 according to the present embodiment.

  FIG. 13 shows an example in which the reduction magnification is 0.4 (the reciprocal of the magnification is 2.5) and the initial value is 0. In the reduction process, the shift enable signal ShiftEnable is always at the H level.

  That is, when the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result of the accumulator 30 is not 0, the image processing apparatus 100 changes the valid signal valid to the L level to change the processed pixel. 9, and only the decrementer 76 decrements the cumulative addition result (its integer part) as shown in FIG. 9, and does not update the output of the filter operation unit 40.

  Further, when the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result of the accumulator 30 is 0, the image processing apparatus 100 adds the reciprocal of the magnification and the cumulative addition result (output of the accumulator 30). The integer part of the result is decremented by the decrementer 72. Then, pixel data of the image after the reduction process can be generated by performing a product-sum operation on the pixel data to be processed by the filter calculation unit 40 and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result.

  Therefore, in FIG. 13, when the cumulative addition result is 1.5, 2.0, or 1.0 (F1, F2, F3), the valid signal valid is changed to the L level. In other cases, the valid signal “valid” is changed to the H level, and pixel data after interpolation is generated for the pixel data after the shift operation.

  It goes without saying that the position of the interpolation pixel can be changed by setting the initial value to a value other than zero.

  As described above, the image processing apparatus 100 according to the present embodiment can generate pixel data of an image obtained by enlarging or reducing the input image according to the inverse of the magnification set in the magnification setting register 10. The image processing apparatus 100 can eliminate the need for a divider for obtaining the reciprocal of the magnification. Further, it is not necessary to compare the cumulative addition result of the reciprocal of the magnification with the count value of the pixel counter. Therefore, the number of bits used in the pixel counter is not increased, and the screen size of the electro-optical device can be increased without being limited by the number of bits of the pixel counter.

2. Display Controller Next, a display controller to which the image processing apparatus 100 according to this embodiment is applied will be described.

  FIG. 14 is a block diagram showing a configuration example of a display controller to which the image processing apparatus 100 according to this embodiment is applied.

The display controller 200 includes a camera interface (Interface: I / F) (pixel data input I / F in a broad sense) 210, first and second scaler circuits 220 and 230, a frame buffer 240, RGB I / F ( In a broad sense, pixel data of the input image is input to the camera I / F 210 including the output I / F) 250. More specifically, pixel data of an image from a camera module incorporating a CCD camera or a CMOS camera is input to the camera I / F 210. The camera I / F 210 performs interface processing of the pixel data (reception processing with the camera module and signal buffering), and outputs the pixel data after the interface processing to the first scaler circuit 220.

  The first scaler circuit 220 performs enlargement or reduction processing on the pixel data of the input image from the camera I / F 210.

  The frame buffer 240 stores, for example, pixel data for at least one frame (one screen) of the electro-optical device driven by a display driver connected to the RGB I / F 250. Data processed by the first scaler circuit 220 is stored in the frame buffer 240.

  The second scaler circuit 230 performs enlargement or reduction processing of the image represented by the pixel data read from the frame buffer 240.

  The RGB I / F 250 performs interface processing for outputting data after processing by the second scaler circuit 230. The RGB I / F 250 performs pixel data interface processing (transmission processing with a display driver and signal buffering) from the second scaler circuit 230, and displays RGB format pixel data after the interface processing (not shown). Output to the driver. The RGB I / F 250 includes, for example, a synchronization signal generation circuit, and a display synchronization signal for driving the electro-optical device (vertical synchronization signal VSYNC defining one vertical scanning period which is a scanning period of one frame, one horizontal scanning period Can be generated and supplied to the display driver. At this time, the RGB I / F 250 synchronizes the pixel data of each frame with the vertical synchronization signal and outputs each pixel data in synchronization with the dot clock.

  At least one of the first and second scaler circuits 220 and 230 includes a horizontal image processing unit that performs enlargement or reduction processing on the pixel data in the horizontal direction of the image, and pixel data in the vertical direction of the image. And a vertical direction image processing unit that performs enlargement or reduction processing. Further, at least one of the horizontal direction image processing unit and the vertical direction image processing unit includes the image processing apparatus 100 in the present embodiment.

  The display controller 200 can output pixel data obtained by converting the output of the second scaler circuit 230 into YUV format in the same manner as pixel data in RGB format. Therefore, the display controller 200 can include a YUVI / F270. The YUV I / F 270 performs pixel data interface processing (transmission processing with the CRT device and signal buffering) from the second scaler circuit 230, and the YUV format pixel data after the interface processing is not shown. Output to the device.

  The display controller 200 can also include a JPEG circuit 280 that performs compression processing or decompression processing on the data stored in the frame buffer 240. The JPEG circuit 280 can read the data stored in the frame buffer 240, perform compression processing or decompression processing according to the JPEG standard, and write the processed data back to the frame buffer 240.

  Further, the display controller 200 can include a host I / F 290. Data from a host (not shown) is input to the host I / F 290. At this time, the host I / F 290 performs interface processing (reception processing with the host and signal buffering), and supplies the data after the interface processing to the frame buffer 240. The data read from the frame buffer 240 can be supplied to the host via the host I / F 290. In this case, the host I / F 290 performs interface processing (transmission processing with the host and signal buffering), and outputs the data after the interface processing to the host.

  FIG. 15 is a block diagram showing a configuration example of the first scaler circuit 220 shown in FIG.

  15, the same parts as those in FIG. 14 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Each part of the first scaler circuit 220 in FIG. 15 operates in synchronization with the system clock. Pixel data input as external input data via the camera I / F 210 is buffered in the input buffer 300 in synchronization with an external clock from the camera I / F 210.

  The clock generation circuit 302 generates a shift clock whose mask is controlled based on the pixel shift based on the pixel shift and a pixel clock whose mask is controlled based on the pixel valid.

  The first scaler circuit 220 performs an enlargement / reduction process on the pixel data in the vertical direction of the input image, and an enlargement / reduction process on the pixel data in the horizontal direction of the input image. And a horizontal image processing unit 320 for performing.

  The vertical image processing unit 310 includes a vertical magnification setting register (not shown), a vertical scaling circuit 312, and a vertical accumulator circuit 314. The vertical magnification setting register (not shown) has the function of the magnification setting register 10 of FIG. The vertical scaling circuit 312 has the functions of the coefficient LUT 50 and the filter calculation unit 40 in FIG. The vertical accumulator circuit 314 has the function of the accumulator 30 of FIG. A host (not shown) sets the reciprocal of the magnification in the vertical direction of the image in the vertical magnification setting register. Further, a host (not shown) sets the initial value of cumulative addition of the vertical accumulator circuit 314 in a vertical accumulator circuit initial value setting register (not shown). This initial value is supplied to the vertical accumulator circuit 314.

  The horizontal image processing unit 320 includes a horizontal magnification setting register (not shown), a horizontal scaling circuit 322, and a horizontal accumulator circuit 324. The horizontal magnification setting register (not shown) has the function of the magnification setting register 10 of FIG. The horizontal scaling circuit 322 has the functions of the coefficient LUT 50 and the filter calculation unit 40 in FIG. The horizontal accumulator circuit 324 has the function of the accumulator 30 of FIG. A host (not shown) sets the reciprocal of the horizontal magnification of the image in the horizontal magnification setting register. Further, a host (not shown) sets the initial value of cumulative addition of the horizontal accumulator circuit 324 in a horizontal accumulator circuit initial value setting register (not shown). This initial value is supplied to the horizontal accumulator circuit 324.

  The vertical accumulator circuit 314 cumulatively adds the reciprocal of the magnification set in the vertical magnification setting register, corresponds to the vertical interpolation coordinate that is the address of the coefficient LUT, the line valid corresponding to the valid signal valid, and the shift enable signal ShiftEnable. Output line shift. The vertical scaling circuit 312 performs a product-sum operation on the coefficient corresponding to the vertical interpolation coordinates and the pixel data from the input buffer 300 and outputs the result to the horizontal scaling circuit 322. The vertical scaling circuit 312 outputs the line valid to the horizontal scaling circuit 322 as a line enable.

  The horizontal accumulator circuit 324 cumulatively adds the reciprocal of the magnification set in the horizontal magnification setting register, corresponds to the horizontal interpolation coordinate that is the address of the coefficient LUT, the pixel valid corresponding to the valid signal valid, and the shift enable signal ShiftEnable. Output pixel shift.

  FIG. 16 shows the relationship between the pixel clock, pixel valid, and pixel data. FIG. 16 shows the relationship between the pixel clock and pixel data during the enlargement process, and the relationship between the pixel clock, pixel valid, and pixel data during the reduction process.

  In FIG. 15, the horizontal scaling circuit 322 performs a product-sum operation on the coefficient corresponding to the horizontal interpolation coordinate and the output data from the vertical scaling circuit 312, and outputs the operation result to the output buffer 304. The horizontal scaling circuit 322 outputs the pixel valid to the output buffer 304 as a line enable.

  The output buffer 304 stores output data from the horizontal scaling circuit 322 in synchronization with the pixel clock. At this time, only data for which line enable is active is stored in the output buffer 304.

  By doing so, the horizontal image processing unit 320 can perform the enlargement process or the reduction process on the pixel data validated during the reduction process by the vertical image processing unit 310 (always valid during the enlargement process). . Only the pixel data that has been validated by the horizontal image processing unit 320 during the reduction process (always valid during the enlargement process) is stored in the output buffer 304.

  The address generation circuit 306 generates a write address of the frame buffer 240 and generates a write enable to the frame buffer 240 based on the line valid from the vertical accumulator circuit 314 and the pixel valid from the horizontal accumulator circuit 324. can do.

  As a result, the pixel data stored in the output buffer 340 is stored in the frame buffer 240.

  FIG. 17 is a block diagram showing a configuration example of the second scaler circuit 230 shown in FIG.

  In FIG. 17, the same parts as those in FIG. Each part of the second scaler circuit 230 in FIG. 17 operates in synchronization with the system clock.

  Data read from the frame buffer 240 based on the address generated by the address generation circuit 400 is buffered in the input buffer 402.

  The clock generation circuit 404 generates a shift clock whose mask is controlled based on the pixel shift based on the pixel shift and a pixel clock whose mask is controlled based on the pixel valid.

  The second scaler circuit 230 includes a vertical image processing unit 410 that performs an enlargement or reduction process on vertical pixel data of an input image (an image represented by pixel data stored in the frame buffer 240), A horizontal image processing unit 420 that performs enlargement or reduction processing on the pixel data in the horizontal direction of the input image.

  The vertical image processing unit 410 includes a vertical magnification setting register (not shown), a vertical scaling circuit 412, and a vertical accumulator circuit 414. The vertical magnification setting register (not shown) has the function of the magnification setting register 10 of FIG. The vertical scaling circuit 412 has the functions of the coefficient LUT 50 and the filter calculation unit 40 of FIG. The vertical accumulator circuit 414 has the function of the accumulator 30 of FIG. A host (not shown) sets the reciprocal of the magnification in the vertical direction of the image in the vertical magnification setting register. A host (not shown) sets the initial value of cumulative addition of the vertical accumulator circuit 414 in a vertical accumulator circuit initial value setting register (not shown). This initial value is supplied to the vertical accumulator circuit 414.

  The horizontal image processing unit 420 includes a horizontal magnification setting register (not shown), a horizontal scaling circuit 422, and a horizontal accumulator circuit 424. The horizontal magnification setting register (not shown) has the function of the magnification setting register 10 of FIG. The horizontal scaling circuit 422 has the functions of the coefficient LUT 50 and the filter calculation unit 40 in FIG. The horizontal accumulator circuit 424 has the function of the accumulator 30 of FIG. A host (not shown) sets the reciprocal of the horizontal magnification of the image in the horizontal magnification setting register. A host (not shown) sets the initial value of cumulative addition of the horizontal accumulator circuit 424 in a horizontal accumulator circuit initial value setting register (not shown). This initial value is supplied to the horizontal accumulator circuit 424.

  The function of the vertical image processing unit 410 is the same as that of the vertical image processing unit 310 in FIG. The function of the horizontal image processing unit 420 is the same as that of the horizontal image processing unit 320 in FIG.

  The line shift from the vertical accumulator circuit 414 is supplied to the address generation circuit 400. The pixel shift from the horizontal accumulator circuit 424 is supplied to the address generation circuit 400. The address generation circuit 400 generates a read address for the frame buffer 240 based on the line shift and the pixel shift.

  The horizontal scaling circuit 422 performs a product-sum operation on the coefficient corresponding to the horizontal interpolation coordinate and the output data from the vertical scaling circuit 412, and outputs the operation result to the output buffer 406.

  The output buffer 406 stores output data from the horizontal scaling circuit 422 in synchronization with the pixel clock. At this time, only data for which line enable is active is stored in the output buffer 406.

  By doing so, the horizontal image processing unit 420 can perform the enlargement process or the reduction process on the pixel data validated during the reduction process by the vertical image processing unit 410 (always valid during the enlargement process). . Only the pixel data validated during the reduction process (always valid during the enlargement process) by the horizontal image processing unit 420 is stored in the output buffer 406.

  As a result, the pixel data stored in the output buffer 406 is output to the RGB I / F 250 or YUV I / F 270.

3. Electronic Device FIG. 18 is a block diagram illustrating a configuration example of an electronic device according to this embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device.

  The cellular phone 700 includes the display controller 200 of FIG. The mobile phone 700 includes a camera module 710. The camera module 710 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 200.

  Mobile phone 700 includes a display panel 630. A liquid crystal display panel can be used as the display panel 630. In this case, the display panel 630 is driven by the display driver 620. The display panel 630 includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels. The display driver 620 has a function of a scan driver that selects a scan line in units of one or a plurality of scan lines, and also has a function of a data driver that supplies a voltage corresponding to pixel data to the plurality of data lines.

  The display controller 200 is connected to the display driver 620 and supplies RGB format pixel data to the display driver 620. Conversion between the RGB format and the YUV format of the pixel data can be performed in the display controller 200.

  The host 720 is connected to the display controller 200. The host 720 controls the display controller 200. Further, the host 720 can supply the display controller 200 after demodulating the pixel data received via the antenna 722 by the modem 730. Based on this pixel data, the display controller 200 causes the display driver 620 to display on the display panel 630.

  The host 720 can instruct transmission to another communication device via the antenna 722 after the pixel data generated by the camera module 710 is modulated by the modem 730.

  The host 720 performs pixel data transmission / reception processing, imaging of the camera module 710, and display panel display processing based on operation information from the operation input unit 740.

  In FIG. 18, a liquid crystal display panel is described as an example of the display panel 630, but the present invention is not limited to this. The display panel 630 may be an electroluminescence or plasma display device, and can be applied to a display controller that supplies pixel data to a display driver that drives them. The display controller 200 may output YUV pixel data to a CRT device connected via an output terminal (not shown).

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a block diagram illustrating an outline of a configuration of an image processing apparatus according to an embodiment. The figure which shows an example of the relationship between the pixel data after a process, and a valid signal. Explanatory drawing of the expansion process and reduction process of an image in this embodiment. Explanatory drawing of the pixel data of an interpolation pixel. Explanatory drawing of the other example of the expansion process and reduction process of the image in this embodiment. The block diagram of the structural example of the accumulator of FIG. Explanatory drawing of the integer part and decimal part of the setting data of a magnification setting register. The figure which shows typically operation | movement of the expansion process mode of the accumulator of FIG. The figure which shows typically operation | movement of the reduction process mode of the accumulator of FIG. FIG. 2 is a block diagram of a configuration example of a coefficient LUT in FIG. 1. The block diagram of the structural example of the accumulator of FIG. 1, a coefficient LUT, and a filter calculating part. Explanatory drawing of an example of the expansion process of the image processing apparatus in this embodiment. Explanatory drawing of an example of the reduction process of the image processing apparatus in this embodiment. 1 is a block diagram of a configuration example of a display controller to which an image processing apparatus according to an embodiment is applied. FIG. 15 is a block diagram of a configuration example of a first scaler circuit in FIG. 14. The figure which shows the relationship between a pixel clock, pixel valid, and pixel data. FIG. 15 is a block diagram of a configuration example of a second scaler circuit in FIG. 14. 1 is a block diagram of a configuration example of an electronic device according to an embodiment. FIG. 10 is a schematic diagram illustrating an example of an image after enlargement processing or reduction processing in a conventional image processing apparatus. 1 is a block diagram of a configuration example of an electronic device according to an embodiment. 20A and 20B are explanatory diagrams of examples of firmware codes.

Explanation of symbols

10 magnification setting register, 20 seamless pixel processing unit, 30 accumulator,
32 initial value setting register, 40 filter operation unit, 50 coefficient LUT,
60 mode determination unit, 62 magnification accumulator register, 64, 70 adder,
66 upper bit adding section, 68 lower bit adding section, 72, 76 decrementer,
74, 80 selector, 78 integer analysis unit, 100 image processing device,
200 display controller, 210 camera I / F, 220 first scaler circuit,
230 second scaler circuit, 240 frame buffer, 250 RGB I / F,
270 YUV I / F, 280 JPEG circuit, 290 Host I / F

Claims (7)

An image processing apparatus for enlarging and reducing an input image,
A magnification register in which a reciprocal of a magnification for enlarging or reducing the input image is set;
An accumulator that cumulatively adds the reciprocal of the magnification;
An initial value setting register in which an initial value of the accumulator is set;
A seamless pixel processing unit that performs image enlargement or reduction processing based on the inverse of the magnification,
The accumulator is
After adding the reciprocal of the magnification to the initial value, cumulatively adding the reciprocal of the magnification,
When the integer part of the reciprocal of the magnification is 0, the seamless pixel processing unit outputs pixel data of the image after the enlargement process performed on the input image,
When the integer part of the reciprocal of the magnification is not 0, the seamless pixel processing unit outputs a valid signal that specifies whether or not to thin out the pixel unit constituting the input image based on the cumulative addition result of the accumulator. An image processing apparatus that outputs and outputs pixel data of an image after reduction processing performed on the input image. In claim 1,
The seamless pixel processing unit
A filter operation unit that performs a product-sum operation based on pixel data of the input image and an output of the accumulator to generate pixel data after the enlargement process or reduction process,
When the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result is not 0,
The pixel data to be processed by the filter operation unit is updated, and the image after the enlargement process is performed by performing a product-sum operation on the updated pixel data and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result Generate pixel data for
When the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result is 0,
The image after the enlargement processing by performing a product-sum operation on the previous pixel data and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result without updating the pixel data to be processed by the filter operation unit Generate pixel data for
When the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result is not 0,
While decrementing the integer part of the cumulative addition result, without updating the output of the filter operation unit,
When the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result is 0,
The integer part of the addition result of the reciprocal of the magnification and the output of the accumulator is decremented, and the product of the pixel data to be processed by the filter operation unit and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result An image processing apparatus that performs pixel operation to generate pixel data of the image after the reduction process. An image processing apparatus for enlarging and reducing an input image,
A magnification register in which a reciprocal of a magnification for enlarging or reducing the input image is set;
An accumulator that cumulatively adds the reciprocal of the magnification;
An initial value setting register in which an initial value of the accumulator is set;
A seamless pixel processing unit that performs image enlargement or reduction processing based on the inverse of the magnification,
The accumulator is
After adding the reciprocal of the magnification to the initial value, cumulatively adding the reciprocal of the magnification,
When the integer part of the reciprocal of the magnification is 0, the seamless pixel processing unit outputs pixel data of the image after the enlargement process performed on the input image,
The image processing apparatus, wherein when the integer part of the reciprocal of the magnification is not 0, the seamless pixel processing unit outputs pixel data of an image after reduction processing performed on the input image. An image processing method for performing enlargement and reduction processing of an input image,
A reciprocal of the magnification for enlarging or reducing the input image is set in the magnification register, and an initial value is set in the initial value setting register.
After adding the reciprocal of the magnification to the initial value, cumulatively adding the reciprocal of the magnification,
When the integer part of the reciprocal of the magnification set in the magnification register is 0, the pixel data of the image after the enlargement process performed on the input image is output,
When the integer part of the reciprocal of the magnification is not 0, based on the cumulative addition result, it is specified whether or not to decimate in units of pixels constituting the input image, and reduction performed on the input image An image processing method comprising outputting pixel data of a processed image. In claim 4,
When the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result is not 0,
Update pixel data to be processed, and generate pixel data of the image after the enlargement process by performing a product-sum operation on the updated pixel data and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result And
When the integer part of the reciprocal of the magnification is 0 and the integer part of the cumulative addition result is 0,
The pixel data of the image after the enlargement process is generated by performing a product-sum operation on the previous pixel data and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result without updating the pixel data to be processed. And
When the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result is not 0,
Decrement the cumulative addition result,
When the integer part of the reciprocal of the magnification is not 0 and the integer part of the cumulative addition result is 0,
A value obtained by decrementing the reciprocal of the magnification is added to the cumulative addition result, and the reduction processing is performed by performing a product-sum operation on the pixel data to be processed and a coefficient corresponding to at least a part of the decimal part of the cumulative addition result. An image processing method characterized by generating subsequent pixel data. A pixel data input interface to which pixel data of an input image is input;
A first scaler circuit for performing enlargement or reduction processing of the input image input via the pixel data input interface;
A frame buffer for storing the processed data of the first scaler circuit;
A second scaler circuit for performing enlargement or reduction processing of an image represented by pixel data read from the frame buffer;
A driver interface that performs an interface process for outputting the processed data of the second scaler circuit to a display driver that drives the display panel;
At least one of the first and second scaler circuits is:
A horizontal image processing unit for performing enlargement or reduction processing on pixel data in the horizontal direction of the image;
A vertical image processing unit that performs enlargement or reduction processing on pixel data in the vertical direction of the image,
At least one of the horizontal image processing unit and the vertical image processing unit is:
A display controller comprising the image processing apparatus according to claim 1. A display panel;
A display controller according to claim 6;
An electronic device comprising: a display driver that drives the display panel based on image data supplied by the display controller.

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