JP2011133605A - Apparatus and method for processing image, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus and electronic equipment for performing processing for stopping a line buffer in only an unnecessary amount when priority is given to power consumption by trade-off of image quality and the power consumption. <P>SOLUTION: The image processing apparatus for obtaining pixel data of magnified images of original images or reduced images of the original images includes: line buffers 52-56 for buffering the pixel data of a plurality of lines of the original images; a setting register for holding various settings for obtaining interpolation pixels of adjacent pixels in a horizontal direction or a vertical direction of the original images; and a vertical scaler 48 for magnifying or reducing the pixel data buffered in the line buffers 52-56 in the vertical direction on the basis of vertical interpolation information of the vertical direction indicating an interpolation processing method for obtaining each interpolation pixel from the setting register. The image processing apparatus stops at least one clock of the plurality of the lines of the line buffers 52-56 on the basis of mode selection signals from the setting register. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, an image processing method, and an electronic apparatus.

  2. Description of the Related Art In recent years, mobile devices such as mobile phones have been remarkably evolved and can be connected to a computer network such as the Internet. On the other hand, for example, a VGA (Video Graphics Array) size is adopted as a display panel of a portable device due to enlargement and high definition of the screen size of the display panel. Therefore, in order to display various contents as described above on the display panel, it is required that a recent portable device realize an image scaler function. With this scaler function, it is necessary to suppress the degradation of the image quality of the image after the scale processing as much as possible and generate an easy-to-see image.

  Thus, for example, Patent Document 1 discloses a technique that can generate pixel data of interpolated pixels obtained by interpolating an original image with an optimal interpolation method according to the characteristics of the image.

JP 2008-236522 A

  However, when performing such filtering, there is a problem that power consumption increases because a fixed line buffer is always used.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 An image processing apparatus for obtaining pixel data of an enlarged image of an original image or a reduced image of the original image, the line buffer for buffering pixel data of a plurality of lines of the original image, and the line Based on the pixel data buffered in the buffer, a setting register for holding various settings for obtaining an interpolation pixel of a pixel adjacent in the horizontal direction or the vertical direction of the original image, and each interpolation pixel from the setting register A vertical scaler for vertically expanding or reducing the pixel data buffered in the line buffer based on the vertical direction vertical direction interpolation information indicating an interpolation processing method for obtaining, from the setting register At least one of the plurality of lines of the line buffer based on a mode selection signal of The image processing apparatus characterized by stopping the clock.

  According to this, when performing vertical filtering (scaling) on an input image, for example, the number of line buffers to be used can be selected from one line or three lines, and the image quality after filtering is reduced. If you do not want that much or want to reduce power consumption as much as possible, you can use only one line buffer and stop the rest of the line buffer, so if you want to prioritize power consumption with a trade-off between image quality and power consumption An image processing apparatus capable of stopping the line buffer by an unnecessary amount is provided.

  Application Example 2 In the image processing apparatus, the line of the line buffer has three stages, and the clocks of the rear two stages of the three stages are stopped based on the mode selection signal. A featured image processing apparatus.

  According to this, when prioritizing power consumption with a trade-off between image quality and power consumption with a simple configuration, the line buffer can be stopped for two unnecessary subsequent stages.

  Application Example 3 An image processing method for obtaining pixel data of an enlarged image of an original image or a reduced image of the original image, the line buffer step for buffering pixel data of a plurality of lines of the original image, A setting step for holding various settings for obtaining interpolated pixels of pixels adjacent in the horizontal direction or the vertical direction of the original image based on the pixel data buffered in the line buffer step, and each interpolation in the setting step A vertical scaler step for expanding or reducing the buffered pixel data in the vertical direction based on the vertical direction vertical interpolation information indicating an interpolation processing method for obtaining a pixel, and in the setting step, Stopping at least one clock of the plurality of lines based on a mode selection signal of Image processing method for the butterflies.

  According to this, when performing vertical filtering (scaling) on an input image, for example, the number of line buffers to be used can be selected from one line or three lines, and the image quality after filtering is reduced. If you do not want that much or want to reduce power consumption as much as possible, you can use only one line buffer and stop the rest of the line buffer, so if you want to prioritize power consumption with a trade-off between image quality and power consumption An image processing method capable of stopping the line buffer by an unnecessary amount is provided.

  Application Example 4 An electronic apparatus comprising the image processing apparatus according to any one of the above.

  According to this, since the image processing apparatus is provided, there is provided an electronic apparatus capable of stopping the line buffer by an unnecessary amount when power consumption is prioritized by a trade-off between image quality and power consumption.

The figure which shows the structural example of the mobile telephone which concerns on this embodiment. The figure which shows the whole block concerning this embodiment. The block diagram which shows the 2nd image processing circuit and 2nd setting register which concern on this embodiment. The block diagram which shows the vertical direction expansion / contraction circuit which concerns on this embodiment. 1 is a block diagram of an electronic device according to an embodiment. 1 is an external view of an electronic apparatus according to an embodiment.

  Hereinafter, it explains in detail using a drawing concerning this embodiment. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

(Liquid crystal display device)
FIG. 1 is a diagram illustrating a configuration example of a mobile phone according to the present embodiment. As shown in FIG. 2, a baseband engine (BBE) 10 of a mobile phone according to the present embodiment includes an LSI (Large Scale) on which a central processing unit (CPU) that controls basic functions of the mobile phone 2 is mounted. Integration), a video and still image received via the Internet, a natural image taken with a camera, a menu screen necessary for operation of the mobile phone 2, and an output source of various image data such as characters and graphic information such as icons is there.

  In FIG. 1, a liquid crystal display panel (display panel in a broad sense) 12 is provided as a display of the mobile phone 2. The liquid crystal display panel 12 has a liquid crystal sealed between two glass substrates 14 and 16. The large glass substrate 14 is an active matrix substrate, for example, and each pixel is provided with a TFT (Thin Film Transistor) which is an active element. A transparent pixel electrode is connected to the drain terminal of the TFT of each pixel, a source line that is a data line is connected to the source terminal, and a gate line that is a scanning line is connected to the gate terminal. A transparent electrode is provided on the glass substrate 16 facing the glass substrate 14. A display driver (driving unit in a broad sense) 18 that drives the liquid crystal display panel 12 is COG-mounted on the glass substrate 16 along the short side of the glass substrate 14. The display driver 18 drives the liquid crystal display panel 12 by supplying scanning signals to the gate lines of the liquid crystal display panel 12 and data signals to the source lines.

  An image processing controller (an image processing device in a broad sense) 20 is provided between the baseband engine 10 and the display driver 18. A plurality of bus lines are connected between the baseband engine 10 and the image processing controller 20, and between the image processing controller 20 and the display driver 18, and image data, horizontal / vertical synchronization signals, clock signals, and various commands are transmitted. Transferred.

  In the present embodiment, the baseband engine 10 receives content data on the network and supplies image data included in the content data to the image processing controller 20. The image processing controller 20 enlarges or reduces the size of the image represented by the image data from the baseband engine 10 and supplies the image data after the enlargement process or the reduced process to the display driver 18.

A block diagram necessary for this embodiment is shown in the following figure.
(Overall block)
FIG. 2 is a diagram showing an entire block according to the present embodiment. An input interface (InterFace: hereinafter abbreviated as I / F) 22 is an interface with an apparatus for controlling the image processing apparatus such as a host CPU. The CPU can write the image data input from the input I / F 22 into the frame buffer 26 via the first memory I / F 24. Further, writing to the first to third setting registers 34 to 38 for determining the operation of the first to third image processing circuits 28 to 32 is also possible.

  In the first memory I / F 24, the image data input from the input I / F 22 is converted into an appropriate format and output to the frame buffer 26. At this time, conversion from RGB pixel data to YUV pixel data is also performed.

  In the second memory I / F 40, the image data read from the frame buffer 26 is output to any one of the first to third image processing circuits 28 to 32 according to the handshake protocol.

  In the display I / F 42, the data read from the display FIFO 44 is output to the LCD panel. At this time, conversion from pixel data in YUV format to pixel data in RGB format is also performed.

  The frame buffer 26 is a frame buffer.

  The display FIFO 44 is a FIFO (First In First Out).

  The first image processing circuit 28 is a circuit that performs conversion processing on the image data input from the second memory I / F 40 according to the setting value of the first setting register 34.

  The second image processing circuit 30 is a circuit that performs conversion processing on the image data input from the second memory I / F 40 or the first image processing circuit 28 according to the setting of the second setting register 36.

  The third image processing circuit 32 is a circuit that performs conversion processing on the image data input from the second memory I / F 40 or the first and second image processing circuits 28 and 30 according to the setting of the third setting register 38. .

  The first setting register 34 is a setting register that determines the operation of the first image processing circuit 28.

  The second setting register 36 is a setting register that determines the operation of the second image processing circuit 30.

  The third setting register 38 is a setting register that determines the operation of the third image processing circuit 32.

  In the present embodiment, the image processing circuit that performs image enlargement / reduction is the second image processing circuit 30. However, the essence of the present embodiment is effective regardless of the position of the second image processing circuit 30 and the presence or absence of circuits in the previous and subsequent stages, as can be understood from the description of the first to third image processing circuits 28 to 32.

(Second image processing circuit 30 and second setting register 36 block diagram)
FIG. 3 is a block diagram showing the second image processing circuit 30 and the second setting register 36 according to this embodiment. The second image processing circuit 30 according to the present embodiment includes a data control circuit 46, a vertical scaling circuit 48 as a vertical scaler, and a horizontal scaling circuit 50.

  In the present embodiment, the second image processing circuit 30 is referred to as a scaler because the input image is enlarged or reduced.

  The input image data and the input image data enable are input from the second memory I / F 40 or the first image processing circuit 28 as described above. An input image data request is also output to the second memory I / F 40 or the first image processing circuit 28.

  The output image data and the output image data enable are output to the third image processing circuit 32 or the display FIFO 44. An output image data request is also input from the third image processing circuit 32 or the display FIFO 44.

  The data control circuit 46 controls the input data and the output data, and outputs the enlarged coordinates to the vertical direction enlargement / reduction circuit 48 and the horizontal direction enlargement / reduction circuit 50. Here, the enlarged coordinates are values indicating which position in the output image the pixel of the input image corresponds to when the input image is enlarged or reduced.

  The vertical direction enlargement / reduction circuit 48 performs enlargement / reduction in the vertical direction according to input image data, enlargement coordinates, and various settings. Here, the input image data is input from the second memory I / F 40 or the first image processing circuit 28 as described above. The enlarged coordinates are input from the data control circuit 46. Various settings are input from the second setting register 36.

  The horizontal enlargement / reduction circuit 50 performs horizontal enlargement / reduction in accordance with input image data, enlargement coordinates, and various settings. Here, the input image data is input from the vertical enlargement / reduction circuit 48. The enlarged coordinates are input from the data control circuit 46. Various settings are input from the second setting register 36.

  The second setting register 36 holds various settings necessary for the second image processing circuit 30 to operate from the input I / F 22 (input I / F) in FIG. The set values are held in the registers M1, O1, CV0 to 7, and CH0 to 7. Here, the register M1 is a mode selection signal according to the present invention, and the register O1 is a set value such as an enlargement ratio. The registers CV <b> 0 to CV <b> 7 are coefficient tables for performing pixel complementation when expanding in the vertical direction. The registers CH0 to CH7 are coefficient tables for performing pixel interpolation when expanding in the horizontal direction.

  The register values held in these registers are registers SM1, SO1, SCV0 to 7, SCH0 according to a frame synchronization signal output from a circuit for controlling data output from the frame buffer 26 via the second memory I / F 40 in FIG. To 7. The mode selection signal received by the vertical enlargement / reduction circuit 48 and the horizontal enlargement / reduction circuit 50, the other set values, and the coefficient table are values of these registers.

  With this mechanism, since the set values received by the vertical direction enlargement / reduction circuit 48 and the horizontal direction enlargement / reduction circuit 50 are always synchronized with the frame, it is possible to prevent the display image from being disturbed by the change of the set value during one frame. .

(Vertical enlargement / reduction circuit 48 block diagram)
FIG. 4 is a block diagram showing the vertical enlargement / reduction circuit 48 according to the present embodiment.
The vertical enlargement / reduction circuit 48 according to the present embodiment includes first to third line buffers 52 to 56 as line buffers, zero to third shift registers 58 to 64, and zeroth to third coefficient table selection circuits 66 to 72. And multipliers 74 to 80 and an adder 82.

  As shown in FIG. 4, the first to third line buffers 52 to 56 are memories that can store one line of input image data.

  The 0th to 3rd shift registers 58 to 64 are each a register that can store data for one pixel.

  The 0th to 3rd coefficient table selection circuits 66 to 72 are circuits that select values from the coefficient table according to the enlarged coordinates.

  The multipliers 74 to 80 multiply the outputs of the flip-flops constituting the shift register and the coefficients H0 to H3.

  The adder 82 adds the outputs of the multipliers 74 to 80.

  The relationship between the enlarged coordinates and the coefficients is shown in Table 1 below.

  The operation of the vertical enlargement / reduction circuit 48 corresponding to the 4-line mode will be described with reference to FIG. First, in step S 10, the process waits until input image data input from the outside accumulates in the second line buffer 54.

  Next, when data reaches the second line buffer 54 in step S20, the input image data is the 0th shift register 58, the first line buffer 52 output is the first shift register 60, and the second line buffer 54 output is the second. The data is stored in the shift register 62 and the third shift register 64.

  Next, in step S30, a coefficient is selected from the corresponding coefficient table based on the coordinate signal and the mode selection signal.

  Next, in step S40, the sums of the coefficients H0 to 3 selected by the 0th to 3rd shift registers 58 to 64 and the 0th to 3rd coefficient table selection circuits 66 to 72 are respectively calculated and output as output image data. To do.

  Next, in step S50, the processing from steps S20 to S40 is repeated for one line.

  In step S60, the output of the first to third line buffers 52 to 56 is stored in the 0th shift register 58 and the first shift registers 60 to 64 from the second line onward.

  Next, in step S70, steps S60, S30, and S40 are repeated until the final line-2.

  Next, in step S80, the output of the first line buffer 52 is stored in the 0th shift register 58 and the first shift register 60 in the final line-1, and the second shift register 62 and the third shift register 64 are respectively in the second line. The outputs of the line buffer 54 and the third line buffer 56 are stored.

  Next, in step S90, steps S80, S30, and S40 are repeated one line.

  Next, in step S100, the output of the third line buffer 56 is stored in the 0th shift register 58 and the third shift register 64 in the final line, and the second line buffer 54 is stored in the first shift register 60 and the second shift register 62. Store the output of.

  Next, in step S110, steps S100, S30, and S40 are repeated one line. And it ends.

  The operation of the vertical enlargement / reduction circuit 48 corresponding to the two-line mode will be described with reference to FIG. First, in step S210, the clocks of the second and third line buffers 54 and 56 and the second and third shift registers 62 and 64 are stopped by a mode selection signal input from the outside.

  In step S220, the process waits until input image data input from the outside accumulates in the first line buffer 52.

  Next, when data reaches the first line buffer 52 in step S230, the input image data is stored in the 0th shift register 58, and the output of the first line buffer 52 is stored in the first shift register 60.

  Next, in step S240, a coefficient is selected from the corresponding coefficient table based on the coordinate signal and the mode selection signal.

  Next, in step S250, the 0th and 1st shift registers 58 and 60 and the selected coefficients H0 and H1 are summed, and output as output image data.

  Next, in step S260, steps S230 to S250 are repeated until the final line-1.

  Next, in step S270, the output of the first line buffer 52 is stored in the zeroth shift register 58 and the first shift register 60 in the last line.

  Next, in step S280, steps S270, S240, and S250 are repeated one line. And it ends.

(Electronics)
FIG. 5 shows an example of a block diagram of the electronic apparatus according to the present embodiment. The electronic device 100 according to this embodiment includes a microcomputer (or ASIC) 102, an input unit 104, a memory 106, a power generation unit 108, an LCD 110, and a sound output unit 112.

  Here, the input unit 104 is for inputting various data. The microcomputer 102 performs various processes based on the data input by the input unit 104. The memory 106 serves as a work area for the microcomputer 102 and the like. The power generation unit 108 is for generating various power sources used in the electronic device 100. The LCD 110 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 112 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 100, and the function can be realized by hardware such as a speaker.

  FIG. 6A illustrates an example of an external view of a mobile phone 120 which is one of electronic devices. The mobile phone 120 includes a dial button 122 that functions as an input unit, an LCD 124 that displays a telephone number, a name, an icon, and the like, and a speaker 126 that functions as a sound output unit and outputs sound.

  FIG. 6B illustrates an example of an external view of a portable game device 130 which is one of electronic devices. The portable game apparatus 130 includes an operation button 132 that functions as an input unit, a cross key 134, an LCD 136 that displays a game image, and a speaker 138 that functions as a sound output unit and outputs game sound.

  FIG. 6C illustrates an example of an external view of a personal computer 140 that is one of electronic devices. The personal computer 140 includes a keyboard 142 that functions as an input unit, an LCD 144 that displays characters, numbers, graphics, and the like, and a sound output unit 146.

  By incorporating the microcomputer according to the present embodiment into the electronic devices in FIGS. 6A to 6C, it is possible to provide an electronic device with low cost and high image processing speed and high cost performance.

  In addition to the devices shown in FIGS. 6A, 6 </ b> B, and 6 </ b> C, electronic devices that can use this embodiment include devices that include portable information terminals, pagers, electronic desk calculators, and touch panels. Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and a car navigation device can be considered.

  According to the present embodiment, in a field that pursues low power consumption such as a mobile phone that is a product using an image processing device and a field that pursues high image quality such as a television, Power consumption can be suppressed by setting the number of line buffers to one line.

  On the other hand, in a field where high image quality is desired, the number of line buffers can be set to 3 lines to suppress deterioration in image quality.

  In the embodiment, an example in which the line buffer is switched between 3 lines and 1 line has been shown. However, the essence is not limited to the number of lines. Is to stop.

  As described above, according to the present embodiment, enlargement / reduction processing can be performed while suppressing power consumption of the circuit. In addition, it is possible to deal with products in a wider field with one IC.

  DESCRIPTION OF SYMBOLS 2 ... Mobile phone 10 ... Baseband engine (BBE) 12 ... Liquid crystal display panel (display panel) 14, 16 ... Glass substrate 18 ... Display driver (drive part) 20 ... Image processing controller (image processing apparatus) 22 ... Input interface 24 First memory I / F 26 Frame buffer 28 to 32 First to third image processing circuits 34 to 38 First to third setting register 40 Second memory I / F 42 LCD I / F 44 Display FIFO 46 ... Data control circuit 48 ... Vertical enlargement / reduction circuit (vertical scaler) 50 ... Horizontal enlargement / reduction circuit 52 to 56 ... 1st to 3rd line buffer (line buffer) 58 to 64 ... 0th to 3rd shift registers 66 to 72 ... 0th to 3rd coefficient table selection circuit 74-80 ... Multiplier 82 ... adder 100 ... electronic device 102 ... microcomputer 104 ... input unit 106 ... memory 108 ... power generation unit 110 ... LCD 112 ... sound output unit 120 ... cell phone 122 ... dial button 124 ... LCD 126 ... speaker 130 ... portable Game device 132 ... Operation button 134 ... Cross key 136 ... LCD 138 ... Speaker 140 ... Personal computer 142 ... Keyboard 144 ... LCD 146 ... Sound output section.

Claims (4)

An image processing apparatus for obtaining pixel data of an enlarged image of an original image or a reduced image of the original image,
A line buffer for buffering pixel data of a plurality of lines of the original image;
Based on pixel data buffered in the line buffer, a setting register that holds various settings for obtaining interpolated pixels of pixels adjacent in the horizontal direction or vertical direction of the original image;
A vertical scaler for expanding or reducing the pixel data buffered in the line buffer in the vertical direction based on the vertical direction interpolation information indicating the interpolation processing method for obtaining each interpolation pixel from the setting register When,
Including
An image processing apparatus that stops at least one clock of the plurality of lines of the line buffer based on a mode selection signal from the setting register. The image processing apparatus according to claim 1.
The line of the line buffer has three stages,
An image processing apparatus that stops clocks in the rear two of the three stages based on the mode selection signal. An image processing method for obtaining pixel data of an enlarged image of an original image or a reduced image of the original image,
A line buffer step for buffering pixel data of a plurality of lines of the original image;
Based on the pixel data buffered in the line buffer step, a setting step for holding various settings for obtaining interpolation pixels of pixels adjacent in the horizontal direction or the vertical direction of the original image;
A vertical scaler step for expanding or reducing the buffered pixel data in the vertical direction based on the vertical direction interpolation information indicating the interpolation processing method for obtaining each interpolation pixel in the setting step;
Including
An image processing method comprising: stopping at least one clock of the plurality of lines based on a mode selection signal in the setting step.   An electronic apparatus comprising the image processing apparatus according to claim 1.