JP2006246573A - Inverter transformer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter transformer capable of assuring effect for suppressing failure in oscillation start for example, even if an operation threshold voltage of a switching device varies by a temperature change in a use environment, and capable of eliminating need for largely high cost required to obtain the effect. <P>SOLUTION: This inverter transformer 4 includes an inverter 7 for converting a DC voltage after a full-wave rectification into a high frequency AC voltage, and a transformer 8 for charging the high frequency AC voltage to a high voltage. The inverter 7 includes a pair of FETs 9, 10, and a bias circuit 11 for switching the FETs 9, 10 between ON and OFF states. The FETs 9, 10 are alternately turned on by a gate bias voltage of the bias circuit 11, thus repeating the operation to generate the high frequency AC voltage Vb with the high voltage in a secondary winding 8b of the transformer 8. A resistance 25 acting to add an auxiliary bias to the gate bias voltage of the first FET 9 is connected between the gate of the first FET 9 and a choke coil 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inverter transformer that converts an input voltage into a high-frequency voltage having a predetermined pressure and outputs the voltage.

  Conventionally, an inverter transformer that rectifies an AC voltage input from a commercial power supply and converts it to a high-frequency voltage (high-frequency AC voltage), boosts the high-frequency voltage to a predetermined voltage by a transformer, and outputs the voltage to the secondary side is widely used. ing. This type of inverter transformer is used as a power source for a discharge lamp such as a fluorescent lamp, and an example thereof is disclosed in Patent Document 1, for example. The inverter transformer of Patent Document 1 is a push-pull type circuit using two field effect transistors (FETs) 51 and 52 as shown in FIG. 5, for example, and is smoothed by turning on these FETs 51 and 52 alternately. Is converted to a high frequency voltage.

  The FETs 51 and 52 have a characteristic that the gate threshold voltage varies within a predetermined volt range for each element, and the voltage value varies within a range of about 1 V, for example, depending on the product as shown in FIG. Further, the FETs 51 and 52 have a temperature characteristic, and as shown in FIG. 6, there is a characteristic that the gate threshold voltage increases as the temperature decreases. Therefore, it is necessary to apply to the FETs 51 and 52 a gate bias voltage having such a value that the FETs 51 and 52 can be driven even when the gate threshold voltage increases due to low temperature. The gate bias voltage is set by adjusting the resistance values of the resistors R1 to R4 shown in FIG. 5 connected in a bridge shape.

  However, since the FETs 51 and 52 take values within the range of the gate threshold voltages Vsa and Vsb as shown in FIG. 7 depending on their own temperature state, the FETs 51 and 52 are lowered when the FETs 51 and 52 are heated to a low temperature. It is easy to take a state in which the gate bias voltage applied to is higher than the gate threshold voltage, and the on-time of the FETs 51 and 52 becomes longer. For this reason, there is an overlapping interval in which both FETs 51 and 52 are simultaneously turned on, and when both FETs 51 and 52 are turned on, a surge current flows to each drain, so that the FETs 51 and 52 are likely to generate heat and have a high possibility of breakage. On the other hand, when the gate bias voltage is too low, the FETs 51 and 52 cause an oscillation start failure and do not start oscillation. Therefore, the gate bias voltage needs to be set to a high voltage value so that the two FETs 51 and 52 are not turned on at the same time and an oscillation start failure does not occur.

  Therefore, the gate bias voltage is set to the following value by adjusting the resistance values of the resistors R1 to R4. First, the middle point of the resistors R1 and R3 and the middle point of the resistors R2 and R4 shown in FIG. 8 are short-circuited by a feedback winding (gate winding), and the combined voltage at the short-circuited portion is Vg. The combined voltage Vg at this short-circuited portion is set to be equal to or higher than the highest gate threshold voltage that can occur within the range under the operating temperature. For example, assuming that the minimum operating temperature of the FETs 51 and 52 is −30 degrees, the highest gate threshold voltage that can be generated at this temperature is about 3.8 V as shown in FIG. .8V or higher is set.

Further, as shown in FIG. 9, when the voltage between the terminals of the resistor R3 is V1, and the voltage between the terminals of the resistor R4 is V2, one of the voltages V1 and V2 between the terminals is most likely to occur within the range of the operating environment temperature. It is set to be lower than the low gate threshold voltage. For example, if the maximum operating temperature of the FETs 51 and 52 is +80 degrees, the lowest gate threshold voltage that can be generated at this temperature is about 2 V as shown in FIG. The value is set to 2V or less. If the combined voltage Vg and the inter-terminal voltages V1 and V2 are set as described above, the FETs 51 and 52 are not turned on at the same time, and no oscillation start failure occurs.
JP-A-4-23518 (page 2-3, FIG. 1)

  However, depending on the type of the FETs 51 and 52, the gate threshold voltage may be 4.5 V or higher at low temperatures. When such FETs 51 and 52 are used, the Zener diode 53 shown in FIGS. In view of the threshold voltage value, an element of 6V or higher is used instead of a Zener voltage element of around 6V having a small temperature gradient. Here, the Zener diode 53 has a characteristic that an element having a Zener voltage lower than 6V has a negative temperature gradient, while an element having a voltage higher than 6V has a positive temperature gradient. Accordingly, when the Zener diode 53 has a Zener voltage of 6V or more, the gate threshold voltage of the FETs 51 and 52 increases when the operating environment temperature decreases, but the Zener voltage of the Zener diode 53 decreases. There was a problem that could not be done.

  In addition, since one of the inter-terminal voltages V1 and V2 is set to be equal to or lower than the lowest gate threshold voltage that can occur within the operating temperature range, even if the inverter transformer is turned on, the FET 51, There is a problem that a voltage sufficient to oscillate 52 (turns on alternately) cannot be supplied to the FETs 51 and 52, and the start of oscillation is delayed at startup. When the oscillation of the FETs 51 and 52 is delayed as described above, for example, one of the two FETs 51 and 52 may be on and the other may remain off, and a surge current may flow to the drain on the on side. There was a request to improve the responsiveness.

  In addition to the method of setting the values of the resistors R1 to R4 and the Zener diode 53 as described above, the gate bias voltage is set using a temperature sensitive resistor, for example, for any of the resistors R1 to R4. It is also conceivable to use a method of adding. For example, a temperature sensitive resistor having a positive temperature coefficient is used for the resistors R1 and R2, and the voltage between terminals V1 and V2 and, consequently, the combined voltage Vg are increased at a low temperature, thereby suppressing oscillation start failure. By reducing the combined voltage Vg, the FETs 51 and 52 are prevented from being simultaneously turned on to prevent a surge current from flowing. However, since this method requires the use of an expensive temperature sensitive resistor, there is a problem in that the cost of the apparatus is increased.

  The object of the present invention is to ensure the effect of suppressing the start of oscillation failure even when the operating threshold voltage of the switching element fluctuates due to, for example, a change in temperature of the use environment, and incurs a significant increase in cost when this effect can be achieved. There is no inverter transformer to provide.

  In order to solve the above-described problem, in the invention according to claim 1, the switching elements are alternately turned on by alternately setting the bias voltages applied to the pair of switching elements to be equal to or higher than the operation threshold voltage. An inverter transformer comprising an inverter that converts an input voltage into a high frequency voltage and a transformer that boosts the high frequency voltage to a high voltage. The gist is that an impedance element for applying a bias is connected.

  According to the present invention, since the auxiliary bias is applied to the bias voltage applied to the switching element by the impedance element, the bias voltage is set to a high voltage value. Therefore, if the switching element has temperature characteristics, for example, even if the operating threshold voltage of the switching element increases due to low temperatures, if the bias voltage is set to a value that takes into account the increased value, the operating environment is low Even if it becomes, it becomes possible to turn on a switching element reliably. Therefore, the oscillation start failure (non-oscillation) of the switching element is difficult to occur. In addition, since the present invention uses an impedance element that is relatively inexpensive and available, the cost can be kept lower than when using a component for the effect of a temperature sensitive resistor, for example. is there.

  According to a second aspect of the present invention, in the first aspect of the invention, the impedance element is provided between the output side of the current limiting element connected in the circuit of the inverter and the control terminal of the switching element. The gist is that they are connected in series.

  According to the present invention, in addition to the operation of the first aspect of the invention, the inter-terminal voltage between the output side of the current limiting element and the control terminal of the switching element is lower than, for example, the input terminal side of the switching element. Value. Therefore, since the impedance element is connected between the terminals having a relatively low voltage, it is not necessary to apply a high voltage to the impedance element, which contributes to improvement in durability of the impedance element.

The invention according to claim 3 is summarized in that, in the invention according to claim 1 or 2, the impedance element is connected to each pair of the switching elements.
According to the present invention, in addition to the operation of the invention described in claim 1 or 2, since the bias voltage with the auxiliary bias added is supplied to both of the switching elements provided in the pair, it is applied to each switching element. Both bias voltages are high in voltage value. Therefore, when the inverter transformer is started, the pair of switching elements are alternately turned on quickly, and the switching element is not easily switched on. hard.

  According to the present invention, for example, even if the operating threshold voltage of the switching element fluctuates due to temperature changes in the usage environment, it is possible to ensure an oscillation start failure suppression effect, and without incurring a significant cost increase when this effect can be achieved. That's it.

Hereinafter, an embodiment of an inverter transformer embodying the present invention will be described with reference to FIGS.
FIG. 3 is a block diagram showing a schematic configuration of the discharge lamp control device 1. The discharge lamp control device 1 has an input side connected to the commercial power source 2 and an output side connected to the discharge lamp 3, and turns on the discharge lamp 3 based on an input AC voltage (for example, about 100 V) Va input from the commercial power source 2. It is a device that controls light) and blinking. In the discharge lamp control device 1, a plurality of discharge lamps 3 are connected in parallel, and a plurality of (three in this example) discharge lamps 3, 3,. As the discharge lamp 3, for example, a neon tube or an argon tube is used, and when there are three discharge lamps as in this example, those having emission colors of R, G, and B are used.

  FIG. 1 is a circuit diagram showing an electrical configuration of an inverter transformer (neon transformer) 4. The discharge lamp control device 1 includes an inverter transformer 4 that rectifies and converts high frequency the input AC voltage Va input from the commercial power source 2, boosts the high frequency voltage, and supplies the high frequency AC voltage to the discharge lamp 3. The inverter transformer 4 is provided in the number of the discharge lamps 3 (three in this example) so as to form a pair with each discharge lamp 3, and is accommodated in the case of the discharge lamp control device 1. Although three inverter transformers 4 are provided in this example, only one inverter transformer 4 is shown in FIG.

  The inverter transformer 4 includes a filter circuit 5 that performs noise removal processing (filter processing), overvoltage protection processing, and the like on the input AC voltage Va input from the commercial power source 2, and a full-wave rectifier for the input AC voltage Va from the commercial power source 2. And a wave rectifier circuit 6. The full-wave rectification circuit 6 is configured by bridge-connecting diodes, and full-wave rectifies the input AC voltage Va from which noise has been canceled by the filter circuit 5. The filter circuit 5 and the full-wave rectifier circuit 6 do not have to be prepared for each inverter transformer 4 and may be shared by the three inverter transformers 4 in this example.

  The inverter transformer 4 includes an inverter 7 that converts a DC voltage after full-wave rectification into a high-frequency voltage, and a transformer 8 that boosts the high-frequency voltage to a high voltage. The inverter 7 is connected between the full-wave rectifier circuit 6 and the transformer 8, and the circuit configuration will be described below. The inverter 7 includes a pair of first FET 9 and second FET 10 and a bias circuit 11 that switches on and off of the first FET 9 and second FET 10. The first FET 9 and the second FET 10 correspond to switching elements.

  The bias circuit 11 is a circuit in which four resistors R1 to R4 are connected in a bridge shape, and more specifically, a first voltage dividing resistor 12 in which resistors R1 and R3 are connected in series, and resistors R2 and R4 are connected in series. This is a circuit in which the second voltage dividing resistor 13 is connected in parallel. The resistance values of the resistors R1 to R4 are set so that one of the series circuit of the resistors R1 and R3 and the series circuit of the resistors R2 and R4 has a higher voltage dividing ratio than the other.

  As the first FET 9 and the second FET 10 in this example, for example, a MOSFET (Metal-Oxide-Semiconductor FET) is used. The first FET 9 has a drain connected to one end of the first winding 8 a of the transformer 8, a source short-circuited, and a gate (control terminal) connected to the midpoint of the first voltage dividing resistor 12. The second FET 10 has a drain connected to the other end of the first winding 8 a of the transformer 8, a source short-circuited, and a gate connected to the midpoint of the second voltage dividing resistor 13. The first FET 9 and the second FET 10 are turned on when the gate bias voltage Vx applied to the gate becomes equal to or higher than the gate threshold voltage Vs, and turned off when the gate bias voltage Vx falls below the gate threshold voltage Vs. The first FET 9 and the second FET 10 operate so that the gate bias voltage Vx is alternately applied so that the gate bias voltage Vx is alternately equal to or higher than the gate threshold voltage Vs, and the first FET 9 and the second FET 10 are alternately turned on. In this example, the gate threshold voltages Vs of the first FET 9 and the second FET 10 are the same value. The gate bias voltage Vx corresponds to the bias voltage, and the gate threshold voltage Vs corresponds to the operation threshold voltage.

  A resonance capacitor 14 is connected in parallel between both drains of the first FET 9 and the second FET 10, that is, at both ends of the first winding 8 a of the transformer 8. The resonance capacitor 14 forms a parallel resonance circuit (LC resonance circuit) with the inductance component of the transformer 8.

  Between the terminals of the full-wave rectifier circuit 6, a ripple capacitor 15 that absorbs the ripple of the DC voltage after full-wave rectification is connected. In addition, a choke coil (inductor) 16 is connected to the output terminal of the full-wave rectifier circuit 6 as an element that prevents a sudden flow of current into the inverter 7. A diode 17, a resistor 18, and an electrolytic capacitor 19 are connected in series between the output terminal of the choke coil 16 and GND. Among them, the electrolytic capacitor 19 is an element that supplies a stable voltage to the gates of the first FET 9 and the second FET 10. The choke coil 16 corresponds to a current limiting element.

  A Zener diode 20 is connected to both ends of the first voltage dividing resistor 12 (second voltage dividing resistor 13) to hold the voltage value divided on the upstream side at a constant value. The Zener diode 20 has an anode connected to the GND side and a cathode connected to the power supply side. A diode 21 is connected between the first voltage dividing resistor 12 (second voltage dividing resistor 13) and the choke coil 16, and the first voltage dividing resistor 12 (second voltage dividing resistor 13) is connected to the choke coil 16. A resistor 22 is connected between the resistor 18 and the middle point of the electrolytic capacitor 19.

  In the transformer 8, the first winding 8 a is connected between the drain terminals of the first FET 9 and the second FET 10, and the intermediate tap of the first winding 8 a is connected to the choke coil 16. The discharge lamp 3 (see FIG. 3) is connected to the secondary winding 8b of the transformer 8. The transformer 8 boosts the primary voltage, that is, the high-frequency voltage generated by the inverter 7 to generate a high-frequency AC voltage Vb and applies it to the discharge lamp 3. A capacitor 23 and a diode 24 in parallel are connected in series to one end of the second winding in order to prevent the discharge lamp 3 from being in a striped light emission state.

  The transformer 8 includes a feedback winding 8c through which a current flows due to mutual induction between the first winding 8a. The feedback winding 8c has one end connected to the gate of the first FET 9 (ie, the middle point of the first voltage dividing resistor 12) and the other end connected to the gate of the second FET 10 (ie, the middle point of the second voltage dividing resistor 13). ). The first winding 8a, the resonance capacitor 14, the first FET 9, the second FET 10, and the feedback winding 8c constitute a self-excited resonance circuit.

  A resistor 25 is connected between the gate of the first FET 9 and the choke coil 16 so as to apply an auxiliary bias to the gate bias voltage Vx of the first FET 9. Therefore, the voltage value obtained by adding the voltage Vr between the terminals of the resistor 25 to the conventional gate bias voltage obtained from the voltage dividing ratios of the first voltage dividing resistor 12 and the second voltage dividing resistor 13 is a new gate bias voltage Vx. Is applied to the gate of the first FET 9. Even if the gate threshold voltage Vs of the first FET 9 rises due to temperature characteristics, the resistance value of the resistor 25 is set to a value that can reliably turn on the first FET 9 as long as it is within the operating environment range. The resistor 25 corresponds to an impedance element.

Next, the operation of the inverter transformer 4 of this example will be described.
When the power switch of the discharge lamp control device 1 is turned on and the input AC voltage Va of the commercial power supply 2 is supplied to each inverter transformer 4, a voltage as shown in FIG. 2 is applied to each gate of the first FET 9 and the second FET 10. Waveform gate bias voltages Vx1 and Vx2 are respectively applied. Since each of the first FET 9 and the second FET 10 has a characteristic unique to each element, one of the first FET 9 and the second FET 10 is turned on first due to a slight difference in characteristics when the power is turned on.

  Here, for example, if the second FET 10 is turned on first, a current flows through the flow path of the choke coil 16, the first winding 8a, and the second FET 10. At this time, since mutual induction occurs in the feedback winding 8c, a current corresponding to the direction of the current flowing in the first winding 8a flows in the feedback winding 8c. Therefore, the voltage generated in the feedback winding 8c is superimposed on the second gate bias voltage Vx2 applied to the second FET 10, the second FET 10 is kept on, and the first FET 9 is kept off.

  Thereafter, when the resonance current (resonance voltage) by the resonance circuit of the transformer 8 and the resonance capacitor 14 is inverted, the second gate bias voltage Vx2 falls below the gate threshold voltage Vs, the second FET 10 is turned off, and the first FET 9 is applied. The 1 gate bias voltage Vx1 becomes equal to or higher than the gate threshold voltage Vs, and the first FET 9 is turned on. Accordingly, a current flows through the flow path of the choke coil 16, the first winding 8a, and the first FET 9. Also at this time, since a mutual induction action occurs in the feedback winding 8c, a current corresponding to the direction of the current flowing in the first winding 8a flows in the feedback winding 8c. Therefore, the voltage generated in the feedback winding 8c is superimposed on the first gate bias voltage Vx1, and the first FET 9 is kept on and the second FET 10 is kept off.

  The first FET 9 and the second FET 10 are alternately turned on by alternately repeating the above operation, and a high-frequency high-frequency AC voltage Vb is generated in the secondary winding 8b of the transformer 8 by repeating this operation. The transformer 8 supplies the high-frequency AC voltage Vb generated on the secondary side to the discharge lamp 3 via the capacitor 23. The discharge lamp 3 is lit or blinked when the high-frequency AC voltage Vb is equal to or higher than the starting voltage value.

  In this example, since the resistor 25 is connected to the first FET 9 side, the voltage waveform S1 of the first gate bias voltage Vx1 and the voltage waveform S2 of the second gate bias voltage Vx2 are the resistances R1 to R4 and A waveform shifted upward by a voltage based on the voltage dividing ratio of the resistor 25 is taken. That is, the voltage waveforms S1 and S2 have waveforms shifted upward by the gate threshold voltage Vs. The resistance value of the resistor 25 is set so as to satisfy such a waveform.

  Further, a voltage obtained by adding the voltage Vr between the terminals of the resistor 25 to the voltage applied by the resistors R1 to R4 is applied to the first FET 9 as the first gate bias voltage Vx1. This will be described below. First, the voltage between the terminals of the resistor 25 (that is, the voltage after the choke coil 16) Vr takes a half-string voltage waveform S3 as shown in FIG. The first gate bias voltage Vx1 is a voltage waveform S3 in the form of a half-string wave, which is a current sine wave voltage waveform determined by the relationship of the voltage dividing ratio between the first voltage dividing resistor 12 and the second voltage dividing resistor 13. The voltage waveform S1 shown in FIG. In the voltage waveform S1 of this example, the peak value Vp1 of the sine wave (> the peak value Vp2 of the voltage waveform S2) is higher by the voltage Vr between the terminals of the resistor 25.

  The first gate bias voltage Vx1 before the addition of the resistor 25 has a peak value due to the voltage division ratio relationship between the first voltage dividing resistor 12 and the second voltage dividing resistor 13 as compared with the second gate bias voltage Vx2. Took a small waveform. Therefore, in this example, by adding the resistor 25 on the first FET 9 side, the voltage value (peak value Vp1) of the first gate bias voltage Vx1 is set higher than before, and the oscillation start of the first FET 9 is ensured. ing.

  In this example, the terminal-to-terminal voltage Vr of the resistor 25 is generated, for example, at a peak of 141 V at the start-up, and this voltage is superimposed on the gate bias voltage by the first voltage dividing resistor 12 and the second voltage dividing resistor 13, The total voltage is applied to the first FET 9 as a new first gate bias voltage Vx1. Therefore, since the first gate bias voltage Vx1 having a sufficiently high value is applied to the first FET 9, even if the first FET 9 has a low temperature and the gate threshold voltage Vs becomes high, the Zener diode 20 has a high Zener voltage. The first gate bias voltage x1 sufficient to be able to oscillate can be supplied to the first FET 9 without taking measures to change to the above. Therefore, even if the first FET 9 is at a low temperature, it is difficult for the first FET 9 to oscillate.

  In this example, since the first gate bias voltage Vx1 having a high value is applied to the first FET 9, the oscillation of the first FET 9 (that is, the alternate ON operation of the FET) is promptly started at the time of start-up. The time Ta from turning on to the start of oscillation is shortened. Here, for example, when the second FET 10 is turned on at the time of startup and the first FET 9 does not start for a while and remains off for a while, a surge current flows to the drain of the second FET 10. If the oscillation is performed quickly, the first FET 9 and the second FET 10 are unlikely to be in the switch state as described above, and the surge current is difficult to flow.

  Furthermore, in this example, in order to increase the first gate bias voltage Vx1, a method of adding an element in the circuit of the inverter 7 is used. This additional element is a resistor 25. Therefore, even if the number of elements is increased, the voltage waveforms S1 and S2 of the first gate bias voltage Vx1 and the second gate bias voltage Vx2 do not become out of phase. Therefore, it is not necessary to have a section in which the first FET 9 and the second FET 10 are simultaneously turned on, and it is also possible to prevent the flow of surge current that occurs when both are simultaneously turned on.

According to the configuration of the present embodiment, the following effects can be obtained.
(1) A resistor 25 is connected between the gate of the first FET 9 and the choke coil 16, and the terminal voltage Vr of the resistor 25 is added to the first gate bias voltage Vx1. Accordingly, since the first gate bias voltage Vx1 is supplied to the first FET 9 at a high level, even if the first FET 9 is at a low temperature and the gate threshold voltage Vs is significantly increased, for example, the Zener diode 20 is connected to an element having a high Zener voltage (Zener voltage). The gate bias voltage having a value sufficient for oscillation can be supplied to the first FET 9 without using a method of changing to an element having a voltage of 6 V or more. For this reason, it is possible to make it difficult to cause an oscillation failure at a low temperature without changing parts.

  (2) Since the first gate bias voltage Vx1 having a high value is applied to the first FET 9, the oscillation of the first FET 9 is quickly started at the time of startup. Accordingly, if the oscillation start is delayed, a surge current may flow to the drain of the first FET 9. However, if the oscillation starts quickly as in this example, the phenomenon that the surge current flows to the drain is less likely to occur. it can.

  (3) Although an element is inserted into the inverter 7 in order to increase the first gate bias voltage Vx1, since this additional element is a resistor 25, the first gate bias voltage Vx1 and the second gate are increased even if the element is increased. The phase of the voltage waveforms S1 and S2 of the bias voltage Vx2 does not change. Accordingly, the gate bias voltages Vx1 and Vx2 are not less than the gate threshold voltage Vs at the same time, and the first FET 9 and the second FET 10 are not simultaneously turned on, and a phenomenon in which a surge current flows to the drain does not occur.

  (4) If the configuration of this example is used, the first gate bias voltage Vx1 having a sufficiently high voltage value is supplied to the first FET 9, so that the gate threshold voltage Vs of the first FET 9 is in the range of 3 to 5 V, for example, due to temperature change. This can be dealt with even when a variable FET is used. Accordingly, the number of FET options that can be used for the first FET 9 is increased, and general products and the like can also be used.

  (5) In this example, since the newly added component (element) is only one resistor 25, the required cost is low, and the circuit configuration (component arrangement pattern) in the inverter 7 is greatly increased. There is no need to change the design.

  (6) The voltage between the gate of the first FET 9 and the output side of the choke coil 16 is very small compared with the voltage on the drain side of the first FET 9, and in this example, for example, the former voltage is about 140V. On the other hand, the latter voltage is as high as 450V. Therefore, since the resistor 25 is connected between the gate of the first FET 9 and the output side of the choke coil 16, that is, at a low voltage portion, a high voltage is not applied to the resistor 25, and the durability of the resistor 25 is ensured. can do.

(7) Since the inter-terminal voltage Vr of the resistor 25 is added as the gate bias voltage, elements having low resistance values can be used as the resistors R1 to R4.
In addition, this embodiment is not limited to the said structure, You may change into the following aspects.

  The resistance added in the inverter 7 is not limited to one (resistor 25), and the resistor may be connected not only to the first FET 9 side but also to the second FET 10 side. For example, as shown in FIG. 4, a resistor 25 is connected to the first FET 9 side, and a resistor 30 is connected between the rear side of the choke coil 16 and the gate of the second FET 10. In this case, since both the first gate bias voltage Vx1 and the second gate bias voltage Vx2 are in a high voltage state, the switching operation in which the first FET 9 and the second FET 10 are alternately turned on is performed more quickly. Effective in suppressing surge current generation.

The resistor 25 is not limited to being connected to the first FET 9 side, and conversely, may be connected to the second FET 10 side.
The impedance element is not limited to the resistor 25 and is not particularly limited as long as it can add a voltage to the gate bias voltage of the first FET 9 (second FET 10) and does not change the phase of the gate bias voltage.

The inverter transformer 4 is not necessarily provided with the full-wave rectifier circuit 6, and the full-wave rectifier circuit 6 may be omitted when a DC power source such as a battery (battery) is used as a power source.
The inverter transformer 4 is not limited to the neon transformer as described in the embodiment, but may be applied for illumination.

Next, the technical idea that can be grasped from the above embodiment and other examples will be described below.
(1) In any one of claims 1 to 3, the inverter includes a pair of the switching elements, a current limiting element connected to a power source, a resonance capacitor that forms a parallel resonance circuit with the transformer, A bias circuit configured to output a bias voltage with a value corresponding to a voltage dividing ratio of the resistor.

  (2) In claims 1 to 3 and the technical idea (1), the transformer includes a primary winding connected to the inverter and a secondary winding that is a side that outputs a boosted high voltage. And a feedback winding for applying a voltage to the pair of switching elements in a manner superimposed on the bias voltage of the bias circuit.

  (3) In any one of Claims 1-3, the said impedance element is a resistance element. In this case, even if a new element is added to the inverter to prevent the oscillation start failure of the switching element, the phase of the bias voltage applied to each switching element does not change because the added element is a resistance element. Therefore, even if the number of elements is increased, it is not necessary for the switching elements to be turned on at the same time because the on-timing of each switching element is shifted, and a problem that a surge current flows into the switching element hardly occurs.

The circuit diagram which shows the electric constitution of the inverter transformer in one Embodiment. The wave form diagram of a gate bias voltage, the voltage between resistance terminals, and drain current. The block diagram which shows schematic structure of a discharge lamp control apparatus. The circuit diagram which shows a part of electrical structure of the inverter transformer in another example. The circuit diagram which shows a part of electrical structure of the conventional inverter transformer. The graph which shows the temperature characteristic of FET. The wave form diagram of the gate bias voltage applied to a pair of FET. The circuit diagram which shows a part of electrical structure of an inverter transformer. The circuit diagram which shows a part of electrical structure of an inverter transformer.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 4 ... Inverter transformer, 7 ... Inverter, 8 ... Transformer, 9 ... 1st FET which comprises a switching element, 10 ... 2nd FET which comprises a switching element, 16 ... Choke coil as a current limiting element, 25 ... Resistance as an impedance element , Vx (Vx1, Vx2): gate bias voltage as bias voltage, Vs: gate threshold voltage as operating threshold voltage, Va: input voltage.

Claims (3)

By alternately setting the bias voltage applied to each of the pair of switching elements to be equal to or higher than the operation threshold voltage, the inverter is alternately turned on to convert the input voltage into a high frequency voltage, and the high frequency voltage is set to a high voltage. In an inverter transformer with a transformer for boosting,
An inverter transformer, wherein an impedance element that applies an auxiliary bias to at least one of the bias voltages of the pair of switching elements is connected in the circuit of the inverter.   2. The inverter according to claim 1, wherein the impedance element is connected in series between an output side of a current limiting element connected in the circuit of the inverter and a control terminal of the switching element. Trance.   The inverter transformer according to claim 1, wherein the impedance element is connected to each pair of the switching elements.

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