JP2006245599A - Electronic component and semiconductor device - Google Patents

Electronic component and semiconductor device Download PDF

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JP2006245599A
JP2006245599A JP2006109951A JP2006109951A JP2006245599A JP 2006245599 A JP2006245599 A JP 2006245599A JP 2006109951 A JP2006109951 A JP 2006109951A JP 2006109951 A JP2006109951 A JP 2006109951A JP 2006245599 A JP2006245599 A JP 2006245599A
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electronic component
conductor portion
substrate
main surface
semiconductor device
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JP4043493B2 (en
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Takashi Noguchi
高 野口
Masahiro Machida
政広 町田
Makoto Terui
誠 照井
Yuichi Ideushi
雄一 出牛
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component such as a chip from which heat can be dissipated efficiently to the outside, and to provide a semiconductor device where an electronic component is mounted on a substrate for mounting an electronic component. <P>SOLUTION: The electronic component comprises a bump-like conductor portion 39 being connected electrically with a conductor portion formed on the major surface 60a of a substrate 60, and an auxiliary conductor portion 45 extending from the surface of the electronic component where the bump-like conductor portion is not formed toward the major surface of the substrate and having a length in the extending direction long enough to touch the major surface of the substrate when the electronic component is mounted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、電子部品、及び電子部品搭載用基板に電子部品が搭載された半導体装置に関する。   The present invention relates to an electronic component and a semiconductor device in which the electronic component is mounted on an electronic component mounting substrate.

これまで、電気機器分野では、電子部品からの発生する熱を効率良く外部に放熱させる技術開発が進められている。   Up to now, in the electrical equipment field, technological development for efficiently radiating heat generated from electronic components to the outside has been advanced.

そこで、放熱のための技術として、熱伝導率が高い放熱部品や樹脂を、チップ上に設ける技術がある（例えば、特許文献１参照）。   Therefore, as a technique for heat dissipation, there is a technique in which a heat dissipation component or a resin having high thermal conductivity is provided on a chip (see, for example, Patent Document 1).

また、熱放射率を向上させる皮膜を、チップ上もしくは基板上に設ける技術がある（例えば、特許文献２参照）。
特開平１０−１２５８３４号公報 特開平１１−６７９９８号公報 In addition, there is a technique for providing a film for improving the thermal emissivity on a chip or a substrate (for example, see Patent Document 2).
Japanese Patent Laid-Open No. 10-125834 JP-A-11-67998

しかしながら、上記文献１では、放熱のための材料として熱伝導率が高い材料を採用していることが開示されているに過ぎない。   However, the above document 1 merely discloses that a material having high thermal conductivity is adopted as a material for heat dissipation.

よって、このような構成では、チップから伝わった熱を効率良く大気へ放熱するには不十分である。特に、チップから基板に伝わった熱に関しては、当該熱が基板内部にこもり効率良く大気へ放熱されないことが懸念される。   Therefore, such a configuration is insufficient to efficiently dissipate the heat transmitted from the chip to the atmosphere. In particular, regarding the heat transferred from the chip to the substrate, there is a concern that the heat is trapped inside the substrate and is not efficiently dissipated to the atmosphere.

また、上記文献２には、熱放射率が高い皮膜を基板上に設けることが開示されているものの、チップから皮膜に至る伝熱経路に関する具体的な検討がなされていないため、熱をより効率的に大気へ放射させるという点を考慮すると、まだ改善の余地がある。特に、チップで生じた熱が皮膜へ到達するまでの間の伝熱経路において、熱がこもることが懸念される。   Moreover, although the document 2 discloses that a film having a high thermal emissivity is provided on the substrate, no specific study on the heat transfer path from the chip to the film has been made, so heat can be more efficiently used. There is still room for improvement in view of the point of radiating to the atmosphere. In particular, there is a concern that heat may accumulate in the heat transfer path until the heat generated in the chip reaches the film.

そこで、この発明の主目的は、チップ等の電子部品からの熱を効率良く外部に放熱可能な、電子部品、及び電子部品搭載用基板に電子部品が搭載された半導体装置を提供することにある。   Accordingly, a main object of the present invention is to provide an electronic component capable of efficiently dissipating heat from an electronic component such as a chip to the outside, and a semiconductor device in which the electronic component is mounted on an electronic component mounting substrate. .

この発明は、上記課題に鑑みてなされてものであり、この発明の電子部品搭載用の基板に搭載される電子部品よれば、下記のような構成上の特徴を有する。   The present invention has been made in view of the above problems, and according to the electronic component mounted on the electronic component mounting substrate of the present invention, the following structural features are provided.

すなわち、この発明の電子部品は、基板の主表面上に形成された導体部と電気的に接続される突起状導体部と、電子部品のうち突起状導体部が形成された面とは異なる面から基板の主表面に向かって延在するとともに、延在方向に有する長さは、電子部品の搭載時に、基板の主表面と接触可能な長さとされている補助導体部とを具えている。   That is, the electronic component of the present invention has a protruding conductor portion electrically connected to the conductor portion formed on the main surface of the substrate, and a surface different from the surface of the electronic component on which the protruding conductor portion is formed. The length extending in the direction toward the main surface of the substrate and extending in the extending direction includes an auxiliary conductor portion that is configured to be in contact with the main surface of the substrate when the electronic component is mounted.

この発明の電子部品によれば、補助導体部を設けることにより、電子部品と基板との間の伝熱経路を補強できるので、電子部品からの発熱を確実に基板に伝えることができる。   According to the electronic component of the present invention, by providing the auxiliary conductor portion, the heat transfer path between the electronic component and the substrate can be reinforced, so heat generated from the electronic component can be reliably transmitted to the substrate.

以下、図１〜図８を参照して、この発明の実施の形態につき説明する。尚、各図は、この発明が理解できる程度に各構成成分の形状、大きさ及び配置関係を概略的に示してあるに過ぎず、従って、この発明は図示例に限定されるものではない。また、図を分かり易くするために、断面を示すハッチングは、一部分を除き省略してある。尚、以下の説明は、単なる好適例に過ぎず、また、例示した数値的条件は何らこれに限定されない。また、各図において同様の構成成分については同一の番号を付して示し、その重複する説明を省略することもある。   Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Each drawing merely schematically shows the shape, size, and arrangement relationship of each component to such an extent that the present invention can be understood. Therefore, the present invention is not limited to the illustrated examples. Further, for easy understanding of the drawing, hatching indicating a cross section is omitted except for a part thereof. In addition, the following description is only a suitable example, and the illustrated numerical conditions are not limited to this at all. Moreover, in each figure, the same component is attached | subjected and shown, and the duplicate description may be abbreviate | omitted.

＜第１の実施の形態＞
図１は、この実施の形態の発熱源となる電子部品を搭載（あるいは、実装ともいう。）した実装構造を示す、概略断面図である。この実施の形態では、発熱源である電子部品を、半導体チップの外形寸法と実質的に同一の外形寸法を有する半導体パッケージであるＷＣＳＰ（Ｗａｆｅｒｌｅｖｅｌ Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）３０とし、プリント配線板２０に放熱機構を設けた場合を例に挙げて説明する。尚、実質的に同一とは、パッケージの外形寸法が半導体チップの外形寸法と全く同じ寸法である構成はもとより、パッケージの外形寸法が半導体チップの外形寸法に対して２０％程度まで大きな寸法となる構成も含まれるという意味である。 <First Embodiment>
FIG. 1 is a schematic cross-sectional view showing a mounting structure in which an electronic component serving as a heat generation source of this embodiment is mounted (also referred to as mounting). In this embodiment, the electronic component that is a heat source is a WCSP (Waferlevel Chip Size Package) 30 that is a semiconductor package having substantially the same external dimensions as the semiconductor chip, and the heat dissipation mechanism is provided on the printed wiring board 20. An example will be described in the case of providing. Note that “substantially the same” means that the outer dimensions of the package are exactly the same as the outer dimensions of the semiconductor chip, and the outer dimensions of the package are as large as about 20% of the outer dimensions of the semiconductor chip. It means that the configuration is also included.

ＷＣＳＰとは、半導体チップの外形サイズとほぼ同じパッケージサイズであるＣＳＰのうち、ウェハ状態のまま外部端子形成工程までを完了させた後、ダイシング等によって個片化したものをいう。また、プリント配線板とは、所定の回路設計に基づいて、導体パターンを絶縁性の基材の表面に、または表面及びその内部に、導体配線がパターニング形成されたものをいう。尚、プリント配線板２０に搭載される電子部品には、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）等を用いても良く、任意好適に選択することができる。   WCSP refers to a CSP that is approximately the same package size as the outer size of a semiconductor chip and that is separated into individual pieces by dicing or the like after completing the external terminal formation process in the wafer state. The printed wiring board refers to a conductive pattern formed on the surface of an insulating base material, or on the surface and inside thereof, based on a predetermined circuit design. In addition, BGA (Ball Grid Array) etc. may be used for the electronic component mounted in the printed wiring board 20, and it can select suitably.

図１に示すように、プリント配線板２０上に、ＷＣＳＰ３０が搭載されている。具体的には、プリント配線板２０が具える第２の導体部２７と、ＷＣＳＰ３０が具える第１の突起状導体部である半田ボール３９とが接触して電気的に接続されている。   As shown in FIG. 1, a WCSP 30 is mounted on the printed wiring board 20. Specifically, the second conductor portion 27 provided on the printed wiring board 20 and the solder ball 39 which is the first protruding conductor portion provided on the WCSP 30 are in contact and electrically connected.

先ず、電子部品であるＷＣＳＰ３０について説明する。ここでのＷＣＳＰ３０には従来公知の構造を適用できるので、以下に、その構造例について簡単に説明する。   First, the WCSP 30 that is an electronic component will be described. Since a conventionally known structure can be applied to the WCSP 30 here, an example of the structure will be briefly described below.

図１に示すように、回路素子（不図示）を具える半導体チップ３２上に、回路素子と電気的に接続された電極パッド３３の表面を露出させるように、パッシベーション膜３４及び保護膜３５が順次設けられている。パッシベーション膜３４は、例えば、シリコン酸化膜（ＳｉＯ2）で形成されている。保護膜３５は、ポリイミド樹脂等の低硬度の膜材で形成されており、半導体チップ３２に対する衝撃や、半導体チップ３２と後述する封止膜３８との間の応力による剥離を抑制する。配線層（再配線層とも称する。）３６は、保護膜３５上を半導体チップ３２の中心方向に延出している。そして、各電極パッド３３は、それぞれこれら配線層３６を介して、対応するポスト部３７と電気的に個別に接続されている。この配線層３６によって、ポスト部３７の端面（あるいは、頂面）上に形成される、突起状導体部である半田ボール３９を、電極パッド３３の直上の位置から半導体チップ３２の上側の所望位置に再配置することができる。 As shown in FIG. 1, a passivation film 34 and a protective film 35 are formed on a semiconductor chip 32 having a circuit element (not shown) so as to expose the surface of an electrode pad 33 electrically connected to the circuit element. It is provided sequentially. The passivation film 34 is made of, for example, a silicon oxide film (SiO 2 ). The protective film 35 is formed of a low-hardness film material such as polyimide resin, and suppresses an impact on the semiconductor chip 32 and peeling due to a stress between the semiconductor chip 32 and a sealing film 38 to be described later. A wiring layer (also referred to as a rewiring layer) 36 extends on the protective film 35 toward the center of the semiconductor chip 32. Each electrode pad 33 is electrically connected individually to the corresponding post portion 37 through the wiring layer 36. By this wiring layer 36, a solder ball 39, which is a protruding conductor portion, formed on the end surface (or top surface) of the post portion 37 is moved from a position directly above the electrode pad 33 to a desired position above the semiconductor chip 32. Can be rearranged.

続いて、上述したＷＣＳＰ３０を搭載している、プリント配線板２０について説明する。   Next, the printed wiring board 20 on which the above-described WCSP 30 is mounted will be described.

図１に示すように、ここでのプリント配線板２０は、基体としてのガラスエポキシ基材２２の表裏面、すなわち第１の主表面２２ａ及び第２の主表面２２ｂ上に、第２の導体部２７がパターニング形成されている。この第２の導体部２７は、銅箔（Ｃｕ）による導体配線である。   As shown in FIG. 1, the printed wiring board 20 here has a second conductor portion on the front and back surfaces of a glass epoxy base material 22 as a base, that is, on the first main surface 22a and the second main surface 22b. 27 is formed by patterning. The second conductor portion 27 is a conductor wiring made of copper foil (Cu).

このプリント配線板２０の基材２２には、当該基材２２の表裏面（２２ａ、２２ｂ）間を貫通する貫通孔（ビアホールあるいはスルーホールとも称する。）２２ｃが形成されている。そして、この貫通孔の内壁面２２ｄ上には、第１の導体部２６が、第２の導体部２７と連続するように形成されている。この第１の導体部２６は、導体配線を兼ねたサーマルビア部として機能する。また、図１に示されているように、半田ボール３９と接続される第２の導体部２７上の貫通孔２２ｃの周縁に、ストッパ２１が、レジスト材等によって形成されていても良い。このストッパ２１は、ＷＣＳＰ３０の搭載時に、半田が貫通孔２２ｃ内に流入するのを防止する機能を有している。   A through hole (also referred to as a via hole or a through hole) 22c penetrating between the front and back surfaces (22a, 22b) of the substrate 22 is formed in the substrate 22 of the printed wiring board 20. A first conductor portion 26 is formed on the inner wall surface 22 d of the through hole so as to be continuous with the second conductor portion 27. The first conductor portion 26 functions as a thermal via portion that also serves as a conductor wiring. Further, as shown in FIG. 1, the stopper 21 may be formed of a resist material or the like on the periphery of the through hole 22 c on the second conductor portion 27 connected to the solder ball 39. The stopper 21 has a function of preventing solder from flowing into the through hole 22c when the WCSP 30 is mounted.

第１の導体部２６は、基材２２に、ドリル等で貫通孔（図１に点線で示す。）２２ｃを形成した後、この内壁面２２ｄ上に、銅を、例えば、めっき形成して設けることができる。この第１の導体部２６の形成は、基材２２の表層に第２の導体部２７をパターニング形成する前に行う。   The first conductor portion 26 is provided by forming, for example, copper on the inner wall surface 22d after forming a through hole (shown by a dotted line in FIG. 1) 22c in the base material 22 with a drill or the like. be able to. The formation of the first conductor portion 26 is performed before the second conductor portion 27 is formed by patterning on the surface layer of the base material 22.

尚、この第１の導体部２６と上述した半田ボール３９とが直接接続する構成としても良いが、図１に示されているように、半田ボール３９を第２の導体部２７上に配置させることにより、搭載時の位置合わせ精度を緩和できて好ましい。また、この構成例のように、貫通孔２２ｃ内はもとより、第２の主表面２２ｂ上にわたって第２の導体部２７が形成されていることにより、プリント配線板２０の裏面２２ｂ側に確実に熱を伝えることができ放熱の点から好ましい。   The first conductor portion 26 and the above-described solder ball 39 may be directly connected, but the solder ball 39 is disposed on the second conductor portion 27 as shown in FIG. Therefore, it is preferable because the alignment accuracy at the time of mounting can be relaxed. Further, as in this configuration example, the second conductor portion 27 is formed not only in the through hole 22c but also on the second main surface 22b, so that heat can be reliably applied to the back surface 22b side of the printed wiring board 20. It is preferable from the viewpoint of heat dissipation.

この実施の形態では、上述した貫通孔２２ｃ内の第１の導体部２６上に、当該第１の導体部２６よりも熱放射率が高い第１の絶縁部２５が形成されている点を主たる特徴とする。   The main point of this embodiment is that the first insulating portion 25 having a higher thermal emissivity than the first conductor portion 26 is formed on the first conductor portion 26 in the through hole 22c described above. Features.

ここでは、第１の導体部よりも熱放射率の高い第１の絶縁部２５が、貫通孔２２ｃの内壁面上に形成された第１の導体部２６で画成されている中空部内を満たした構造である。   Here, the first insulating portion 25 having a higher heat emissivity than the first conductor portion fills the hollow portion defined by the first conductor portion 26 formed on the inner wall surface of the through hole 22c. Structure.

第１の絶縁部２５の材料としては、例えば、セラミックスを含有した塗料を使用するのが好ましい。セラミックスを含有した塗料は、熱伝導性を有するのはもとより、９０％以上の高い熱放射率を有するものが多く、高効率な熱放射を実現可能なためである。具体的には、Ａｌ2Ｏ3を主成分として含有するアルミナ系セラミックス等を使用することができる。また、例えば、特開平１０−２７９８４５号公報に記載されているようなセラミックスを含有したもの等を任意好適に使用することができる。また、熱放射率を向上させるための黒色顔料が添加された、セラミックス等であっても良い。 As a material for the first insulating portion 25, for example, a paint containing ceramics is preferably used. This is because ceramic-containing paints often have thermal conductivity and many have a high thermal emissivity of 90% or more, and can realize highly efficient thermal radiation. Specifically, alumina-based ceramics containing Al 2 O 3 as a main component can be used. Further, for example, those containing ceramics as described in JP-A-10-279845 can be suitably used. Moreover, the ceramic etc. which the black pigment for improving a thermal emissivity was added may be sufficient.

一般的に、サーマルビア部を兼ねた第１の導体部２６のみで放熱を行った場合（第１の導体部２６が貫通孔２２ｃ内を満たしている構造も含む。）には、対流伝熱によるサーマルビア部周辺の大気温度の上昇が不可避であった。   In general, when heat is radiated only by the first conductor portion 26 also serving as a thermal via portion (including a structure in which the first conductor portion 26 fills the through hole 22c), convective heat transfer is performed. It was inevitable that the atmospheric temperature around the thermal via was increased.

しかし、この実施の形態のように、第１の絶縁部２５が設けられていることにより、ＷＣＳＰ３０から第１の導体部２６に伝えられた熱を、第１の絶縁部２５から外部に赤外線として高効率に熱放射（あるいは、輻射とも称する。）させることができる。   However, since the first insulating portion 25 is provided as in this embodiment, the heat transferred from the WCSP 30 to the first conductor portion 26 is transmitted from the first insulating portion 25 to the outside as infrared rays. Heat radiation (or also referred to as radiation) can be performed with high efficiency.

その結果、サーマルビア部２６の周辺の大気温度の上昇を抑制でき、効率的な放熱を実現することができる。   As a result, an increase in the atmospheric temperature around the thermal via portion 26 can be suppressed, and efficient heat dissipation can be realized.

具体的には、貫通孔２２ｃ内が第１の導電部２６である銅のみの場合の熱伝導率が及び熱放射率が、それぞれ約１３７Ｗ／ｍ・Ｋ及び約０．０３であるのに対して、この構成例のように、第１の絶縁部２５であるアルミナ系セラミックスを貫通孔内２２ｃに設けた構成の場合の熱伝導率及び熱放射率は、約１６１Ｗ／ｍ・Ｋ及び約０．９２となる。   Specifically, the thermal conductivity and thermal emissivity in the case where only the copper that is the first conductive portion 26 is in the through hole 22c are about 137 W / m · K and about 0.03, respectively. Thus, as in this configuration example, the thermal conductivity and thermal emissivity in the configuration in which the alumina ceramics as the first insulating portion 25 are provided in the through hole 22c are about 161 W / m · K and about 0. .92.

このことからも明らかなように、第１の絶縁部を貫通孔２２ｃに設けることにより、チップ等の電子部品から伝わる熱を効率良く外部に放熱することができる。   As is clear from this, the heat transmitted from the electronic component such as the chip can be efficiently radiated to the outside by providing the first insulating portion in the through hole 22c.

尚、第１の絶縁部２５は、貫通孔２２ｃ内の第１の導体部２６上に所定膜厚で形成されていれば良いが、この構成例のように、第１の絶縁部２５が貫通孔２２ｃ内を満たしている、すなわち埋め込んでいることによって、放熱効果をさらに促進でき好ましい。   The first insulating portion 25 may be formed with a predetermined film thickness on the first conductor portion 26 in the through hole 22c. However, as in this configuration example, the first insulating portion 25 penetrates the first insulating portion 25. It is preferable that the inside of the hole 22c be filled, that is, buried, because the heat dissipation effect can be further promoted.

また、この実施の形態では、第２の主表面２２ｂ上に、第１の導体部２６よりも熱放射率が高い第２の絶縁部２８、及び上述した第２の導体部２７を介して第１の導体部２６よりも熱放射率が高い第３の絶縁部２９が形成されており、これらは第１の絶縁部２５と連続するように形成されている。よって、より一層高効率な熱放射を実現することができる。尚、ここでの第２及び第３の絶縁部（２８、２９）も、第１の絶縁部２５と同様にセラミックスを含有した塗料材料である。   In this embodiment, the second main surface 22b is provided with the second insulating portion 28 having a higher heat emissivity than the first conductor portion 26 and the second conductor portion 27 described above. A third insulating portion 29 having a thermal emissivity higher than that of the first conductor portion 26 is formed, and these are formed so as to be continuous with the first insulating portion 25. Therefore, it is possible to realize even more efficient heat radiation. Here, the second and third insulating portions (28, 29) are also paint materials containing ceramics, like the first insulating portion 25.

こうした第１、第２及び第３の絶縁部（２５、２８、２９）は、第２の主表面２２ｂ側から、例えば、スプレー法によって液状の赤外線放射性の絶縁体塗料を所定領域に塗布した後、熱硬化させることにより形成することができる。   The first, second, and third insulating portions (25, 28, 29) are applied to the predetermined region from the second main surface 22b side by applying, for example, a liquid infrared radioactive insulating paint by a spray method to a predetermined region. It can be formed by thermosetting.

上述した説明より、ここでのプリント配線板２０は、配線基板としての機能に加え、赤外線放射性の絶縁体による高効率な熱放射を実現可能とする、優れた放熱板としての機能を併せて具えている。   From the above description, in addition to the function as a wiring board, the printed wiring board 20 here also has a function as an excellent heat sink that can realize high-efficiency heat radiation by an infrared radioactive insulator. It is.

続いて、上述した構造のプリント配線板２０の放熱効果の検証を、放熱効果の指標となる「熱抵抗値（θｊａ）」を測定して行った。   Subsequently, the heat dissipation effect of the printed wiring board 20 having the above-described structure was verified by measuring a “thermal resistance value (θja)” that is an index of the heat dissipation effect.

先ず、図２を参照して、電子部品を、ＷＣＳＰ３０及びＢＧＡ５０とした場合の、熱抵抗値の測定方法の概要について説明する。   First, referring to FIG. 2, an outline of a method for measuring a thermal resistance value when electronic components are WCSP 30 and BGA 50 will be described.

図２（Ａ）は、電子部品をＷＣＳＰ３０とした場合の、熱抵抗値の測定方法の概要を説明するための概略図である。ここでのＷＣＳＰ３０には、沖電気工業（株）製 Ｐ−ＶＦＬＧＡ４８−０６０６−０．８を使用した。尚、このＷＣＳＰ３０の構造は、既に説明したＷＣＳＰ３０と実質的に同様であるため、ここではその説明を省略する。ここでは、半導体チップ３２とこの半導体チップ３２と接合するパッシベーション膜３４との境界の温度を接合部温度（Ｔj）とし、ＷＣＳＰ３０から所定距離離れた位置の温度を基準点温度（Ｔa）とした。   FIG. 2A is a schematic diagram for explaining an outline of a method for measuring a thermal resistance value when the electronic component is a WCSP 30. As the WCSP 30 here, P-VFLGA48-0606-0.8 manufactured by Oki Electric Industry Co., Ltd. was used. Note that the structure of the WCSP 30 is substantially the same as that of the WCSP 30 already described, and thus the description thereof is omitted here. Here, the temperature at the boundary between the semiconductor chip 32 and the passivation film 34 bonded to the semiconductor chip 32 is defined as a junction temperature (Tj), and the temperature at a predetermined distance from the WCSP 30 is defined as a reference point temperature (Ta).

図２（Ｂ）は、電子部品をＢＧＡ５０とした場合の、熱抵抗値の測定方法の概要を説明するための概略断面図である。ここでのＢＧＡ５０には、沖電気工業（株）製 Ｐ−ＢＧＡ３５２−３５３５−１．２７）を使用した。尚、このＢＧＡ５０の構造は、従来公知のワイヤボンディング方式と実質的に同様であるので、その構造については以下簡単に説明する。   FIG. 2B is a schematic cross-sectional view for explaining an outline of a method of measuring a thermal resistance value when the electronic component is BGA50. Oki Electric Industry Co., Ltd. P-BGA352-3535-1.27) was used for BGA50 here. The structure of the BGA 50 is substantially the same as that of a conventionally known wire bonding method, and the structure will be briefly described below.

図２（Ｂ）に示すように、絶縁基板５２上に、半導体チップ５３が、回路素子（不図示）形成面を上側にして搭載されている。回路素子と接続された電極パッド５４と、絶縁基板５２上の導体パターン５５とがワイヤ５６によって結線されている。これにより、所定の回路素子が、絶縁基板５２の表裏面間を貫通して設けられているコンタクト５７を介して、外部端子である半田ボール５８と電気的に接続されている。また、絶縁基板５２上には、半導体チップ５３を埋め込んで封止する樹脂封止膜５９が形成されている。ここでの導体パターン５５は、銅で形成されており、ワイヤ５６は金（Ａｕ）で形成されている。ここでは、半導体チップ５３とこの半導体チップ５３と接合する樹脂封止膜５９との境界の温度を接合部温度（Ｔj）とし、ＢＧＡ５０から所定距離離れた位置の温度を基準点温度（Ｔa）とした。   As shown in FIG. 2B, a semiconductor chip 53 is mounted on an insulating substrate 52 with a circuit element (not shown) formation surface facing upward. The electrode pad 54 connected to the circuit element and the conductor pattern 55 on the insulating substrate 52 are connected by a wire 56. As a result, a predetermined circuit element is electrically connected to the solder ball 58 that is an external terminal via the contact 57 provided so as to penetrate between the front and back surfaces of the insulating substrate 52. Further, a resin sealing film 59 is formed on the insulating substrate 52 so as to embed and seal the semiconductor chip 53. The conductor pattern 55 here is made of copper, and the wire 56 is made of gold (Au). Here, the temperature at the boundary between the semiconductor chip 53 and the resin sealing film 59 bonded to the semiconductor chip 53 is defined as a junction temperature (Tj), and the temperature at a predetermined distance from the BGA 50 is defined as a reference point temperature (Ta). did.

続いて、図２（Ｃ）を参照して、熱抵抗値の具体的な測定方法につき説明する。   Next, a specific method for measuring the thermal resistance value will be described with reference to FIG.

図２（Ｃ）に示すように、定電圧電源８１から、各半導体チップ（３２、５３）の接合部温度（Ｔj）測定位置近傍に設けられている抵抗体Ｒに、１Ｗの電力（＝Ｐｏｗｅｒ）を印加して発熱させ、熱飽和状態（あるいは、熱的平行状態ともいう。）とする。尚、印加電力（１Ｗ）の供給は、電流計８２及び電圧計８３を参照しながら定電圧電源８１を微調整して行う。   As shown in FIG. 2C, 1 W of power (= Power) is supplied from the constant voltage power supply 81 to the resistor R provided in the vicinity of the junction temperature (Tj) measurement position of each semiconductor chip (32, 53). ) Is applied to generate heat and become a heat saturated state (also referred to as a thermal parallel state). The applied power (1 W) is supplied by finely adjusting the constant voltage power supply 81 with reference to the ammeter 82 and the voltmeter 83.

そして、このときの接合部温度（Ｔj）を、抵抗体Ｒ近傍の半導体チップに設けられているダイオードＤに定電流電源８４から電流を流し、このときの電圧値を電圧計８５で測定することにより算出する。また、このときの基準点温度（Ｔa）を、熱電対（不図示）等を用いて測定する。   Then, the junction temperature (Tj) at this time is caused to flow from the constant current power supply 84 to the diode D provided in the semiconductor chip near the resistor R, and the voltage value at this time is measured by the voltmeter 85. Calculated by Further, the reference point temperature (Ta) at this time is measured using a thermocouple (not shown) or the like.

さらに、この構成例では、熱抵抗値への赤外線放射性の絶縁部の影響を検討すべく、図３に示すように、当該絶縁部の形成領域の異なる測定用のサンプルを用意した。図３では、電子部品をＷＣＳＰとした場合につき説明するが、ＢＧＡの場合についても同様である。   Further, in this configuration example, in order to examine the influence of the infrared radiation insulating portion on the thermal resistance value, as shown in FIG. 3, samples for measurement having different formation regions of the insulating portion were prepared. In FIG. 3, the case where the electronic component is WCSP will be described, but the same applies to the case of BGA.

サンプル(1)：赤外線放射性の絶縁部の形成無し（図３（Ａ））。尚、以下において、サンプル(1)をブランク(1)と称する場合がある。   Sample (1): No infrared radiation insulating portion is formed (FIG. 3A). In the following, sample (1) may be referred to as blank (1).

サンプル(2)：ＷＣＳＰ全面から第１主表面２２ａ上にわたって、赤外線放射性の第４の絶縁部２４が形成されている（図３（Ｂ））。尚、このとき絶縁部は、約１×１０-4ｍの膜厚とする。 Sample (2): A fourth insulating portion 24 having infrared radiation is formed from the entire WCSP to the first main surface 22a (FIG. 3B). At this time, the insulating portion has a film thickness of about 1 × 10 −4 m.

サンプル(3)：サンプル(2)で説明した領域に加えて、赤外線放射性の第１〜第３の絶縁部（２５、２８、２９）が、第２主表面２２ｂ及び貫通孔内２２ｃに形成されている（図３（Ｃ）参照）。尚、このとき絶縁部は、約１×１０-4ｍの膜厚とし、貫通孔２２ｃ内には充填する。 Sample (3): In addition to the region described in sample (2), first to third insulating portions (25, 28, 29) having infrared radiation are formed on the second main surface 22b and the through-hole 22c. (See FIG. 3C). At this time, the insulating portion has a thickness of about 1 × 10 −4 m and fills the through hole 22c.

こうして得られた各種パラメータによって、熱抵抗値θｊａを、下記に示す式（１）から算出することができる。
θｊａ［℃／Ｗ］＝（Ｔj−Ｔa）［℃］／Ｐｏｗｅｒ［Ｗ］ ・・・・（１） With the various parameters thus obtained, the thermal resistance value θja can be calculated from the following equation (1).
θja [° C./W]=(Tj−Ta) [° C.] / Power [W] (1)

尚、熱抵抗値の測定方法は、上述した方法のみに限定されるものではなく、各パラメータ（Ｔj、Ｔa）の測定条件を、例えば、ＪＥＤＥＣ（Ｊｏｉｎｔ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｅｎｇｉｎｅｅｒｉｎｇ Ｃｏｕｎｓｉｌ）規格等に基づいて行うほか、目的や設計に応じて任意好適な方法及び測定条件を選択することができる。   Note that the method of measuring the thermal resistance value is not limited to the above-described method, and the measurement conditions of each parameter (Tj, Ta) are performed based on, for example, the JEDEC (Joint Electron Engineering Engineering) standard. In addition, any suitable method and measurement conditions can be selected according to the purpose and design.

図４に、熱抵抗値θｊａの測定結果をに示す。図４（Ａ）は、電子部品をＷＣＳＰとした場合の測定結果であり、図４（Ｂ）は、電子部品をＢＧＡとした場合の測定結果である。ここでは、ブランク(1)の熱抵抗値を基準値としたときの各条件の熱抵抗値を棒グラフとして示すとともに、ブランク(1)の熱抵抗値に対する低減率（％）併せて付記してある。   FIG. 4 shows the measurement result of the thermal resistance value θja. FIG. 4A shows the measurement result when the electronic component is WCSP, and FIG. 4B shows the measurement result when the electronic component is BGA. Here, the thermal resistance value of each condition when the thermal resistance value of the blank (1) is used as a reference value is shown as a bar graph, and the reduction rate (%) with respect to the thermal resistance value of the blank (1) is also appended. .

図４（Ａ）及び（Ｂ）に示す測定結果から、電子部品がＷＣＳＰ及びＢＧＡのいずれの場合においても、赤外線放射性の絶縁部が設けられていることにより、熱抵抗値が６．３〜１２．９％及び４．０〜６．５％の割合で、それぞれ低減することが確認された。   From the measurement results shown in FIGS. 4A and 4B, the thermal resistance value is 6.3 to 12 because the infrared radiation insulating portion is provided in any case where the electronic component is WCSP or BGA. It was confirmed that the ratios were reduced by 0.9% and 4.0-6.5%, respectively.

このことから、放熱フィン等の放熱部品を別途搭載せずとも、電子部品の放熱効率の向上を実現できることが判る。   From this, it can be seen that the heat dissipation efficiency of the electronic component can be improved without separately mounting a heat dissipation component such as a heat dissipation fin.

また、サンプル(2)の結果から、赤外線放射性の絶縁部で電子部品全面が覆われた構造によっても良好な放熱効果を得られるが、さらに、サンプル(3)のように、貫通孔内の導体部上や基板の裏面上に同絶縁部が設けてあることにより、一層放熱効果が促進されることが確認された。   Also, from the results of sample (2), a good heat dissipation effect can be obtained even by a structure in which the entire surface of the electronic component is covered with an infrared radiation insulating part. Further, as in sample (3), the conductor in the through hole is obtained. It was confirmed that the heat dissipation effect was further promoted by providing the insulating part on the part and the back surface of the substrate.

上述した説明から明らかなように、この実施の形態によれば、電子部品を搭載するプリント配線板等に設けられた貫通孔の内壁面上に形成された導体部上に、当該導体部よりも熱放射率が高い絶縁部が形成されている。   As is apparent from the above description, according to this embodiment, the conductor portion formed on the inner wall surface of the through hole provided in the printed wiring board or the like on which the electronic component is mounted is more than the conductor portion. An insulating part having a high thermal emissivity is formed.

その結果、電子部品から導体部を経て絶縁部に伝えられた熱を、当該絶縁部から赤外線として高効率に放射させることができるので、放熱フィン等の放熱部品を別途搭載せずに放熱効果を促進させることができる。   As a result, the heat transferred from the electronic component to the insulating portion through the conductor portion can be radiated from the insulating portion as infrared rays with high efficiency. Can be promoted.

＜第２の実施の形態＞
図５を参照して、この発明の第２の実施の形態につき説明する。 <Second Embodiment>
A second embodiment of the present invention will be described with reference to FIG.

第１の実施の形態では、パッケージを搭載するマザーボード用基板に放熱効果を促進させるための赤外線放射性の絶縁部が形成されていたが、この実施の形態では、マザーボード用基板に実装可能なインターポーザ用基板に対して、第１の実施の形態と同様の赤外線放射性の絶縁部が形成されている点、及び当該インターポーザー用基板上全面に、電子部品の外面を覆うように熱放射用の絶縁部が形成されている点が主な相違点である。尚、第１の実施の形態で既に説明した構成要素と同一の構成要素には同一の番号を付して示しており、その具体的な説明を省略する（以下の各実施の形態についても同様）。   In the first embodiment, an infrared radiation insulating portion for promoting the heat dissipation effect is formed on the motherboard for mounting the package. However, in this embodiment, for the interposer that can be mounted on the motherboard for the motherboard. An infrared radiation insulating portion similar to that of the first embodiment is formed on the substrate, and an insulating portion for heat radiation is formed on the entire surface of the interposer substrate so as to cover the outer surface of the electronic component. The main difference is that is formed. The same components as those already described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted (the same applies to the following embodiments). ).

この構成例では、パッケージのインターポーザ用基板として、ＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）用の基板を例に挙げて説明する。ＭＣＭとは、１枚の高密度基板に、例えば、複数のパッケージ及びその周辺の部品類を搭載してモジュール化したものをいう。尚、ＭＣＭ用の基板には、このほかに、ベアチップを搭載する構造のものも含まれる。   In this configuration example, an MCM (Multi Chip Module) substrate will be described as an example of a package interposer substrate. MCM refers to a module formed by mounting a plurality of packages and their peripheral components on a single high-density substrate. In addition to the above, the substrate for MCM includes a structure in which a bare chip is mounted.

具体的には、図５に示すように、ＭＣＭ用基板７０上に、例えば、フラッシュメモリ等の構成部分としてのＷＣＳＰが複数搭載されている。尚、ＷＣＳＰの構造については、第１の実施の形態で既に説明してあるのでここでは省略する。   Specifically, as shown in FIG. 5, for example, a plurality of WCSPs as components such as a flash memory are mounted on the MCM substrate 70. Since the structure of the WCSP has already been described in the first embodiment, it is omitted here.

ここでのＭＣＭ用基板７０は、ガラスエポキシ基材７２の表裏面、すなわち第１の主表面７２ａ及び第２の主表面７２ｂ上に、銅箔による第２の導体部７７がパターニング形成されている。   In this MCM substrate 70, the second conductor portion 77 made of copper foil is patterned on the front and back surfaces of the glass epoxy base material 72, that is, on the first main surface 72 a and the second main surface 72 b. .

そして、このＭＣＭ用基板７０の基材７２には、基材の表裏面（７２ａ、７２ｂ）間を貫通する貫通孔７２ｃが形成されており、この貫通孔の内壁面７２ｄ上に、導体配線を兼ねたサーマルビア部として機能する、第１の導体部７６が形成されている。また、第１の導体部７６は、第１及び第２の主表面（７２ａ、７２ｂ）上の第２の導体部７７と連続するように形成されている。   The base material 72 of the MCM substrate 70 is formed with a through hole 72c that penetrates between the front and back surfaces (72a, 72b) of the base material. Conductor wiring is provided on the inner wall surface 72d of the through hole. A first conductor portion 76 is formed which functions as a thermal via portion that also serves as the thermal via portion. The first conductor portion 76 is formed to be continuous with the second conductor portion 77 on the first and second main surfaces (72a, 72b).

そして、この貫通孔７２ｃ内の第１の導体部７６上に、当該第１の導体部７６よりも熱放射率が高い第１の絶縁部７５が形成されている。ここでも、第１の実施の形態と同様に、第１の絶縁部７５が、貫通孔７２ｃの内壁面上の第１の導体部７６で画成されている中空部内を満たした、すなわち埋め込んでいる構造である。また、第２の主表面７２ｂ上には、第１の導体部７６よりも熱放射率が高い第２の絶縁部７８、及び上述した第２の導体部７７を介して第１の導体部７６よりも熱放射率が高い第３の絶縁部７９が形成されており、これらは第１の絶縁部７５と連続するように形成されている。   A first insulating portion 75 having a higher thermal emissivity than the first conductor portion 76 is formed on the first conductor portion 76 in the through hole 72c. Here too, as in the first embodiment, the first insulating portion 75 fills, that is, embeds, the hollow portion defined by the first conductor portion 76 on the inner wall surface of the through hole 72c. It is a structure. Further, on the second main surface 72b, the first conductor portion 76 is interposed via the second insulating portion 78 having a higher heat emissivity than the first conductor portion 76 and the above-described second conductor portion 77. A third insulating portion 79 having a higher thermal emissivity than the third insulating portion 79 is formed, and these are formed so as to be continuous with the first insulating portion 75.

また、この構成例では、ＭＣＭ用基板７０の第１の主表面７２ａ全面に、電子部品３０を覆うように熱放射用の第４の絶縁部７４が形成されている。   In this configuration example, the fourth insulating portion 74 for heat radiation is formed on the entire first main surface 72 a of the MCM substrate 70 so as to cover the electronic component 30.

さらに、この実施の形態では、ＭＣＭ用基板７０の第２の主表面７２ｂ側に、当該ＭＣＭ用基板７０をマザーボード用の基板８８に搭載可能な、第２の突起状導体部としての半田ボール８０が形成されている。   Further, in this embodiment, the solder balls 80 as the second projecting conductor portions that can be mounted on the motherboard substrate 88 on the second main surface 72 b side of the MCM substrate 70. Is formed.

この構成によれば、半田ボール８０は、ＭＣＭ用基板７０の第２の主表面７２ｂ上に設けられた第２の導体部７７と、ＭＣＭ用基板７０の貫通孔（不図示）内に設けられ当該第２の導体部７７と電気的に接続された第１の導体部（不図示）と、第１の主表面７２ａ上に設けられ当該第１の導体部と電気的に接続された第２の導体部７７とを介して、半田ボール３９に接続されている。   According to this configuration, the solder ball 80 is provided in the second conductor portion 77 provided on the second main surface 72b of the MCM substrate 70 and the through hole (not shown) of the MCM substrate 70. A first conductor portion (not shown) electrically connected to the second conductor portion 77 and a second conductor portion provided on the first main surface 72a and electrically connected to the first conductor portion. This is connected to the solder ball 39 via the conductor portion 77.

ここでの第１、第２、及び第３の絶縁部（７５、７８、７９）の材料も、第１の実施の形態と同様に、例えば、セラミックスを含有した塗料を使用するのが好ましい。セラミックスを含有した塗料は、熱伝導性を有するのはもとより、９０％以上の高い熱放射率を有するものが多く、高効率な熱放射を実現可能なためである。具体的には、Ａｌ2Ｏ3を主成分として含有するアルミナ系セラミックス等を使用することができる。また、例えば、特開平１０−２７９８４５号公報に記載されているようなセラミックスを含有したもの等を任意好適に使用することができる。また、熱放射率を向上させるための黒色顔料が添加されたセラミックス等であっても良い。 As for the material of the first, second, and third insulating portions (75, 78, 79) here, it is preferable to use, for example, a paint containing ceramics, as in the first embodiment. This is because ceramic-containing paints often have thermal conductivity and many have a high thermal emissivity of 90% or more, and can realize highly efficient thermal radiation. Specifically, alumina-based ceramics containing Al 2 O 3 as a main component can be used. Further, for example, those containing ceramics as described in JP-A-10-279845 can be suitably used. Moreover, the ceramic etc. to which the black pigment for improving a thermal emissivity was added may be sufficient.

上述した説明から明らかなように、この実施の形態によれば、第１の実施の形態と同様の効果を得ることができる。   As is apparent from the above description, according to this embodiment, the same effect as that of the first embodiment can be obtained.

さらに、この実施の形態では、このような放熱効果を有する基板を、他の基板を搭載可能なＭＣＭ用基板等のインターポーザ用基板にも適用することができる。   Furthermore, in this embodiment, a substrate having such a heat dissipation effect can be applied to an interposer substrate such as an MCM substrate on which another substrate can be mounted.

また、この実施の形態によれば、インターポーザ用基板７０上全面に、電子部品を覆うように熱放射用の絶縁部が形成されている。その結果、外部へのより一層高効率な熱放射を実現することができる。   Further, according to this embodiment, the insulating portion for heat radiation is formed on the entire surface of the interposer substrate 70 so as to cover the electronic component. As a result, more efficient heat radiation to the outside can be realized.

＜第３の実施の形態＞
図６を参照して、この発明の第３の実施の形態につき説明する。 <Third Embodiment>
A third embodiment of the present invention will be described with reference to FIG.

この実施の形態では、放熱効果を促進させるための加工が、主として電子部品側に施されている点が、第１の実施の形態との主な相違点である。   In this embodiment, the main difference from the first embodiment is that the processing for promoting the heat dissipation effect is performed mainly on the electronic component side.

図６に示すように、この実施の形態の電子部品４０が、電子部品４０からの熱を当該電子部品４０を搭載する基板６０側に効率良く伝えるための補助導体部（以下、金属サポート部と称する場合がある。）４５を具えている点を主たる特徴とする。尚、金属サポート部４５には、銅などの熱伝導性に優れた材料を任意好適に選択することができる。   As shown in FIG. 6, the electronic component 40 of this embodiment efficiently transmits heat from the electronic component 40 to the side of the substrate 60 on which the electronic component 40 is mounted (hereinafter referred to as a metal support portion). The main feature is that it has 45. For the metal support portion 45, a material having excellent thermal conductivity such as copper can be arbitrarily selected.

ここでは、電子部品４０を、基板搭載用の突起状導体部である半田ボール３９を具える、ＷＣＳＰとし、基板６０を一般的なプリント配線板とした場合を例に挙げて説明する。   Here, the case where the electronic component 40 is a WCSP including a solder ball 39 which is a protruding conductor portion for mounting on a substrate and the substrate 60 is a general printed wiring board will be described as an example.

図６に示すように、この実施の形態では、金属サポート部４５が、半田ボール３９が形成されている面とは異なるＷＣＳＰ４０の表面上から、基板の主表面６０ａに向かって延在しており、このとき延在方向に有する長さが基板の主表面６０ａと接触する長さである点を第１の特徴とする。   As shown in FIG. 6, in this embodiment, the metal support portion 45 extends from the surface of the WCSP 40 different from the surface on which the solder balls 39 are formed, toward the main surface 60a of the substrate. The first characteristic is that the length in the extending direction at this time is the length in contact with the main surface 60a of the substrate.

尚、ここでの金属サポート部４５の延在方向の端部は、ＷＣＳＰ４０に対して非対向な方向、すなわちＷＣＳＰに対して外側に離れる方向に折り曲げられた形状であるがこれに限定されるものではなく、基板の主表面６０ａと接触する部分を有していれば良い。よって、金属サポート部４５の延在方向に有する長さは、例えば、基板６０の主表面６０ａを突き抜けて基板６０に埋め込まれる長さ等であっても良く、目的や設計に応じて種々の形状を任意好適に選択することができる（詳細後述）。   Here, the end portion of the metal support portion 45 in the extending direction is bent in a direction not facing the WCSP 40, that is, a direction away from the WCSP, but is not limited thereto. Instead, it suffices to have a portion that contacts the main surface 60a of the substrate. Therefore, the length of the metal support portion 45 in the extending direction may be, for example, a length that penetrates the main surface 60a of the substrate 60 and is embedded in the substrate 60, and has various shapes depending on the purpose and design. Can be arbitrarily selected (details will be described later).

また、このとき、金属サポート部４５は、ＷＣＳＰ４０の表面うち、半導体チップ３２を構成するシリコン（Ｓｉ）基板３２の露出面上の広い領域を覆うように設けられているのが良い。発熱源となる回路素子を含むシリコン表面から発生する熱を、効率良く絶縁部４７及び基板６０に伝えることができるためである。   At this time, the metal support portion 45 may be provided so as to cover a wide area on the exposed surface of the silicon (Si) substrate 32 constituting the semiconductor chip 32 in the surface of the WCSP 40. This is because heat generated from the silicon surface including the circuit element serving as a heat source can be efficiently transmitted to the insulating portion 47 and the substrate 60.

このような、熱導電性の優れた金属サポート部を設けることにより、ＷＣＳＰ４０の裏面（すなわち、半導体チップの裏面３２ｂ）及び側面（すなわち、半導体チップの側面３２ｃ）における熱が素早く絶縁部４７へと伝わるのに加えて、基板６０へも素早く伝わる。すなわち、ＷＣＳＰ４０と絶縁部４７との間、及びＷＣＳＰ４０と基板６０との間の伝熱経路を補強できるので、ＷＣＳＰ４０からの熱を確実に基板６０に伝えることができる。   By providing such a metal support portion with excellent thermal conductivity, heat on the back surface (that is, the back surface 32b of the semiconductor chip) and the side surface (that is, the side surface 32c of the semiconductor chip) of the WCSP 40 is quickly transferred to the insulating portion 47. In addition to being transmitted, it is also quickly transmitted to the substrate 60. That is, since the heat transfer path between the WCSP 40 and the insulating portion 47 and between the WCSP 40 and the substrate 60 can be reinforced, the heat from the WCSP 40 can be reliably transmitted to the substrate 60.

さらに、この実施の形態では、金属サポート部４５上に、赤外線放射性の絶縁部４７が形成されている点を第２の特徴とする。   Furthermore, this embodiment has a second feature in that an infrared radiation insulating portion 47 is formed on the metal support portion 45.

この構成例では、赤外線放射性の絶縁部４７が、金属サポート部４５上を含むＷＣＳＰ４０全面を覆い、かつ基板６０の主表面６０ａ上にわたって形成されている。この絶縁部４７は、金属サポート部４５上に所定膜厚で形成された構成であっても良いが、このように、サポート部４５上を含む広範な領域に設けてあることにより熱放射の面積がより広がるので、より一層放熱効果を促進できる。   In this configuration example, the infrared radiation insulating portion 47 is formed over the main surface 60 a of the substrate 60 while covering the entire surface of the WCSP 40 including the metal support portion 45. The insulating portion 47 may have a structure formed on the metal support portion 45 with a predetermined film thickness. However, since the insulating portion 47 is provided in a wide area including the support portion 45 as described above, the area of heat radiation is reduced. Since it spreads more, the heat dissipation effect can be further promoted.

また、ここでの絶縁部４７の材料も、第１の実施の形態と同様に、例えば、セラミックスを含有した塗料を使用するのが好ましい。セラミックスを含有した塗料は、熱伝導性を有するのはもとより、９０％以上の高い熱放射率を有するものが多く、高効率な熱放射を実現可能なためである。具体的には、Ａｌ2Ｏ3を主成分として含有するアルミナ系セラミックス等を使用することができる。また、例えば、特開平１０−２７９８４５号公報に記載されているようなセラミックスを含有したもの等を任意好適に使用することができる。また、熱放射率を向上させるための黒色顔料が添加されたセラミックス等であっても良い。 In addition, the material of the insulating portion 47 here is preferably a paint containing ceramics, for example, as in the first embodiment. This is because ceramic-containing paints often have thermal conductivity and many have a high thermal emissivity of 90% or more, and can realize highly efficient thermal radiation. Specifically, alumina-based ceramics containing Al 2 O 3 as a main component can be used. Further, for example, those containing ceramics as described in JP-A-10-279845 can be suitably used. Moreover, the ceramic etc. to which the black pigment for improving a thermal emissivity was added may be sufficient.

ここでの絶縁部４７は、金属サポート部４５をＷＣＳＰ４０上に形成した後、基板の主表面６０ａ側から、例えば、スプレー法によって液状の赤外線放射性の絶縁体塗料を所定領域に塗布した後、熱硬化させることにより形成することができる。   Here, the insulating portion 47 is formed by, after forming the metal support portion 45 on the WCSP 40, applying a liquid infrared radioactive insulating paint on a predetermined region from the main surface 60a side of the substrate, for example, by a spray method, It can be formed by curing.

こうして、金属サポート部４５を介して基板６０側に確実に伝えられたＷＣＳＰ４０からの熱を、絶縁部４７によって高い熱放射率で赤外線に変換して外部に放出させることができるので、放熱効果を促進させることができる。   In this way, the heat from the WCSP 40 that is reliably transmitted to the substrate 60 side through the metal support part 45 can be converted into infrared rays with a high thermal emissivity by the insulating part 47 and released to the outside. Can be promoted.

続いて、図７を参照して、金属サポート部４５の形状の具体例について説明する。図７（Ａ）から図７（Ｃ）の下段は、図６に示す構造を、図中矢印Ｐ方向から見たときの概略断面図、及び上段は、下段に対応する金属サポート部４５の展開図である。ここでは、赤外線放射性の絶縁部４７の図示は省略してある。また、以下に説明する金属サポート部４５のＷＣＳＰ４０への固定は、成形された金属サポート部４５を所定温度で加熱してＷＣＳＰ４０に溶着する等、任意好適な方法を用いることができる。   Next, a specific example of the shape of the metal support portion 45 will be described with reference to FIG. 7A to 7C are schematic cross-sectional views when the structure shown in FIG. 6 is viewed from the direction of arrow P in the drawing, and the upper stage is a development of the metal support portion 45 corresponding to the lower stage. FIG. Here, the illustration of the infrared radiation insulating portion 47 is omitted. The metal support portion 45 described below can be fixed to the WCSP 40 by any suitable method such as heating the molded metal support portion 45 at a predetermined temperature and welding it to the WCSP 40.

図７（Ａ）の金属サポート部４５１は、ＷＣＳＰ４０全面を完全に覆う形状である。このような形状によって、応力集中に対する懸念はあるものの、シリコン表面から発生した熱を確実に基板６０側に伝えることができる。尚、こうした形状は、エッチング処理等を用いて成形することができる。   7A has a shape that completely covers the entire surface of the WCSP 40. With such a shape, although there is a concern about stress concentration, heat generated from the silicon surface can be reliably transmitted to the substrate 60 side. Such a shape can be formed using an etching process or the like.

図７（Ｂ）の金属サポート部４５２は、半導体チップ３２の裏面３２ｂ全面を覆う形状である点が、図７（Ａ）の金属サポート部４５１と相違している。このような形状とすることによって、半導体チップを構成するシリコン基板表面から発生した熱を効率良く基板６０に伝えることができる。尚、こうした形状は、エッチング処理等を用いて成形することができる。   The metal support part 452 in FIG. 7B is different from the metal support part 451 in FIG. 7A in that the metal support part 452 has a shape covering the entire back surface 32b of the semiconductor chip 32. With such a shape, heat generated from the surface of the silicon substrate constituting the semiconductor chip can be efficiently transmitted to the substrate 60. Such a shape can be formed using an etching process or the like.

図７（Ｃ）の金属サポート部４５３は、ＷＣＳＰ４０の裏面及び側面を網目状に覆う形状である。基板の主表面６０ａからＷＣＳＰ４０方向に延びるスリット４９が形成されていることにより、基板６０とＷＣＳＰ４０との境界で発生する、熱膨張係数の差による応力集中を緩和することができる。また、網目模様を含むこうした平板状の銅板は、金型等を用いて比較的容易に成形できるので、製造コストの点で優れている。   The metal support portion 453 in FIG. 7C has a shape that covers the back and side surfaces of the WCSP 40 in a mesh shape. By forming the slits 49 extending from the main surface 60a of the substrate in the direction of the WCSP 40, stress concentration caused by the difference in thermal expansion coefficient that occurs at the boundary between the substrate 60 and the WCSP 40 can be reduced. In addition, such a flat copper plate including a mesh pattern is excellent in terms of manufacturing cost because it can be formed relatively easily using a mold or the like.

続いて、図８を参照して、金属サポート部４５（４５１、４５２、４５３（図７参照）等）の端部、すなわち基板の主表面６０ａと接触する端部の形状の具体例について説明する。   Next, a specific example of the shape of the end of the metal support portion 45 (451, 452, 453 (see FIG. 7), etc.), that is, the end contacting the main surface 60a of the substrate will be described with reference to FIG. .

図８（Ａ）では、金属サポート部４５の端部に、基板の主表面６０ａを突き抜けて基板６０に埋め込まれる、接続ピン６５が形成されている。このような接続ピン６５が設てあることにより、基板６０に搭載したＷＣＳＰ４０が、外部からの衝撃によって位置ズレを起こすのを防止でき、安定した搭載状態を維持することができる。このときの金属サポート部は、例えば、平板状の銅板の端部（例えば、図７（Ａ）でＱで示す位置）に、銅によって別途形成した接続ピン６５を当該銅板に対して鉛直に溶着するなどして作製することができる。そして、この接続ピン６５を、例えば、あらかじめドリル等で形成しておいた基板６０の細孔に嵌め込んで固定すれば良い。   In FIG. 8A, a connection pin 65 that penetrates through the main surface 60 a of the substrate and is embedded in the substrate 60 is formed at the end of the metal support portion 45. By providing such a connection pin 65, it is possible to prevent the WCSP 40 mounted on the substrate 60 from being displaced due to an external impact, and a stable mounting state can be maintained. At this time, the metal support part is, for example, welded to the end part of the flat copper plate (for example, the position indicated by Q in FIG. 7A) by vertically connecting the connection pin 65 formed of copper to the copper plate. It is possible to make it. Then, the connection pins 65 may be fixed by being fitted into the pores of the substrate 60 previously formed by a drill or the like, for example.

図８（Ｂ）では、金属サポート部４５の端部自体が接続ピン６７である点が、図８（Ａ）と相違している。この形状の場合には、別途接続ピンを溶着する必要が無いので製造コストの点で優れている。このときのサポート部は、あらかじめ、接続ピンとなる基板６０への埋め込み分を考慮して平板状の銅板を加工しておくなどして作製することができる。また、図８（Ａ）と同様、安定した搭載状態を維持することができ好適である。   8B is different from FIG. 8A in that the end portion of the metal support portion 45 itself is a connection pin 67. In the case of this shape, there is no need to weld a separate connection pin, which is excellent in terms of manufacturing cost. The support portion at this time can be manufactured by processing a flat copper plate in advance in consideration of the portion embedded in the substrate 60 to be the connection pin. Further, as in FIG. 8A, a stable mounting state can be maintained, which is preferable.

図８（Ｃ）では、金属サポート部４５の端部が、ＷＣＳＰ４０と対向する方向に折り曲げられている。そのため、導電体である接続ピンを埋め込む上記の構造と比較して、当該接続ピンの設置による配線設計の自由度が抑制されることがない点で優れている。   In FIG. 8C, the end portion of the metal support portion 45 is bent in a direction facing the WCSP 40. Therefore, it is excellent in that the degree of freedom in wiring design due to the installation of the connection pin is not suppressed as compared with the above structure in which the connection pin that is a conductor is embedded.

尚、赤外線放射性の絶縁部や金属サポート部の形状は、上述した形状のみに限定されず、目的や設計に応じて種々の形状とすることができる。   In addition, the shape of an infrared radiation insulation part and a metal support part is not limited only to the shape mentioned above, It can be set as various shapes according to the objective and design.

上述した説明から明らかなように、この実施の形態によれば、金属サポート部を設けることにより、電子部品と基板との間の伝熱経路を補強できるので、電子部品からの発熱を確実に基板に伝えることができる。   As is clear from the above description, according to this embodiment, by providing the metal support portion, the heat transfer path between the electronic component and the substrate can be reinforced, so heat generation from the electronic component is reliably performed on the substrate. Can tell.

その結果、基板側に確実に伝えられた熱を、赤外線放射性の絶縁部４７により赤外線に高効率に変換して放射することができ、放熱効果を促進させることができる。   As a result, the heat transmitted to the substrate side can be radiated by converting it into infrared rays with high efficiency by the infrared radiation insulating portion 47, and the heat dissipation effect can be promoted.

以上、この発明は、上述した実施の形態のみに限定されない。よって、任意好適に上記条件を組み合わせて、この発明を適用することができる。   As mentioned above, this invention is not limited only to embodiment mentioned above. Therefore, the present invention can be applied by arbitrarily combining the above conditions.

この発明の第１の実施の形態の説明に供する概略断面図である。It is a schematic sectional drawing with which it uses for description of 1st Embodiment of this invention. この発明の第１の実施の形態の、熱抵抗値の測定方法の概要を説明する概略図（その１）である。It is the schematic (the 1) explaining the outline | summary of the measuring method of the thermal resistance value of 1st Embodiment of this invention. この発明の第１の実施の形態の、熱抵抗値の測定方法の概要を説明する概略図（その２）であるIt is the schematic (the 2) explaining the outline | summary of the measuring method of the thermal resistance value of 1st Embodiment of this invention. この発明の第１の実施の形態の熱抵抗値の測定結果を示す図である。It is a figure which shows the measurement result of the thermal resistance value of 1st Embodiment of this invention. この発明の第２の実施の形態の説明に供する概略断面図である。It is a schematic sectional drawing with which it uses for description of 2nd Embodiment of this invention. この発明の第３の実施の形態の説明に供する概略断面図である。It is a schematic sectional drawing with which it uses for description of 3rd Embodiment of this invention. この発明の第３の実施の形態の、金属サポート部の説明に供する図（その１）である。It is a figure (the 1) with which it uses for description of the metal support part of 3rd Embodiment of this invention. この発明の第３の実施の形態の、金属サポート部の説明に供する図（その２）である。It is FIG. (The 2) with which it uses for description of the metal support part of 3rd Embodiment of this invention.

符号の説明Explanation of symbols

２０：プリント配線板（放熱板）
２２、７２：ガラスエポキシ基材（基体）
２２ａ、７２ａ：第１の主表面
２２ｂ、７２ｂ：第２の主表面
２２ｃ、７２ｃ：貫通孔
２２ｄ、７２ｄ：内壁面
２４：赤外線放射性の第４の絶縁部
２５、７５：赤外線放射性の第１の絶縁部
２６、７６：第１の導体部
２７、７７：第２の導体部
２８、７８：赤外線放射性の第２の絶縁部
２９、７９：赤外線放射性の第３の絶縁部
３０、４０：ＷＣＳＰ（電子部品）
３２：半導体チップ
３２ｂ：半導体チップの裏面
３２ｃ：半導体チップの側面
３３：電極パッド
３４：パッシベーション膜
３５：保護膜
３６：配線層（再配線層）
３７：ポスト部
３８：封止膜
３９：半田ボール（第１の突起状導体部）
４５、４５１、４５２、４５３：金属サポート部（補助導体部）
４７：赤外線放射性の絶縁部
４９：スリット
５０：ＢＧＡ（電子部品）
５２：絶縁基板
５３：半導体チップ
５４：電極パッド
５５：導体パターン
５６：ワイヤ
５７：コンタクト
５８：半田ボール
５９：樹脂封止膜
６０：プリント配線板（基板）
６０ａ：基板の主表面
６５、６７：接続ピン
７０：ＭＣＭ用基板
７４：第４の絶縁部
８０：半田ボール（第２の突起状導体部）
８１：定電圧電源
８２：電流計
８３、８５：電圧計
８４：定電流電源
８８：基板

20: Printed wiring board (heat sink)
22, 72: Glass epoxy substrate (substrate)
22a, 72a: 1st main surface 22b, 72b: 2nd main surface 22c, 72c: Through-hole 22d, 72d: Inner wall surface 24: Infrared radiation 4th insulation part 25, 75: Infrared radiation 1st Insulating parts 26, 76: first conductor part 27, 77: second conductor part 28, 78: infrared radiation second insulation part 29, 79: infrared radiation third insulation part 30, 40: WCSP ( Electronic components)
32: Semiconductor chip 32b: Back surface of semiconductor chip 32c: Side surface of semiconductor chip 33: Electrode pad 34: Passivation film 35: Protective film 36: Wiring layer (rewiring layer)
37: Post part 38: Sealing film 39: Solder ball (first protruding conductor part)
45, 451, 452, 453: Metal support part (auxiliary conductor part)
47: Infrared radiation insulating part 49: Slit 50: BGA (electronic component)
52: Insulating substrate 53: Semiconductor chip 54: Electrode pad 55: Conductor pattern 56: Wire 57: Contact 58: Solder ball 59: Resin sealing film 60: Printed wiring board (substrate)
60a: Main surface of substrate 65, 67: Connection pin 70: Substrate for MCM 74: Fourth insulating portion 80: Solder ball (second protruding conductor portion)
81: Constant voltage power supply 82: Ammeter 83, 85: Voltmeter 84: Constant current power supply 88: Board

Claims (16)

電子部品搭載用の基板の主表面上に搭載される電子部品であって、
前記基板の主表面上に形成された導体部と電気的に接続される突起状導体部と、
前記電子部品のうち該突起状導体部が形成された面とは異なる面から前記基板の主表面に向かって延在するとともに、該延在方向に有する長さは、前記電子部品の搭載時に、前記基板の主表面と接触可能な長さとされている補助導体部と
を具えていることを特徴とする電子部品。 An electronic component mounted on the main surface of a substrate for mounting an electronic component,
A protruding conductor portion electrically connected to a conductor portion formed on the main surface of the substrate;
While extending from the surface of the electronic component different from the surface on which the protruding conductor portion is formed toward the main surface of the substrate, the length in the extending direction is determined when the electronic component is mounted. An electronic component comprising an auxiliary conductor portion having a length capable of contacting the main surface of the substrate. 請求項１に記載の電子部品において、
前記補助導体部の延在方向に有する長さは、前記電子部品の搭載時に、前記主表面を突き抜ける長さとされていることを特徴とする電子部品。 The electronic component according to claim 1,
The length of the auxiliary conductor portion extending in the extending direction is a length that penetrates the main surface when the electronic component is mounted. 請求項１に記載の電子部品において、
前記補助導体部の延在方向の端部は、前記電子部品の搭載時に、前記主表面と接触しかつ前記電子部品と対向する方向に折り曲げられていることを特徴とする電子部品。 The electronic component according to claim 1,
An end part of the auxiliary conductor in the extending direction is bent in a direction in contact with the main surface and facing the electronic part when the electronic part is mounted. 請求項１に記載の電子部品において、
前記補助導体部の延在方向の端部は、前記電子部品の搭載時に、前記主表面と接触しかつ前記電子部品と非対向な方向に折り曲げられていることを特徴とする電子部品。 The electronic component according to claim 1,
An end part of the auxiliary conductor portion in the extending direction is bent in a direction in contact with the main surface and not facing the electronic part when the electronic part is mounted. 請求項１ないし４のいずれか一項に記載の電子部品において、
前記補助導体部には、前記電子部品の搭載時に、前記主表面から前記電子部品方向に延びて形成されたスリットが設けられていることを特徴とする電子部品。 The electronic component according to any one of claims 1 to 4,
The electronic component according to claim 1, wherein the auxiliary conductor portion is provided with a slit formed so as to extend from the main surface toward the electronic component when the electronic component is mounted. 電子部品搭載用の基板と、該電子部品搭載用の基板の主表面に搭載された電子部品とを具える半導体装置であって、
前記電子部品は、
前記基板の主表面上に形成された導体部と電気的に接続される突起状導体部と、
前記電子部品のうち該突起状導体部が形成された面とは異なる面から前記基板の主表面に向かって延在するとともに、該延在方向に有する長さは、前記電子部品の搭載時に、前記主表面と接触可能な長さである補助導体部と
を具えていることを特徴とする半導体装置。 A semiconductor device comprising an electronic component mounting substrate and an electronic component mounted on the main surface of the electronic component mounting substrate,
The electronic component is
A protruding conductor portion electrically connected to a conductor portion formed on the main surface of the substrate;
While extending from the surface of the electronic component different from the surface on which the protruding conductor portion is formed toward the main surface of the substrate, the length in the extending direction is determined when the electronic component is mounted. A semiconductor device comprising an auxiliary conductor portion having a length capable of contacting the main surface. 請求項６に記載の半導体装置において、
前記補助導体部上に、前記補助導電部よりも熱放射性が高い絶縁部が形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 6.
An insulating part having higher heat radiation than the auxiliary conductive part is formed on the auxiliary conductor part. 請求項７に記載の半導体装置において、
前記絶縁部は、前記補助導体部を覆い、かつ前記主表面上にわたって形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 7,
The semiconductor device is characterized in that the insulating portion covers the auxiliary conductor portion and is formed over the main surface. 請求項７または８に記載の半導体装置において、
前記絶縁部は、セラミックスを含有していることを特徴とする半導体装置。 The semiconductor device according to claim 7 or 8,
The semiconductor device, wherein the insulating part contains ceramics. 請求項９に記載の半導体装置において、
前記セラミックスは、Ａｌ2Ｏ3を主成分として含有していることを特徴とする電子部品を搭載した半導体装置。 The semiconductor device according to claim 9.
A semiconductor device having an electronic component mounted thereon, wherein the ceramic contains Al 2 O 3 as a main component. 請求項６ないし１０のいずれか一項に記載の半導体装置において、
前記補助導体部の延在方向に有する長さは、前記主表面を突き抜ける長さとされていることを特徴とする電子部品を搭載した半導体装置。 The semiconductor device according to any one of claims 6 to 10,
A length of the auxiliary conductor portion extending in the extending direction is a length penetrating the main surface. A semiconductor device having an electronic component mounted thereon. 請求項６ないし１０のいずれか一項に記載の半導体装置において、
前記補助導体部の延在方向の端部は、前記主表面と接触しかつ電子部品と対向する方向に折り曲げられていることを特徴とする電子部品を搭載した半導体装置。 The semiconductor device according to any one of claims 6 to 10,
An end portion of the auxiliary conductor portion in the extending direction is bent in a direction in contact with the main surface and facing the electronic component. 請求項６ないし１０のいずれか一項に記載の半導体装置において、
前記補助導体部の延在方向の端部は、前記主表面と接触しかつ電子部品と非対向な方向に折り曲げられていることを特徴とする半導体装置。 The semiconductor device according to any one of claims 6 to 10,
An end portion of the auxiliary conductor portion in the extending direction is bent in a direction contacting the main surface and not facing the electronic component. 請求項６ないし１３のいずれか一項に記載の半導体装置において、
前記補助導体部には、前記主表面から前記電子部品方向に延びて形成されたスリットが設けられていることを特徴とする半導体装置。 The semiconductor device according to any one of claims 6 to 13,
A semiconductor device, wherein the auxiliary conductor portion is provided with a slit formed extending from the main surface in the direction of the electronic component. 請求項６ないし１４のいずれか一項に記載の半導体装置において、
前記電子部品は、回路素子を有する半導体チップであることを特徴とする半導体装置。 The semiconductor device according to any one of claims 6 to 14,
The electronic device is a semiconductor chip having a circuit element. 請求項６ないし１４のいずれか一項に記載の半導体装置において、
前記電子部品は、回路素子を有する半導体チップを含み、該半導体チップの外形寸法と同一の外形寸法を有する半導体パッケージであることを特徴とする半導体装置。
The semiconductor device according to any one of claims 6 to 14,
The electronic device includes a semiconductor chip having a circuit element, and is a semiconductor package having the same outer dimension as the outer dimension of the semiconductor chip.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231296A (en) * 2008-03-19 2009-10-08 Powertech Technology Inc Heat radiation type multiple hole semiconductor package
WO2021081477A1 (en) * 2019-10-24 2021-04-29 Texas Instruments Incorporated Metal-covered chip scale packages

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231296A (en) * 2008-03-19 2009-10-08 Powertech Technology Inc Heat radiation type multiple hole semiconductor package
JP4647673B2 (en) * 2008-03-19 2011-03-09 力成科技股▲分▼有限公司 Heat dissipation type multi-hole semiconductor package
WO2021081477A1 (en) * 2019-10-24 2021-04-29 Texas Instruments Incorporated Metal-covered chip scale packages

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