JP2006239953A - Recording device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a recording device which can transmit a recording waveform data signal to the driving circuit of a recording head from a main body main circuit by a smaller number of signal wires than the number of kinds of recording waveform. <P>SOLUTION: The recording waveform data signal DATA is serially transmitted to a head driver 21 from the main body main circuit. The head driver 21 of the recording head 1 has a first serial-parallel conversion circuit 35, a second serial-parallel conversion circuit 36, and a switching circuit 37. In this case, the first serial-parallel conversion circuit 35 converts each state of the recording waveform data signal DATA corresponding to the rising edge of each clock pulse in a clock signal CLK2 into a parallel signal. The second serial-parallel conversion signal 36 converts each state of the recording waveform data signal DATA corresponding to the falling edge of each clock pulse into a parallel signal. The switching circuit 37 switches both parallel signals from the rising edge and the falling edge of a latch signal LAT2, and outputs as a plurality of kinds of the recording waveform signals FIRE 01-06. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a recording apparatus such as an ink jet recording apparatus.

  Conventionally, as a recording apparatus, an ink jet recording apparatus that performs recording by ejecting ink droplets toward the recording medium while moving an ink jet head mounted on a carriage at a predetermined interval along the recording medium It has been known.

  In such an ink jet recording apparatus, an ink jet head (hereinafter referred to as a recording head) is provided with a drive circuit to which a recording data signal and various control signals are input from a main body circuit (on the apparatus main body side). A recording head having a plurality of channels of ink ejection nozzles is known (see, for example, Patent Document 1).

  By the way, in the conventional recording head as described above, a recording waveform signal is input to a driving circuit to drive the head, but a plurality of recording waveforms for ejecting a plurality of types of ink droplets for gradation recording. In some cases, it may be necessary to change the recording waveform signal in units of blocks or columns of a certain nozzle in order to prepare the power supply, suppress the power peak, or avoid crosstalk. Further, in the case of color recording, the characteristics differ depending on the ink, and there is a demand to use a recording waveform optimal for the characteristics. In these cases, the number of types of recording waveforms increases. As the number of types of recording waveforms increases, the number of signal lines for inputting recording waveform signals to the drive circuit increases accordingly.

  When the number of signal lines increases in this way, not only becomes complicated, but also when a flexible flat cable is used for signal transmission from the main circuit on the apparatus main body side to the drive circuit of the recording head, the flexible flat cable is used. The width of the cable is widened, the winding is complicated, and it is disadvantageous in terms of cost and maintenance.

Therefore, in the technique described in Patent Document 1, by mounting the waveform generation circuit on the recording head, the signal line for inputting the recording waveform signal from the main body circuit on the apparatus main body side to the driving circuit on the recording head side is provided. Propose to reduce the number. That is, data necessary for generating a recording waveform signal such as a pulse width is serially transmitted in advance to a waveform generation circuit mounted on a recording head, and recording waveform signals are output from the waveform generation circuit when recording starts based on the data. It is doing so.
Japanese Unexamined Patent Publication No. 2000-158643 (paragraphs 0053 to 0056 and FIG. 4)

  In the technique described in Patent Document 1, although the number of signal lines for inputting a recording waveform from the main body circuit on the apparatus main body side to the drive circuit on the recording head side is reduced, an additional waveform generation circuit is required. A waveform generation circuit must be provided for each type of recording waveform, and the weight of the recording head also increases.

  According to the present invention, recording waveform data is transferred from a main body circuit (on the apparatus main body side) to a driving circuit (of the recording head) with fewer signal lines than the number of types of recording waveforms without mounting a waveform generation circuit on the recording head. Provided is a recording apparatus capable of transmitting a signal.

  According to the first aspect of the present invention, there is provided a recording head having a plurality of actuators for performing dot recording, a driving circuit for outputting a driving pulse to the plurality of actuators of the recording head, and a recording waveform data signal for the driving circuit. And a main body circuit for transmitting a drive signal including selection data for each actuator, wherein the drive circuit generates a plurality of types of recording waveform signals based on the recording waveform data signal, In a recording apparatus having a selection means for selecting a predetermined recording waveform signal based on the selection data from among various types of recording waveform signals, and outputting the recording waveform signal selected by the selection means The drive circuit transmits the recording waveform data signal serially transmitted from the main body main circuit and is transmitted from the main body main circuit. A serial-parallel conversion circuit that converts each state corresponding to the rising edge and falling edge of each clock pulse in the clock signal to a parallel signal, and the rising edge and rising edge of the latch signal transmitted from the main circuit of the main body. And a switching circuit for switching both parallel signals based on the falling edge and outputting the plurality of types of recording waveform signals.

  According to the first aspect of the present invention, the recording waveform data signal is serially transmitted from the main body main circuit, and this recording waveform data signal is transmitted from the main body main circuit in the serial-parallel conversion circuit (of the driving circuit). Each state corresponding to the rising edge and falling edge of each clock pulse in the signal is converted into a parallel signal. Then, based on the rising edge and the falling edge of the latch signal transmitted from the main body main circuit, the parallel signals are switched by the switching circuit and outputted as a plurality of types of recording waveform signals. In other words, the invention of claim 1 uses not only the rising edge of the clock pulse but also the falling edge of the clock pulse to change the recording waveform signal rather than the time for serially transmitting a group of recording waveform data signals. Even when the time (that is, the time between the displacement points of the recording waveform signal) is short, the number of signal lines is less than the number of types of recording waveforms (on the main unit side) without mounting the waveform generation circuit on the recording head. The recording waveform data signal can be transmitted from the main body main circuit to the driving circuit (of the recording head).

  According to a second aspect of the present invention, in the recording apparatus according to the first aspect, the serial-parallel conversion circuit converts each state of the recording waveform data signal corresponding to a rising edge of each clock pulse into a parallel signal. And a second serial-parallel conversion circuit for converting each state of the recording waveform data signal corresponding to the falling edge of each clock pulse into a parallel signal.

  According to the second aspect of the present invention, the recording waveform data signal serially transmitted from the main body main circuit is supplied to the rising edge of each clock pulse in the clock signal transmitted from the main body main circuit by the first serial-parallel conversion circuit. Each state of the recording waveform data signal corresponding to is converted into a parallel signal. On the other hand, each state of the recording waveform data signal corresponding to the falling edge of each clock pulse is converted into a parallel signal by the second serial-parallel conversion circuit. The plurality of types of recording waveform signals are generated using these both parallel signals.

  According to a third aspect of the present invention, in the recording apparatus according to the first or second aspect, the latch signal is output at a predetermined period sandwiching a group of a predetermined number of clock pulses, and each state of the converted parallel signal is: The recording waveform data signal is serially transmitted corresponding to the next group of clock pulses and is changed based on each state.

  According to a third aspect of the present invention, the latch signal is output at a predetermined period with a fixed number of clock pulse groups interposed therebetween, and the plurality of parallel recording waveform signals are output based on the latch signal. Further, each state of the plurality of parallel recording waveform signals is changed on the basis of each state of the recording waveform data signal serially transmitted corresponding to the next group of clock pulses. In addition, the parallel signal is changed.

  According to a fourth aspect of the present invention, in the recording apparatus according to the third aspect, each recording waveform signal includes one or a plurality of drive pulses, and the serially transmitted recording waveform data signal is a drive of each recording waveform signal. The pulse state is serially included for each group of the clock pulses.

  According to the invention of claim 4, since the recording waveform data signal transmitted serially includes the state of the driving pulse of each recording waveform signal serially for each group of the clock pulses, By parallel conversion, a plurality of types of recording waveform signals including one or a plurality of drive pulses are generated and output at predetermined intervals.

  According to a fifth aspect of the present invention, in the recording apparatus according to any one of the first to fourth aspects, the recording head and the drive circuit are mounted on a carriage that is movable along a recording medium, and the main body main circuit is The drive signal and the recording waveform data signal are provided in a device main body that accommodates a carriage, and are transmitted to the drive circuit via a flexible cable provided between the device main body and the carriage.

  According to the invention of claim 5, the number of signal lines for the recording waveform data signal transmitted via the flexible cable can be reduced.

  According to a sixth aspect of the present invention, in the recording apparatus according to any one of the first to fifth aspects, the actuator of the recording head has a volume of an ink chamber that stores ink based on a driving pulse in the selected recording waveform. It is characterized in that the ink droplets are ejected by increasing / decreasing.

  According to the sixth aspect of the present invention, it is possible to finely control the drive for each actuator, and the amount of ejected ink droplets can be easily controlled.

  As described above, the present invention converts each state corresponding to each clock pulse in the clock signal transmitted from the main body circuit of the recording waveform data signal serially transmitted from the main body main circuit to serial-parallel conversion of the drive circuit. Since a plurality of types of recording waveform signals are generated by changing in parallel in the circuit, the recording waveform data signal can be transmitted to the drive circuit with a smaller number of signal lines than the number of types of recording waveforms. In addition, each state corresponding to the rising edge and falling edge of each clock pulse in each clock signal of the recording waveform data signal is converted into a parallel signal by the serial-parallel conversion circuit, and these parallel signals are converted by the switching circuit. Since the signals are switched and output as multiple types of recording waveform signals, even when the time to change the recording waveform (that is, the time between the displacement points of the recording waveform) is shorter than the group of serial data transmission times can do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an electrical configuration of a control device that controls an ink jet recording apparatus according to an embodiment of the present invention.

  As shown in FIG. 1, a control device 1 (in an ink jet recording apparatus) stores a CPU 11 for processing a recording data signal (print data signal) and controlling the operation of the recording apparatus, and a program executed by the CPU 11. A main body circuit including a ROM 12, a RAM 13 for temporarily storing data during data processing by the CPU 11, a gate array 14 which is a gate circuit LSI, and the like is provided. The CPU 11 includes an operation panel 15 for a user (user) to instruct printing, a motor drive circuit 16 for driving a carriage motor M1 (a motor for reciprocating a carriage (not shown)), and a paper feed motor. A motor drive circuit 17 for driving M2 (a motor for feeding a recording sheet as a recording medium in a predetermined direction), a paper sensor 18 for detecting the leading edge of the recording sheet as a recording medium, and the recording head 1 are mounted. An origin sensor 19 for detecting the origin position of a carriage (not shown) is connected.

  The recording head 1 is driven by a head driver 21 as a drive circuit. The head driver 21 is mounted on the carriage together with the recording head 1. The head driver 21 and the gate array 14 are connected via a harness cable 22 (flexible flat cable), and the head driver 21 is controlled by the gate array 14.

  Although not specifically illustrated, the recording head 1 individually increases or decreases the volume of each ink chamber that accommodates a plurality of inks by driving an actuator including a piezoelectric element, an electrostrictive element, and the like. It is to be jetted. An electrode for driving the actuator is provided for each nozzle, and the electrode is connected to the head driver 21. The head driver 21 generates a drive pulse having a recording waveform suitable for the recording head 1 based on the control of the gate array 14 and applies it to each electrode. An encoder sensor 20 that detects the position of the carriage 2 is connected to the gate array 14.

  The CPU 11 is connected to the ROM 12, RAM 13, and gate array 14 via an address bus 23 and a data bus 24. The CPU 11 generates a recording timing signal and a reset signal according to a program stored in advance in the ROM 12, and transmits each signal to the gate array 14. A recording waveform data signal for generating a recording waveform signal, which will be described later, is stored in the ROM 13 in advance, or transmitted together with the recording data signal from the host computer 26 via the interface 27 and stored in the RAM 12 or the image memory 25. It is output to the gate array 14 during the recording operation.

  The gate array 14 stores image data transmitted from a host computer 26 (personal computer), which is an external device, via an interface 27 in the image memory 25. Further, the gate array 14 generates a data reception interrupt signal based on the data transmitted from the host computer 26 via the interface 27 and transmits the signal to the CPU 11. The gate array 14 generates a clock signal CLK1 and a latch signal LAT1 in accordance with the recording timing signal and the control signal from the encoder sensor 20, and the image data based on the image data stored in the image memory 25. Is transmitted to the head driver 21 in synchronization with the clock signal CLK1. The gate array 14 generates a clock signal CLK2 and a latch signal LAT2 having a period different from that of the clock signal CLK1 and the latch signal LAT1 according to the print timing signal and the control signal from the encoder sensor, and the recording waveform data The signal DATA is transmitted to the head driver 21 in synchronization with the clock signal CLK2. Each signal that connects the gate array 14 and the head driver 21 is transmitted via a harness cable 22 that connects the head driver 21 and the gate array 14.

  Further, as shown in FIG. 2, the head driver 21 includes a first serial-parallel conversion circuit 31 for converting the drive signal SIN0-2 into a parallel signal corresponding to each actuator, and a first latch. Circuit 32, selector 33, driver 34, second and third serial / parallel conversion circuits 35 and 36 for converting the recording waveform data signal into a plurality of types of recording waveform signals, and second and third latches Circuits 38 and 39 are provided. The parallel signal generated in the second and third serial / parallel conversion circuits 35 and 36 is switched based on the rising edge and the falling edge of the latch signal transmitted from the gate array 14, and is sent to the selector 33. On the other hand, a switching circuit 37 for outputting the plurality of types of recording waveform signals is provided.

  When the recording head 1 is, for example, a 64-channel multi-nozzle head provided with 64 ink chambers, the first serial-parallel conversion circuit 31 is composed of a 64-bit length shift register. The serial-parallel conversion circuit 31 receives the drive signal SIN0-2 serially transmitted from the gate array 14 in synchronization with the clock signal CLK1, and the drive signal is a parallel signal according to the rise of the clock pulse of the clock signal. Is converted to By serial-parallel conversion of the drive signal, selection signals (selection data) s1, s2, and s3 are set for each channel. Each drive signal is composed of a 3-bit selection signal, and a combination of the bits selects a plurality of types of recording waveform signals including non-printing.

  The latch circuit 32 is generated by the first serial-parallel conversion circuit 31 (corresponding to each actuator of the recording head 1) according to the rising edge (of the pulse) of the latch signal LAT1 transmitted from the gate array 14. Latches the wrong signal.

  On the other hand, the second and third serial-parallel conversion circuits 35 and 36 provided in parallel are each composed of a 6-bit length shift register corresponding to the number of types of recording waveforms. The serial-parallel conversion circuits 35 and 36 receive the recording waveform data signal DATA serially transmitted from the gate array 14 in synchronization with the clock signal CLK2. Then, the second serial-parallel conversion circuit 35 converts each state of the recording waveform data signal DATA corresponding to the rising edge of the clock pulse of the clock signal CLK2 into a parallel signal FIRE 01A-06A. On the other hand, the second serial-parallel conversion circuit 36 converts each state of the recording waveform data signal DATA corresponding to the falling edge of the clock pulse of the clock signal CLK2 into a parallel signal FIRE 01B-06B.

  The second latch circuit 38 latches the output signal FIRE 01A-06A of the second serial-parallel conversion circuit 35 based on the rising edge of the latch signal LAT2 transmitted from the gate array 14, and the third latch circuit 39 Latches the output signal FIRE 01B-06B of the third serial-to-parallel conversion circuit 36 based on the falling edge of the latch signal LAT2 (transmitted via the inverting circuit 41). Then, the switching circuit 37 inputs the latch signal LAT2 through the delay circuit 40 with a slight delay from both the latch circuits 38 and 39, and based on the rising and falling edges of the latch signal LAT2, The 39 output signals FIRE 01A-06A and FIRE 01B-06B are alternately fetched and output to the 64 selectors 33 provided for each channel as the plurality of types of recording waveform signals FIRE 01-06.

  Each selector 33 is configured to output a plurality of types of recording waveform signals FIRE 01-06 transmitted from the switching circuit 37 based on drive signals (including selection signals s1, s2, and s3) output in parallel from the latch circuit 32, respectively. One of them is selected, and the selected recording waveform signal is output to the driver 34. For example, when six types having different numbers of pulses are prepared, the drive signal includes three selection signals s1, s2, and s3, and one of the recordings is recorded according to the input of the selection signal. A waveform signal is selected. Specifically, when the selection signals s1, s2, and s3 are 0, 0, 0, non-printing is performed, 0, 0, 1 is the recording waveform signal FIRE 01, and 0, 1, 0 is the recording waveform signal FIRE 02. , 1, 0, 0, it is possible to obtain seven gradations including non-printing in units of nozzles, such as selecting the recording waveform signal FIRE 03, respectively.

  Each driver 34 generates a driving pulse having a voltage suitable for the recording head 1 based on the recording waveform signal FIRE 01-06 output from the selector 33, and records it as a driving pulse having the selected recording waveform. Output to the electrode (actuator) of each ink chamber of the head 1.

  If the recording head 1 is not 64 channels, the bit length of the serial-parallel conversion circuit 31 and the number of selectors 33 and drivers 34 may be the same as the number of channels of the recording head 1.

  Next, the processing timing of each signal in the head driver 21 will be described with reference to FIGS. 3 and 4 showing timing charts of various signals transmitted to the head driver 21. FIG.

  The drive signals SIN0-2 are read from the image memory 25 by the gate array 14 and serially transmitted to the head driver 21 via the flexible flat cable 22. The recording waveform data signal DATA, clock signals CLK 1 and CLK 2, and latch signals LAT 1 and LAT 2 are also serially transmitted from the gate array 14 to the head driver 21 via the flexible flat cable 22.

  As shown in FIG. 3, the recording waveform data signal DATA output from the gate array 14 indicates each state from the beginning of each of the six types of recording waveform signals FIRE 01-06, and each of the six clock pulses of the clock signal CLK2. Corresponding to serial. The recording waveform data signal DATA is recorded corresponding to each clock pulse CLK2 sequentially sandwiched between adjacent latch signals LAT2 so that each recording waveform signal FIRE 01-06 includes one or more driving pulses. Each state of the waveform signal FIRE 01-06 is included as a group (1 to 6).

  First, the second serial-parallel conversion circuit 35 first converts each state of the first group of recording waveform data signals DATA corresponding to the rising edge 06A-01A of the clock pulse of the clock signal CLK2 into a parallel corresponding to the type of recording waveform. The first group of recording waveform data signals corresponding to the falling edge 06B-01B of each clock pulse is converted by the third serial-parallel conversion circuit 36 while the signal FIRE 06A-01A (see FIG. 3) is converted. Each state of DATA is converted into another parallel signal FIRE 06B-01B (see FIG. 3) following the parallel signal FIRE 06A-01A.

  For example, in FIG. 4, at the rising edge 06A of the first clock pulse, since the recording waveform data signal DATA is in the “1” level, the recording waveform signal FIRE 06A is set to the “1” level. At the rising edge 05A of the next clock pulse, since the recording waveform data signal is in the “0” level, the recording waveform signal FIRE 05A is also set to “0” level. Similarly, the recording waveform signal FIRE 04A is set to “0” level, the recording waveform signal FIRE 03A is set to “1” level, the recording waveform signal FIRE 02A is set to “0” level, and the recording waveform signal FIRE 01A is set to “0” level. . On the other hand, since the recording waveform data signal is at the “1” level at the falling edge 06B of the first clock pulse, the recording waveform signal FIRE 06B is at the “1” level. Since the recording waveform data signal is at the “0” level at the falling edge 05B of the next clock pulse, the recording waveform signal FIRE 05B is also at the “0” level. Similarly, the recording waveform signal FIRE 04B is set to “1” level, the recording waveform signal FIRE 03B is set to “1” level, the recording waveform signal FIRE 02B is set to “1” level, and the recording waveform signal FIRE 01B is set to “1” level. .

  Then, the second latch circuit 38 develops the parallel signal developed in the second serial-parallel conversion circuit 35 at the rising edge AY when the latch signal changes from the “0” level to the “1” level at the timing T0. FIRE 01A-06A is captured, and the third latch circuit 39 receives the third serial-parallel conversion circuit 36 at the falling edge BY of the latch pulse that changes from the “1” level to the “0” level at the T1 timing. The parallel signal FIRE 01B-06B developed in is taken in. The switching circuit 37 sequentially captures and combines these parallel signals FIRE 01A-06A and parallel signals FIRE 01B-06B, and sets the initial waveform states (voltage levels) of the plurality of types of recording waveform signals FIRE 01-06. Similarly, the state of the recording wave data signal DATA of the second group is the rising edge of the clock pulse in the second serial-parallel conversion circuit 35 and the falling edge of the clock pulse in the third serial-parallel conversion circuit 36. Each is deployed in parallel. Then, the signal developed in the second serial-parallel conversion circuit 35 in the second and third latch circuits 38, 39 is developed in the third serial-parallel conversion circuit 36 at the rising edge of the latch signal LAT2 at timing T2. The signals are taken in at the rising edge of the latch signal LAT2 at timing T3, and further taken into the switching circuit 37 sequentially. As a result, the voltage levels of the recording waveform signal FIRE 01-06 set at the timings T0 and T1 as described above are switched according to the contents of the second group of recording waveform data signals DATA. For example, the recording waveform signal FIRE 01 raised at the timing T1 is switched to the “0” level at the timing T2.

  Further, at timings T3 to T11, each voltage level of the recording waveform signal FIRE 01-06 is switched according to the contents of the recording waveform data signals DATA of the third group, the fourth group, the fifth group, and the sixth group. As a result, the recording waveform signal FIRE 01-06 is formed as a recording waveform including one or a plurality of drive pulses, and is input to each selector 33. Therefore, by transmitting the recording waveform data signal using not only the rising edge of the clock pulse of the clock signal but also the falling edge, the recording waveform is changed from the time X1 for serially transmitting a group of recording waveform data signals. Even when the time X2 (that is, the time between the displacement points of the recording waveform) is short, the recording waveform data signal can be transmitted to the head driver 21.

  In each selector 33, a plurality of signals input from the switching circuit 37 by parallel transmission based on drive signals (including selection data s0-0, s0-1, s0-2) input from the latch circuit 32, respectively. One of the types of recording waveform signals FIRE 01-06 is selected, and the selected recording waveform signal is output to the driver 34. Then, a drive pulse having a selected recording waveform is output from the driver 34 to the recording head 1 for ink ejection of each of a plurality of ejection nozzles (not shown), and recording (printing) is performed.

  As long as the recording conditions do not change, the first to sixth recording waveform data signals DATA for generating the recording waveform signal FIRE 01-06 are repeatedly read out by the gate array 14 and the second and third serial data The parallel conversion circuits 35 and 36 and the switching circuit 37 repeatedly output the recording waveform signal FIRE 01-06. The recording apparatus of the embodiment is driven using the length of the recording waveform signal FIRE 01-06 as a recording period. The period of the latch signal LAT1 input to the first latch circuit 32 only needs to be adapted to the recording period.

  In a color recording inkjet recording apparatus, recording waveform signals for each ink color recording head are set according to the ink characteristics, and recording waveform data signals for all recording heads are serially transmitted to each recording head. A plurality of recording waveform signals are developed in parallel for each head. In this case, the second and third serial-parallel conversion circuits 35 and 36 have the number of bits of the number of recording waveform signals × the number of recording heads. Alternatively, the second and third serial-parallel conversion circuits 35 and 36 may be provided for each recording head, and the recording waveform data signal may be serially transmitted from the gate array 14 for each recording head.

  Further, the recording waveform data signal DATA may be appropriately rewritten and transmitted from the host computer 26 and stored in the RAM 12 or the image memory 25 so that the recording waveform signal FIRE 01-06 is changed according to the recording conditions. it can. For example, when a large number of image data jetted almost simultaneously is transmitted from the host computer 26, in order to avoid a power peak or a crosstalk, a large number of drive pulses are set not to overlap with the image data. The recording waveform data signal DATA is transmitted.

  Furthermore, the recording waveform data signal DATA output from the gate array 14 can be corrected according to environmental conditions such as temperature. In each of the embodiments, the ink jet recording apparatus has been described. However, the present invention is not limited thereto, and can be applied to a recording apparatus using an impact recording head, a thermal recording head, or the like.

  Also, not only recording density gradation control but also history control, that is, impact recording heads select the recording waveform depending on the presence or absence of previous and subsequent recording data in consideration of the vibration remaining in the impact element, and the thermal recording head also generates heat. The present invention can also be applied to selecting a recording waveform depending on the presence or absence of preceding and subsequent recording data in consideration of heat remaining in the element.

1 is a block diagram illustrating an electrical configuration of an ink jet recording apparatus according to an embodiment of the present invention. It is a block diagram showing one embodiment of a head driver. It is a timing chart figure of operation of the head driver concerning the above-mentioned embodiment (Drawing 2). FIG. 4 is an enlarged view showing a part of the timing chart of FIG. 3 in an enlarged manner.

Explanation of symbols

1 Recording head 11 CPU
14 Gate array 21 Head driver (drive circuit)
22 Flexible flat cable 33 Selector (selection means)
35 Second serial-parallel conversion circuit 36 Third serial-parallel conversion circuit 37 Switching circuit

Claims (6)

A recording head having a plurality of actuators that perform dot recording, a driving circuit that outputs a driving pulse to the plurality of actuators of the recording head, a recording waveform data signal for each of the driving circuits, and each actuator A main circuit for transmitting a drive signal including selection data, and the drive circuit generates a plurality of types of recording waveform signals based on the recording waveform data signal, and includes a plurality of types of recording waveform signals. In the recording apparatus having a selection means for selecting a predetermined recording waveform signal based on the selection data, and configured to output the recording waveform signal selected by the selection means,
The drive circuit is
Each state corresponding to the rising and falling edges of each clock pulse in the clock signal transmitted from the main circuit of the recording waveform data signal serially transmitted from the main circuit is converted into a parallel signal. Serial-parallel conversion circuit
And a switching circuit that switches both parallel signals based on rising and falling edges of a latch signal transmitted from the main circuit of the main body and outputs the signals as the plurality of types of recording waveform signals. The serial-parallel conversion circuit is:
A first serial-parallel conversion circuit that converts each state of the recording waveform data signal corresponding to the rising edge of each clock pulse into a parallel signal;
The recording apparatus according to claim 1, further comprising: a second serial-parallel conversion circuit that converts each state of the recording waveform data signal corresponding to a falling edge of each clock pulse into a parallel signal. The latch signal is output at a predetermined cycle across a group of a fixed number of clock pulses,
3. Each state of the converted parallel signal is changed based on each state of the recording waveform data signal serially transmitted corresponding to a group of next clock pulses. Recording device. Each recording waveform signal includes one or a plurality of drive pulses,
4. The recording apparatus according to claim 3, wherein the serially transmitted recording waveform data signal serially includes a drive pulse state of each recording waveform signal for each group of clock pulses. The recording head and the drive circuit are mounted on a carriage movable along the recording medium,
The main body main circuit is provided in an apparatus main body that accommodates the carriage, and the drive signal and the recording waveform data signal are transmitted to the drive circuit via a flexible cable provided between the apparatus main body and the carriage. The recording apparatus according to claim 1, wherein the recording apparatus is a recording apparatus. The actuator of the recording head is configured to eject ink droplets by increasing or decreasing the volume of an ink chamber containing ink based on a driving pulse in the selected recording waveform. The recording apparatus according to any one of 5.

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