JP2006238138A - Imaging apparatus and imaging method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus capable of preventing the generation of black crushing and capable of inserting an inverting amplifier into a signal processing circuit. <P>SOLUTION: The imaging apparatus is provided with: an imaging part 1 in which a plurality of unit cells for outputting reset voltage corresponding to the output voltage of a charge detection part 117 and lead voltage corresponding to the output voltage of the charge detection part 117 corresponding to the quantity of received light during initialization are arrayed; a signal processing circuit 120 (inverting amplifier 125, etc.) to output luminance information indicating a difference between the reset voltage and the lead voltage from a third signal output line 104; and a high luminance judgment circuit 130 comprising a bypass transistor 131, etc. for deciding whether incident light on a light receiving element 111 is high luminance or not by judging whether the lead voltage is voltage in a prescribed range or not and a clip transistor 134 to output luminance information indicating that the incident light is high luminance to the third signal output line 104 when decided that the incident light is high luminance. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an imaging device in which unit cells for photoelectrically converting incident light are arranged one-dimensionally or two-dimensionally on a semiconductor substrate, and in particular, prevents a phenomenon in which an image is crushed when intense light is incident. Regarding technology.

  In recent years, imaging devices using imaging devices such as home video cameras and digital still cameras have become widespread. Some of these imaging devices include an amplification type image sensor as an imaging device. The amplification type image sensor has excellent features such as low noise, but has a problem that the image is blacked out when strong light is incident. This is a phenomenon in which the charge overflowing from the light receiving element due to strong light is accumulated in the detection capacitor, so that the amount of charge that can be accumulated is reduced, and an image that is originally white becomes black.

  Therefore, conventionally, various techniques for avoiding such a blackout phenomenon have been proposed (for example, see Patent Document 1).

In Patent Document 1, as a technique for avoiding a blackout phenomenon, in a MOS image sensor which is an amplification type image sensor, when a read voltage is a voltage within a predetermined range for each unit cell, A MOS image sensor comprising output means for outputting luminance information indicating the difference between the two, and outputting luminance information indicating high luminance when the read voltage is not in a predetermined range is disclosed.
JP 2004-31785 A

  However, the circuit configuration of Patent Document 1 has a problem that an S / N ratio cannot be improved by inserting an amplifier between the sampling transistor and the line select transistor in the signal processing circuit.

  In general, by inserting an amplifier between the sampling transistor and the line select transistor in the signal processing circuit, the signal of the unit cell is amplified, the noise generated in the signal processing circuit is not amplified, and the amplified noise is in the unit cell. Since only noise is generated, the S / N ratio of the signal output from the imaging device can be improved. Here, when an amplifier is inserted in an imaging apparatus using only NMOS, it is difficult to configure a normal amplifier from the viewpoint of dynamic range, and an inverter-type inverting amplifier is also used from the viewpoint of ease of circuit configuration. It is advantageous to use.

  However, in the circuit of Patent Document 1, when an inverting amplifier is inserted between the sampling transistor and the line select transistor, strong light is incident on the source voltage of the bypass transistor connected to the input / output terminal of the inverting amplifier. When it does, it becomes higher than when it is not so, the bypass transistor cannot be made conductive, and it becomes impossible to output luminance information indicating high luminance.

  Therefore, the present invention can reliably solve the problem that the image is blackened when strong light is incident, and an inverting amplifier is inserted between the sampling transistor and the line select transistor in the signal processing circuit. It is a first object of the present invention to provide an imaging apparatus and an imaging method that can be performed.

  Note that by adding a circuit that prevents the blackout phenomenon to the imaging device, noise between the signal lines due to capacitive coupling between the signal lines in the circuit and other conductive regions becomes a problem. In order to reduce the capacitive coupling between the signal line and the other conductive region, a method of providing a two-layer insulating film between the signal line and the other conductive region has been proposed (for example, Patent Document 2).

  However, in order to increase the intensity of light incident on the unit cell, it is necessary to shorten the distance from the light incident surface to the photoelectric conversion element. Since the insulating film is provided between the conductive regions, the distance from the light incident surface to the photoelectric conversion element becomes long, and there is a problem that the sensitivity is deteriorated.

Accordingly, the present invention provides an imaging device including a blackout prevention circuit that reduces noise from the other conductive regions with respect to the signal lines without providing an insulating film between the signal lines and the other conductive regions. The purpose of 2.
Japanese Patent Laid-Open No. 11-274446

  In order to achieve the first object, an imaging apparatus according to the present invention is an imaging apparatus that outputs luminance information according to the amount of received light, and includes a reset voltage corresponding to an output voltage of a photoelectric conversion unit at initialization. And imaging means in which a plurality of unit cells that output a read voltage corresponding to the output voltage of the photoelectric conversion unit corresponding to the amount of received light are arranged one-dimensionally or two-dimensionally, and the reset voltage and the read voltage Signal output means for outputting luminance information indicating the difference from the signal output line, and whether or not the incident light to the imaging means has high brightness by determining whether or not the read voltage is a voltage within a predetermined range. And a determination output that outputs luminance information indicating that the incident light has high luminance to the signal output line when the determination unit determines that the incident light has high luminance. With high brightness Characterized in that it comprises a constant means. As a result, the high-intensity determination means uses the lead voltage as an input and the signal output line as an output, so that it can be connected in parallel with the signal output means, and the blackout phenomenon can be prevented and the signal output can be prevented. It is also possible to insert an inverting amplifier between the sampling transistor and the line select transistor constituting the means.

  Here, the determination unit includes a bypass transistor that is non-conductive if the read voltage is within a predetermined range, and that is conductive if the read voltage is not within the predetermined range, and a determination capacitor that holds in advance the charge discharged by the bypass transistor. A determination amplifier circuit that amplifies the voltage of the determination capacitor, and the determination output unit includes a clip transistor that is non-conductive if the output of the determination amplifier circuit is within a predetermined range, and that is conductive if the output is not within the predetermined range. It is good also as a structure to have.

  At this time, the bypass transistor and the clip transistor are NMOS transistors, and the bypass transistor is non-conductive when the read voltage is higher than a potential indicating the potential of the bypass transistor, and the read voltage is a potential of the bypass transistor. Those that conduct when the potential is less than or equal to are preferred. The gate of the bypass transistor is supplied with a constant voltage, and the drain of the clip transistor has a saturation output signal that is different from the reset voltage in the vertical signal line from which luminance information is output from the signal output means. It is desirable to supply a constant voltage as described above.

  In addition, the determination unit further transmits an initialization unit that initializes the determination capacitor by charging, and transmits a voltage of the determination capacitor to the determination amplifier circuit, or sets an input of the determination amplifier circuit to a constant potential. Amplifier switch means for fixing and suppressing current consumption in the determination amplifier circuit, and clip switch means for transmitting the output of the determination amplifier circuit to the clip transistor, or for making the clip transistor non-conductive Also good. At this time, it is preferable that the initialization unit, the amplifier switch unit, and the clip switch unit are transistors, and the determination unit is driven by at least one pulse.

  In order to achieve the second object, in the imaging apparatus according to the present invention, in the imaging apparatus, the determination unit is disposed adjacent to the unit cell, and the determination output unit includes the signal output. It is arranged adjacent to the line. Thus, since the determination output unit is connected adjacent to the signal output line, the problem that the wiring length of the signal output line becomes long due to the provision of the high luminance determination means is avoided.

  Here, the determination output unit may be arranged such that a distance from the signal output line is shorter than a distance from the determination unit, and the signal output unit includes the reset voltage and the lead. A signal amplifying circuit for amplifying a voltage; and a noise canceling circuit for canceling noise included in the reset voltage and the read voltage. The signal amplifying circuit and the noise canceling circuit include the determination unit and the determination output unit. It may be arranged so as to be located between.

  Further, the determination output unit is configured by an NMOS transistor, and a control signal line for transmitting a signal indicating a determination result by the determination unit is connected to a gate of the NMOS transistor configuring the determination output unit, and the control signal The line may be wired so as to pass through a circuit block including the signal amplification circuit and the noise cancellation circuit, and the determination output unit includes a clip transistor connected to the signal output line, A clamp transistor that supplies a clamp voltage and a sampling capacitor that holds luminance information indicating the difference are connected to the signal output line, and the clip transistor, the clamp transistor, and the sampling capacitor are arranged adjacent to each other. May be.

  Note that the present invention can be realized not only as an imaging apparatus having the above-described configuration, but also as an imaging method that suppresses a blackout phenomenon that may occur when incident light on the imaging apparatus has high luminance. It can also be realized.

  According to the image pickup apparatus of the present invention, not only the problem of blackout of the image is solved, but also an inverting amplifier can be inserted between the sampling transistor for reading the signal from the image pickup unit and the line select transistor. In addition, an imaging apparatus capable of providing a normal image with high luminance and providing an image with a high S / N ratio is realized.

  Further, according to the imaging apparatus according to the present invention, the influence (noise) between the signal lines caused by adding the blackout prevention circuit to the imaging apparatus can be reduced by devising the circuit arrangement. There is no need to provide an insulating film between the conductive regions. Therefore, the distance from the light incident surface to the photoelectric conversion element can be shortened, the intensity of light incident on the unit cell is increased, and a highly sensitive imaging device is realized.

  Hereinafter, embodiments of an imaging apparatus according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating an overall configuration of an imaging apparatus according to an embodiment of the present invention. This imaging device is an NMOS image sensor having an inverting amplifier for improving the S / N ratio in a signal processing circuit and having a function of avoiding a blackout phenomenon, and includes an imaging unit 1, a load circuit 2, a row selection encoder 3, It comprises a column selection encoder 4, a signal processing unit 5, and an output circuit 6.

  The imaging unit 1 is an imaging region in which unit cells are arranged one-dimensionally or two-dimensionally. Here, an example of 9 pixels arranged in 3 × 3 two dimensions is shown, but the actual total number of pixels is several thousand in one dimension and hundreds of thousands to several million in two dimensions. Degree.

  The load circuit 2 is a circuit in which one identical circuit is connected for each vertical column, and a load is applied to the pixels of the imaging unit 1 in units of columns in order to read out the output voltage.

  The row selection encoder 3 includes three control lines “RESET”, “READ”, and “LSEL” for each horizontal row, and resets (initializes) the pixels of the imaging unit 1 in units of rows. Read (read) and line select (row selection) are controlled.

The column selection encoder 4 includes control lines and sequentially selects the columns of the imaging unit 1.
The signal processing unit 5 is connected to one identical circuit for each vertical column, and processes the column unit output from the imaging unit 1 and sequentially outputs it.

  The output circuit 6 performs conversion necessary for outputting to the outside to the output of the signal processing unit 5 and outputs the result.

  FIG. 2 is a detailed circuit diagram focusing on one pixel in the imaging apparatus shown in FIG. Here, a load circuit 100, a pixel circuit 110, a signal processing circuit 120, and a high luminance determination circuit 130 are shown. Each of these circuits is composed of an NMOS transistor.

  The load circuit 100 corresponds to one circuit in the load circuit 2 of FIG. 1 and includes a load transistor 101 connected between the first signal output line 102 and GND. A load voltage (LG) is supplied to the gate of the load transistor 101.

  The pixel circuit 110 corresponds to one unit cell in the imaging unit 1 in FIG. 1, and the reset signal obtained by amplifying the voltage at the time of initialization and the read voltage obtained by amplifying the voltage at the time of reading are sent to the first signal output line 102. A light receiving element 111 such as a photodiode that photoelectrically converts incident light and outputs a charge, a capacitor that accumulates the charge generated by the light receiving element 111, and outputs the accumulated charge as a voltage signal ( A floating diffusion) 112, a reset transistor 113 that resets the voltage indicated by the capacitor 112 to an initial voltage (here, VDD), a read transistor 114 that supplies the charge 112 output to the capacitor 112, Amplifying transistor 11 that outputs a voltage that changes following the voltage indicated by capacitor 112 When, and a line select transistor 116 that outputs an output of the amplifier transistor 115 to the first signal output line 102 from the row selecting encoder 3 when receiving the line select signal. In order to facilitate the following description, a portion indicating a voltage corresponding to the electric charge accumulated in the capacitor 112, that is, connection of the capacitor 112, the reset transistor 113, the read transistor 114, and the amplifying transistor 115 is connected. The point is particularly referred to as a charge detection unit 117.

  The signal processing circuit 120 corresponds to one circuit for one vertical column in the signal processing unit 5 of FIG. 1, and when the read voltage in the first signal output line 102 is a voltage within a predetermined range, a unit cell is used. Outputs luminance information that indicates the difference between the reset voltage and the read voltage that is output, and outputs luminance information that indicates high luminance (that is, strong light is incident on the light receiving element) when the read voltage is not within the predetermined range. It is characterized by doing.

  This signal processing circuit 120 determines whether or not the light receiving element is at a high luminance level (hereinafter referred to as “high luminance” when strong light is incident on the light receiving element; A high luminance determination circuit 130 that outputs luminance information indicating that at the time of high luminance to the third signal output line 104, a second signal output line 103, and a third signal output line 104. , The sampling transistor 121 and the clamp capacitor 122 connected in series, the sampling capacitor 123 connected between the third signal output line 104 and GND, the third signal output line 104 and the reference voltage (reset reference). Voltage transistor), an inverting amplifier 125 that amplifies the voltage of the first signal output line 102 and outputs it to the second signal output line 103, and the inverting amplifier 1 5 to determine the reference potential of the reset operating a includes an inverting amplifier reset transistor 126, an inverting amplifier coupling capacitor 127 which transmits only the AC component of the first signal output line 102 to the inverting amplifier 125.

  Note that the sampling transistor 121, the clamp capacitor 122, the sampling capacitor 123, and the clamp transistor 124 are for removing noise included in the signal output from the unit cell, and constitute a noise cancel circuit.

  The high luminance determination circuit 130 is non-conductive when the bypass switch transistor 136 transmits the potential of the first signal output line 102 to the bypass transistor 131 and the read voltage in the first signal output line 102 is within a predetermined range. The bypass transistor 131 that conducts when the read voltage is not in a predetermined range, the determination capacitor 132 that retains the charge discharged by the bypass transistor 131 in advance, and the voltage of the determination capacitor 132 are set to a high potential (here, The determination capacitor initialization transistor 135 charged to (VDD) and the amplifier switch transistor 137 that transmits or cuts off the potential of the determination capacitor 132 to the determination amplifier 133 and fixes the input of the determination amplifier 133 to a low potential (GND in this case). And transmitted through the amplifier switch transistor 137. A decision amplifier 133 that amplifies the voltage of the decision capacitor 132, and a clip switch that transmits or shuts off the output of the decision amplifier 133 to the clip transistor 134 and fixes the gate of the clip transistor 134 at a low potential (GND in this case). A clip transistor that outputs a clip voltage to the third signal output line 104 when the output of the transistor 138 and the determination amplifier 133 transmitted via the clip switch transistor 138 is non-conductive if it is a low potential (GND in this case), and is conductive if it is a high potential. 134.

  Among the circuit elements of the high luminance determination circuit 130, the circuit elements other than the final stage clip transistor 134 are high by determining whether or not the read voltage in the first signal output line 102 is a voltage within a predetermined range. A determination unit that determines whether or not the brightness is present is configured. In addition, when the determination unit determines that the clip transistor 134 at the final stage is at the time of high luminance, the third signal output line displays luminance information indicating high luminance instead of the luminance information at the normal time. A determination output unit that outputs to 104 is configured.

  Here, the pixel circuit 110 receives a reset pulse (initialization signal: RESET), a read pulse (readout pulse: READ), and a line select pulse (row selection signal: LSEL), and the signal processing circuit 120 receives sampling. The pulse (SP), the clamp pulse (CP), and the inverting amplifier reset pulse (AMPCL) are included in the high luminance determination circuit, the determination circuit control pulse 1 (RS1) and its logical inversion signal (RS1B), and the determination circuit. The control pulse 2 (RS2) and its logic inversion signal (RS2B) are supplied at a determined timing, and the transistors corresponding to these control pulses are opened and closed (OFF / ON).

  Further, when the potential of the first signal output line 102 transmitted through the bypass switch transistor 136 indicates the normal potential, the bypass transistor 131 becomes non-conductive at the gate of the bypass transistor 131, and the first signal output line The bias voltage BWBIAS is set such that the bypass transistor 131 becomes conductive when the potential 102 indicates a potential at high luminance. That is, the bypass transistor 131 is non-conductive when the read voltage on the first signal output line 102 is higher than the potential indicating the potential of the bypass transistor 131, and the read voltage on the first signal output line 102 indicates the potential of the bypass transistor 131. Conducts when the potential is lower.

  FIG. 3 is a diagram showing the timing of each control pulse supplied to the imaging apparatus shown in FIG. The imaging apparatus performs an operation of reading a read signal (read voltage) of a unit cell at timings A to D, and determines whether or not the read signal (read voltage) of the unit cell is within a predetermined range at timings E to I. If it is determined, luminance information indicating a difference between the reset voltage and the read voltage is output within a predetermined range, and luminance information indicating high luminance is output if the voltage is not within the predetermined range.

The operation at timings A to I will be described below.
4A to 4D show potentials at timings A to D at normal times, respectively. FIGS. 5A to 5D show potentials at timings A to D at high luminance, respectively. FIG. 6 shows the potential at the timing G at the normal time. FIG. 7 shows the potential at the timing G when the luminance is high.

  At timing A shown in FIG. 3, since the read transistor 114 is OFF and the reset transistor 113 is ON, in the normal state, as shown in FIG. However, at high luminance, as shown in FIG. 5A, the charge generated in the light receiving element 111 exceeds the potential of the read transistor 114 and moves to the charge detection unit 117, and at the same time, the charge detection. The charge of the unit 117 moves to the VDD terminal through the reset transistor 113.

  At the timing B shown in FIG. 3, the reset transistor 113 is turned from ON to OFF, and the charge detection unit 117 is reset to VDD at normal time (FIG. 4B).

  On the other hand, at the time of high brightness, as shown in FIG. 5B, the charge generated in the light receiving element 111 continues to move to the charge detection unit 117 beyond the potential of the read transistor 114, so that the voltage of the charge detection unit 117 is VDD The voltage will be lower. A fluctuation amount at which the voltage of the charge detection unit 117 becomes a voltage lower than VDD is defined as Vb.

  At timing C shown in FIG. 3, the reset transistor 113 remains OFF and the read transistor 114 is ON, so that the charge generated in the light receiving element 111 moves to the charge detection unit 117. At this time, the potential fluctuation of the charge detection unit 117 due to the charge generated in the light receiving element 111 is defined as Vsig.

  At timing D shown in FIG. 3, the reset transistor 113 remains OFF and the read transistor 114 is OFF, so that the charge generated in the light receiving element 111 is read to the charge detection unit 117. As a result, the voltage of the charge detection unit 117 changes, and the voltage after this change is amplified by the amplifying transistor 115, so that the voltage of the first signal output line 102 changes to the read voltage.

  At this time, the voltage fluctuation of the first signal output line 102 due to the read operation is Vsig (FIG. 4D) at normal time and Vsig−Vb at high luminance (FIG. 5D). Thus, since the potential of the charge detection unit 117 is limited by the potential when the reset transistor 113 is OFF, the voltage fluctuation of the first signal output line 102 is reduced by Vb at high luminance. This decrease is a factor causing blackout of the image.

Since the voltage fluctuation of the first signal output line 102 is amplified by the inverting amplifier 125, the voltage of the second signal output line 103 becomes a voltage obtained by inverting and amplifying the voltage of the first signal output line 102. That is, the voltage of the second signal output line 103 is
Normal: Inverting amplifier reset voltage + Av × Vsig (Formula 1)
High brightness: Inverting amplifier reset voltage + Av × (Vsig−Vb) (Formula 2)
It becomes. Here, Av is the amplification factor of the inverting amplifier 125.

Since both ends of the clamp capacitor 122 are held at the inverting amplifier reference voltage and the reset reference voltage, respectively, the voltage of the third signal output line is
Normal time: Reset reference voltage + Av × Ccp / (Ccp + Csp) × Vsig (Formula 3)
High luminance: Reset reference voltage + Av × Ccp / (Ccp + Csp) × (Vsig−Vb) (Formula 4)
It becomes. Here, Ccp is the capacitance value of the clamp capacitor 122, and Csp is the capacitance value of the sampling capacitor 123.

This difference between normal time and high brightness appears as a blackout phenomenon when strong light is incident.
At timing E shown in FIG. 3, since the bypass switch transistor 136 is OFF, the bypass transistor 131 is not turned on, the determination capacitor initialization transistor 135 is turned ON, and the determination capacitor 132 is initialized to VDD. Since the voltage of the decision capacitor 132 is cut off by the amplifier switch transistor 137 and the input of the decision amplifier 133 is fixed to GND, the decision amplifier 133 outputs VDD. The output of the decision amplifier 133 is cut off by the clip switch transistor 138, and the gate of the clip transistor 134 is fixed to GND and turned OFF. Therefore, at this timing E, the high luminance determination circuit 130 performs the initialization operation, but does not affect the potential of the third signal output line 104.

  At the timing F shown in FIG. 3, the amplifier switch transistor 137 is turned on (the potential of the determination capacitor 132 is transmitted to the determination amplifier 133), and the input of the determination amplifier 133 is not fixed to GND. VDD is input to the determination amplifier 133, and the determination amplifier 133 outputs a low potential (here, GND). On the other hand, since the clip switch transistor 138 is cut off, the gate of the clip transistor 134 remains at the initial voltage GND. Further, at this timing F, since the bypass switch transistor 136 is OFF, the high luminance determination operation is not performed.

  If the determination circuit control pulses RS1 and RS2 simultaneously become VDD, the determination capacitor initialization transistor 135 and the amplifier switch transistor 137 compete with each other, and subsequent high-intensity determination operation becomes difficult. A time difference is provided in the rising timing of the determination circuit control pulses RS1 and RS2.

  At the timing G shown in FIG. 3, the bypass switch transistor 136 is turned ON, and the potential of the first signal output line 102 is applied to the bypass transistor 131.

  As shown in FIG. 6, normally, the bypass transistor 131 does not conduct, the voltage of the determination capacitor 132 remains at the initial voltage VDD, and the output of the determination amplifier 133 does not change from a low potential (here, GND). Since the low potential (GND in this case) is applied to the gate of the clip transistor 134, the clip transistor 134 does not conduct and does not affect the potential of the third signal output line.

  On the other hand, as shown in FIG. 7, when the luminance is high, the bypass transistor 131 becomes conductive, and current flows from the determination capacitor 132 to the first signal output line 102 via the bypass transistor 131 and the bypass switch transistor 136. The voltage of the determination capacitor 132 decreases from the initial voltage VDD, and accordingly, the output of the determination amplifier 133 increases, and the clip transistor 134 is turned on. As a result, the potential of the third signal output line 104 changes from the clip voltage to the clip transistor. The potential is obtained by subtracting the threshold voltage of 134. The clip voltage connected to the drain of the clip transistor 134 is set so that the difference between this potential and the reset reference voltage is equal to or higher than the voltage at the time of saturated output (when the light receiving element 111 generates the maximum amount of charge by the incidence of light). If set, a signal equal to or higher than the saturation output can be output as luminance information indicating high luminance.

  As described above, at the timing G shown in FIG. 3, the bypass switch transistor 136 is turned on, and the bypass transistor 131 is normally non-conductive, so that the clip transistor 134 is non-conductive, so that the potential of the third signal output line 104 is increased. Although there is no effect, luminance information indicating high luminance is obtained by turning on the bypass transistor 131 at high luminance, turning on the clip transistor 134, and outputting a potential equal to or higher than the potential at saturation output to the third signal output line. Output.

  At the timing H shown in FIG. 3, the imaging apparatus performs the same operation as the timing F shown in FIG. 3, and contention between the determination capacitor initialization transistor 135 and the amplifier switch transistor 137 is prevented.

  At the timing I shown in FIG. 3, the imaging apparatus performs the same operation as that at the timing E shown in FIG. 3, and a determination capacitor 132, a determination amplifier 133, The clip transistor 134 is initialized.

  As described above, according to the imaging apparatus of the present embodiment, the potential of the first signal output line 102 at the time of reading is a predetermined potential (a potential determined by the gate potential BWBIAS of the bypass transistor 131 and the threshold voltage of the bypass transistor 131). Since the clipping transistor outputs a potential indicating high luminance to the third signal output line 104 in the following case, even when the inverting amplifier 125 is inserted between the sampling transistor 121 and the line select transistor 116, strong light The problem that the image is blackened when the light is incident is surely solved.

  That is, in the imaging apparatus of the present embodiment, the high luminance determination circuit 130 and the inverting amplifier 125 are connected in parallel between the first signal output line 102 and the third signal output line 104. Two circuits (the high luminance determination circuit 130 and the inverting amplifier 125) can coexist, and the blackout phenomenon can be prevented, and an inverting amplifier is inserted between the sampling transistor and the line select transistor of the signal processing circuit. It becomes possible.

  Further, the bias voltage BWBIAS supplied to the bypass transistor 131 can determine the dynamic characteristics of the bypass transistor 131 at a later time and at any time, so that the versatility is high.

  Furthermore, since the luminance information indicating high luminance can be freely set by setting the clip voltage, it is possible to output a voltage that matches the input dynamic range of the subsequent analog circuit. Thereby, the performance of the analog circuit can be utilized efficiently.

  In the present embodiment, the configuration in which the amplifier inserted between the sampling transistor 121 and the line select transistor 116 is an inverting type is shown. However, this amplifier is a non-inverting type or the sampling transistor 121. When no amplifier is inserted between the line select transistor 116 and the line select transistor 116, the amplifier in the high luminance determination circuit 130 can be a non-inverting amplifier.

Next, a circuit arrangement of the imaging device in the present embodiment will be described.
FIG. 8 is a diagram showing an arrangement of the circuit shown in FIG. Here, only the main circuit elements are shown among the circuit elements shown in FIG. As shown in this figure, eight circuit blocks 150 a to 150 h are arranged in the column direction of the imaging unit 1 for each column of the imaging unit 1. The circuit block 150a is a block including the load circuit 100, the circuit block 150b is a block including the line select transistor 116, and the circuit block 150c is a block including a circuit excluding the clip transistor 134 in the high luminance determination circuit 130. The circuit block 150d is a block including the inverting amplifier reset transistor 126 and the inverting amplifier coupling capacitor 127, the circuit block 150e is a block including the sampling transistor 121, the circuit block 150f is a block including the clamp capacitor 122, and the circuit block 150g. Is a block including a clip transistor 134, and a circuit block 150 h is a block including a sampling capacitor 123 and a clamp transistor 124.

  The horizontal width of each of the circuit blocks 150a to 150h is the same as the horizontal width of the unit cell in the imaging unit 1 (for example, about 3 μm). Although the vertical width of each circuit block 150a to 150h varies depending on the circuit elements of each circuit block, the circuit block 150f including the clamp capacitor 122 and the circuit blocks 150a to 150h including the sampling capacitor 123 are extremely difficult to form each capacitor. Has a large vertical width. The vertical width of the entire eight circuit blocks 150a to 150h is, for example, about 1 mm.

  A feature of this circuit arrangement is that the pre-stage circuit (that is, the circuit block 150c) excluding the output stage clip transistor 134 in the high-luminance determination circuit 130 is arranged adjacent to the pixel circuit 110 (that is, the circuit block 150b), and the That is, the output stage clip transistor 134 (that is, the circuit block 150 g) in the determination circuit 130 is disposed adjacent to the third signal output line 104. More specifically, the fifth signal output line 106 (thick black line in FIG. 8) connecting the clip switch transistor 138 of the high luminance determination circuit 130 and the gate of the clip transistor 134 is stretched. It is wired so as to pass through the three circuit blocks 150d to 150f. That is, the clip transistor 134 is arranged such that the distance from the third signal output line 104 is shorter than the distance from the circuit block 150c. Further, the circuit block 150g (the clip transistor 134) and the circuit block 150h (the clamp transistor 124 and the sampling capacitor 123) are disposed adjacent to each other, thereby shortening the wiring length of the third signal output line 104. The significance of such a circuit arrangement will be described in comparison with the normal circuit arrangement shown in FIG.

  In the normal circuit arrangement shown in FIG. 9, all the circuit elements are arranged in one circuit block 160 c without separating the high luminance determination circuit 130. Therefore, the output signal of the high luminance determination circuit 130, that is, the output signal of the clip transistor 134 is the third signal wired so as to straddle the three circuit blocks 150d to 150f as shown by the thick black lines in FIG. It is output to the output line 104. The third signal output line 104 stretched in this way has a parasitic coupling capacitance between the first signal output line 102, the second signal output line 103, and the fourth signal output line 105. Affected (influence of noise generated when the signal changes). The third signal output line 104 is a signal line that outputs the final signal in the signal processing unit 5, and the noise superimposed on the third signal output line 104 is output as it is as noise in the image.

  However, according to the circuit arrangement in the present embodiment shown in FIG. 8, the fifth signal output line 106 extended for a long time in the high-intensity determination circuit 130 is connected to the control signal for connecting the clip switch transistor 138 and the clip transistor 134 ( Logic signal) line, and its amplitude (VDD / GND) margin is large, so that it depends on the parasitic coupling capacitance between the first signal output line 102, the second signal output line 103, and the fourth signal output line 105. Not affected by each signal output line.

  In addition, the influence on the first signal output line 102, the second signal output line 103, and the fourth signal output line 105 from the fifth signal output line 106 in the reverse direction can be influenced by the same parasitic coupling capacitance. However, the signal is output to the fifth signal output line 106 when the luminance is high. At this time, the clip transistor 134 of the high luminance determination circuit 130 is turned on, and the third signal output which is the final signal output line is output. Since luminance information indicating high luminance is output to the line 104 (the signal of the third signal output line 104 is replaced with luminance information indicating high luminance), the influence from the fifth signal output line 106 to other signal output lines Can be ignored. In other words, the voltage of the fifth signal output line 106 does not change during normal time and thus does not affect other signal lines. In high luminance, the voltage may change and affect other signal lines. Since the output of the third signal output line 104 is replaced with luminance information indicating high luminance, the final output image is not affected.

  As described above, any of the first signal output line 102 that transmits the input signal to the high luminance determination circuit 130 and the third signal output line 104 that transmits the output signal of the signal processing circuit 120 depends on the circuit arrangement in this embodiment. Also, the length of the wiring is suppressed from becoming long, and thereby, the influence of noise due to the parasitic coupling capacitance between the signal lines is avoided, and a high-quality image is obtained.

  While the imaging apparatus according to the present invention has been described based on the embodiment, the present invention is not limited to this embodiment. Unless it deviates from the main point of this invention, the various modifications which gave the change within the range which those skilled in the art can consider with respect to this Embodiment are also contained in this invention.

  The image pickup apparatus according to the present invention can be used as an image sensor of an image pickup device, in particular, to eliminate black crushing of an image when strong light is incident and improve image quality. Therefore, various image pickup devices such as home video cameras and digital still cameras can be used. It is useful as an image sensor for an imaging apparatus.

1 is a diagram illustrating an overall configuration of an imaging apparatus according to an embodiment of the present invention. It is a circuit diagram of an imaging device. It is a figure which shows the timing of each control pulse in an imaging device. FIG. 4 is a diagram showing a normal potential at timings A to D in FIG. 3. It is a figure which shows the potential at the time of high-intensity in the timing AD in FIG. FIG. 4 is a diagram illustrating a normal potential at a timing G in FIG. 3. It is a figure which shows the potential at the time of the high brightness | luminance at the timing G in FIG. FIG. 3 is a layout diagram of the circuit shown in FIG. 2. FIG. 9 is another circuit layout diagram for explaining the significance of the circuit layout diagram shown in FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image pick-up part 2 Load circuit 3 Row selection encoder 4 Column selection encoder 5 Signal processing part 6 Output circuit 100 Load circuit 101 Load transistor 102 1st signal output line 103 2nd signal output line 104 3rd signal output line 105 4th signal Output line 106 5th signal output line 110 Pixel circuit 111 Light receiving element 112 Capacitor 113 Reset transistor 114 Read transistor 115 Amplifying transistor 116 Line select transistor 117 Charge detection unit 120 Signal processing circuit 121 Sampling transistor 122 Clamp capacitance 123 Sampling capacitance 124 Clamp transistor 125 Inverting Amplifier 126 Inverting Amplifier Reset Transistor 127 Inverting Amplifier Coupling Capacitor 130 High Brightness Determination Circuit 131 Bypass Transistor 132 Size Capacity 133 determines amplifier 134 clipping transistor 135 determined capacitance initialization transistor 136 bypass switch transistor 137 amplifier switching transistor 138 clips switching transistor 150a~150h circuit block

Claims (15)

An imaging device that outputs luminance information according to the amount of received light,
A plurality of unit cells that output a reset voltage corresponding to the output voltage of the photoelectric conversion unit at the time of initialization and a read voltage corresponding to the output voltage of the photoelectric conversion unit corresponding to the amount of received light are arranged in one or two dimensions. Imaging means,
Signal output means for outputting luminance information indicating a difference between the reset voltage and the read voltage from a signal output line;
A determination unit that determines whether or not the incident light to the imaging unit has high luminance by determining whether or not the lead voltage is a voltage within a predetermined range; and the determination unit determines whether the incident light is high A high-brightness determination unit that includes a determination output unit that outputs luminance information indicating that the incident light has high luminance to the signal output line when it is determined that the incident light has high luminance. apparatus. The determination unit
A bypass transistor that is non-conductive if the read voltage is within a predetermined range, and that is conductive if the read voltage is not within the predetermined range;
A determination capacitor for preliminarily holding charges discharged by the bypass transistor;
A determination amplifier circuit that amplifies the voltage of the determination capacitor;
The determination output unit
The imaging apparatus according to claim 1, further comprising a clip transistor that is non-conductive when the output of the determination amplifier circuit is within a predetermined range, and that is conductive when the output is not within the predetermined range. The imaging device according to claim 2, wherein the bypass transistor and the clip transistor are NMOS transistors. The bypass transistor is non-conductive when the read voltage is higher than a potential indicating the potential of the bypass transistor, and is conductive when the read voltage is equal to or lower than a potential indicating the potential of the bypass transistor. 2. The imaging device according to 2. The imaging apparatus according to claim 2, wherein a constant voltage is supplied to a gate of the bypass transistor. A constant voltage is supplied to a drain of the clip transistor so that a difference from a reset voltage in a vertical signal line from which luminance information is output from the signal output means is equal to or higher than a saturated output signal. The imaging device according to claim 2. The determination unit further includes:
Initialization means for initializing by charging the determination capacity;
An amplifier switch that transmits the voltage of the determination capacitor to the determination amplifier circuit, or suppresses current consumption in the determination amplifier circuit by fixing an input of the determination amplifier circuit to a constant potential;
The imaging apparatus according to claim 2, further comprising: clip switch means that transmits an output of the determination amplification circuit to the clip transistor or makes the clip transistor non-conductive. The imaging apparatus according to claim 7, wherein the initialization unit, the amplifier switch unit, and the clip switch unit are transistors. The imaging device according to claim 2, wherein the determination unit is driven by at least one pulse. The determination unit is disposed adjacent to the unit cell,
The imaging apparatus according to claim 1, wherein the determination output unit is disposed adjacent to the signal output line. The imaging apparatus according to claim 1, wherein the determination output unit is arranged such that a distance from the signal output line is shorter than a distance from the determination unit. The signal output means includes
A signal amplification circuit for amplifying the reset voltage and the read voltage;
A noise cancellation circuit for canceling noise included in the reset voltage and the read voltage;
The imaging apparatus according to claim 1, wherein the signal amplification circuit and the noise cancellation circuit are arranged so as to be positioned between the determination unit and the determination output unit. The determination output unit includes an NMOS transistor,
A control signal line for transmitting a signal indicating a determination result by the determination unit is connected to a gate of the NMOS transistor constituting the determination output unit,
The imaging apparatus according to claim 12, wherein the control signal line is wired so as to pass through a circuit block including the signal amplification circuit and the noise cancellation circuit. The determination output unit includes a clip transistor connected to the signal output line,
A clamp transistor that supplies a clamp voltage and a sampling capacitor that holds luminance information indicating the difference are connected to the signal output line,
The imaging apparatus according to claim 1, wherein the clip transistor, the clamp transistor, and the sampling capacitor are arranged adjacent to each other. An imaging method that suppresses a blackout phenomenon that may occur when light incident on an imaging device has high brightness,
Determining whether the incident light is high brightness,
When it is determined that the incident light has light luminance, the difference is applied to a signal output line from which luminance information indicating a difference between a reset voltage output from an imaging unit having a photoelectric conversion unit and a read voltage is output. Instead of the luminance information to be displayed, luminance information indicating that the incident light has high luminance is output to the signal output line.

Images