JP2006237642A - Semiconductor ic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor IC device removing the layout restrictions of a fuse latch circuit and controlling the increase of its area. <P>SOLUTION: A first layout section 3, in which a fuse (FUSE) is laid out, is equipped with: a fuse area 1 repeatedly arranged by a first repeated pitch P1; a fuse latching circuit area 4, in which a second layout section 4, where the fuse latching circuit (FUSE LAT.) is laid out, is arranged repeatedly at a second repeated pitch P2 smaller than the first repeated pitch P1; and a third layout section 6 arranged within the fuse latch circuit area 4, in which a local address signal line 5 is laid out, is arranged in a space generated by the difference between the first repeated pitch P1 and second repeated pitch P2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a fuse and a fuse latch circuit of a semiconductor memory device, and more particularly to their layout.

  FIG. 16 shows a layout of a conventional fuse and fuse latch circuit. FIG. 16 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 16, conventionally, a fuse (FUSE) and a fuse latch circuit (FUSE LAT.) Corresponding to the fuse one-to-one are respectively set in the chip and adjacent to each other in the fuse area 101 and Arranged in the fuse latch circuit area 102.

  The fuse and fuse latch circuit have basic patterns 103 and 104, respectively. In the fuse area 101 and the fuse latch circuit area 102, a predetermined number of fuses and fuse latch circuits are laid out in the chip by repeating a predetermined number of these basic patterns 103 and 104.

  The repetition pitch P2 of the basic pattern 104 of the conventional fuse latch circuit is equal to the repetition pitch P1 of the basic pattern 103 of the fuse. This is because by making the repeat pitch P2 equal to the repeat pitch P1, it becomes easy to connect the fuse and the fuse latch circuit corresponding to the fuse one-to-one.

  In the fuse latch circuit area 102, there are a basic pattern 104 that can be repeated and a pattern that cannot be repeated in each of the plurality of fuse latch circuits.

  For example, in the case of the fuse latch circuit used in the redundancy circuit shown in FIG. 16, the repeatable basic pattern 104 is a common pattern for a plurality of addresses among the fuse latch circuit patterns, and is repeated. The pattern that cannot be used is the pattern of the local address signal line 105. The local address signal line 105 connects, for example, a global address signal line arranged in the repeating direction of the basic pattern 104 to the fuse latch circuit.

  The input address differs depending on the fuse latch circuit. For this reason, the pattern of the local address signal line 105 is laid out in a layer different in layout from the pattern common to a plurality of addresses. The hierarchy described here is not a physical “up” or “down”. For example, in a semiconductor memory, a plurality of the same layouts are arranged. For this reason, another layout block is often arranged in a certain layout block (cell). Such a structure is called a “hierarchy” in the layout.

  The local address signal lines 105 are on a different layer from the basic pattern 104 of the fuse latch circuit, and are laid out one by one at a place where the basic pattern 104 exists.

  However, in such a layout, the number of local address signal lines 105 increases. For this reason, the parasitic capacitance of the entire address signal line including the global address signal line is increased, and the propagation delay of the address signal becomes conspicuous.

Therefore, as shown in FIG. 17, a plurality of fuse latch circuits corresponding to the same address are arranged next to each other, and the local address signal lines 105 are shared by the plurality of fuse latch circuits, thereby reducing the number of local address signal lines 105. There is also a semiconductor memory device in which the parasitic capacitance of the entire address signal line is reduced (Patent Document 1).
JP-A-11-135754 Japanese Patent Laid-Open No. 11-177039 JP 08-279602 A

  However, in any case, the local address signal line 105 is laid out in a layout hierarchy different from the basic pattern 104 of the fuse latch circuit and in a place where the basic pattern 104 exists. Therefore, it is necessary to provide a space (or region) 106 for arranging the local address signal line 105 in advance in the basic pattern 104 of the fuse latch circuit. This space (or region) 106 cannot be routed with the same wiring layer as that of the local address signal line 105, which is a restriction on the layout.

  Such a layout restriction restricts the degree of freedom of the layout, hinders the reduction of the area of the fuse latch circuit, and leads to an unnecessary increase of the area.

  Conventionally, since the basic pattern 104 of the fuse latch circuit is repeatedly laid out without a gap in the fuse latch circuit area 102, a pattern that does not necessarily need to be repeated at the pitch P2 may be repeated. The pattern that does not necessarily need to be repeated is, for example, a semiconductor substrate on which a fuse latch circuit is formed, or a well contact to a well.

  As described above, since the pattern that does not necessarily need to be repeated at the pitch P2 is repeated more than necessary, the reduction of the area of the fuse latch circuit is hindered and the area is increased.

  The present invention provides a semiconductor integrated circuit device capable of removing restrictions on the layout of a fuse latch circuit and suppressing an increase in the area of the fuse latch circuit.

  The present invention also provides a semiconductor integrated circuit device capable of suppressing the occurrence of blow misses even when the repetition pitch of the basic fuse pattern is reduced to less than the minimum positioning repetition pitch of the fuse blow machine.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a fuse area in which a first layout portion in which fuses are laid out is repeatedly arranged at a first repetition pitch; and a fuse latch circuit corresponding to the fuse Is disposed in the fuse latch circuit area, and is disposed in the fuse latch circuit area, and is disposed in the fuse latch circuit area. At least one of the patterns which are arranged in the space generated by the difference between the first repeat pitch and the second repeat pitch and cannot be repeated in each of the second layout portions and need not be repeated is laid out. And a third layout section.

  In the semiconductor integrated circuit device having the above configuration, the second layout in which the fuse latch circuit corresponding to the fuse is laid out in at least one of the patterns that cannot be repeated or need not be repeated in each fuse latch circuit. Is laid out in a third layout portion different from the portion. As a result, the restrictions on the layout in the second layout section are removed, or a pattern that does not need to be repeated is not repeated more than necessary, and an increase in the area of the fuse latch circuit can be suppressed.

  In the semiconductor integrated circuit device according to the second aspect of the present invention, the layout portion in which the fuse is laid out includes a fuse area in which an irregular repetition pitch is arranged.

  In the semiconductor integrated circuit device having the above configuration, the first layout portion where the fuse is laid out is arranged at an irregular repetition pitch. For example, if the arrangement is arranged at a regular repetition pitch, the minimum positioning of the fuse blow machine is performed. It is possible to reduce the occurrence of blow mistakes when deviating from the repetitive pitch.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device capable of removing restrictions on the layout of the fuse latch circuit and suppressing an increase in the area of the fuse latch circuit.

  Further, according to the present invention, it is possible to provide a semiconductor integrated circuit device capable of suppressing the occurrence of blow miss even when the repetition pitch of the basic pattern of the fuse is reduced to less than the minimum positioning repetition pitch of the fuse blow machine.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
FIG. 1 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 1 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 1, a plurality of fuses (FUSEs) are arranged in the fuse area 1 set in the chip. A basic pattern of fuses is laid out in the first layout section 3, and a predetermined number of fuses are arranged in the chip by repeatedly arranging the first layout section 3 at a first repetition pitch P1.

  A fuse latch circuit area 2 is set adjacent to the fuse area 1 in the chip. In the fuse latch circuit area 2, a plurality of fuse latch circuits (FUSE LAT.) Are arranged. The basic pattern of the fuse latch circuit is laid out in the second layout portion 4, and a predetermined number of fuse latch circuits are arranged in the chip by repeatedly arranging the second layout portion 4 at the second repetition pitch P2. To place. FIG. 2A shows a fuse, and FIG. 2B shows an example of a fuse latch circuit. An outline of one circuit example shown in FIG. 2B will be described. Signals A and B are signals for initializing the fuse latch circuit. For example, the signal A is a signal that becomes “LOW” level for a certain time after power-on, and the signal B is “HIGH” level for a certain time after the signal A changes from “LOW” level to “HIGH” level. Is a signal. As a result, the output of the latch circuit 51 is initialized and fixed to the output corresponding to the state of the fuse shown in FIG. 2A, that is, the state of “broken” or “not blown”. . When the fuse is blown, the output OUT1 of the latch circuit 51 becomes the “LOW” level, the transfer gate 52 is turned off, the clocked inverter 53 is turned on, and the output signal FOUT inverts the level of the address An. Level. On the contrary, when the fuse is “not blown”, the output OUT1 of the latch circuit 51 becomes “HIGH” level, the transfer gate 52 is turned on, the clocked inverter 53 is turned off, and the output signal FOUT is at the level of the address An. Become.

  Further, in the first embodiment, the second repetition pitch P2 is made smaller than the first repetition pitch P1, and the space S generated by the difference between the second repetition pitch P2 and the first repetition pitch P1 is used. The third layout unit 6 is arranged. In the third layout portion 6, a pattern that cannot be repeated by each fuse latch circuit is laid out. The pattern that cannot be repeated is, for example, a wiring for supplying a signal to the fuse latch circuit. In the fuse latch circuit used in the redundancy circuit as shown in FIG. The local address signal line 5 is arranged in a region 7 for arranging a preset local address signal line 5 in the third layout unit 6. The local address signal line 5 connects one of the global address signal lines to the corresponding fuse latch circuit. The global address signal line is, for example, a wiring extending in a direction crossing the local address signal line 5 and is disposed, for example, above the local address signal line 5. In the figure, reference numeral 8 is a contact between the local address signal line 5 and the global address signal. Reference numeral 11 in the figure denotes an in-basic pattern address signal line that connects the local address signal line 5 to the fuse latch circuit. FIG. 3A shows the relationship between the local address signal line 5 and the global address signal line.

  As shown in FIG. 3A, the global address signal line 9-A0 through which the address A0 is propagated is connected to the local address signal line 5-A0 that crosses the global address signal line 9-A0. Further, the local address signal line 5-A0 extends, for example, in a direction crossing the local address signal line 5-A0, and is disposed, for example, below the local address signal line 5-A0, within the basic pattern address signal line 11-A0. Connected to. As a result, the address A0 is input to the fuse latch circuits (FUSE LAT.0) to (FUSE LAT.3). Similarly, the global address signal line 9-A1 through which the address A1 is propagated is connected to the local address signal line 5-A1 crossing the global address signal line 9-A1. Further, the local address signal line 5-A1 extends, for example, in a direction crossing the local address signal line 5-A1, and is located, for example, below the local address signal line 5-A1, in the basic pattern address signal line 11-A1. Connected to. As a result, the address A1 is input to the fuse latch circuits (FUSE LAT.4) to (FUSE LAT.7).

  FIG. 3B shows a cross section taken along line BB in FIG.

  As shown in FIG. 3B, the in-basic pattern address signal lines 11 (11-A0, 11-A1) are formed by, for example, a first conductor layer (1ST) formed on a semiconductor substrate. The address signal line 5 (5-A0, 5-A1) is formed by, for example, the second conductor layer (2ND) above the first conductor layer (1ST), and the global address signal line 9 is, for example, the first conductor layer (1ST). The third conductor layer (3RD) above the second conductor layer (2ND).

  In the semiconductor integrated circuit device according to the first embodiment, the third layout unit 6 in which the local address signal lines 5 are laid out is replaced with the second layout unit in which the basic pattern of the fuse latch circuit is laid out. Separate from 4. As a result, the degree of freedom in the layout of the wiring formed by using the same wiring layer as that of the local address signal line 5 in the second layout section 4 is increased.

  Further, as will be described in detail in the third embodiment, patterns that do not necessarily have to be repeated, such as well contacts, can be laid out in the third layout section 6. Thereby, it is possible to eliminate the well contact from the second layout portion 4.

  In addition, it seems that the repetition pitch P2 of the 2nd layout part 4 becomes smaller than the repetition pitch P2 shown in FIG.16 and FIG.17 will increase the area of the 2nd layout part 4 qualitatively. . However, the degree of freedom of layout is actually improved. Furthermore, the area 106 of the second layout section 4 can be reduced because the space 106 and the well contact shown in FIG. 16 and FIG. it can.

  Further, if the area of the second layout portion 4 is reduced, the length of the local address signal line 5 can be shortened, and the advantage that the parasitic capacitance of the address signal lines including global and local can be suppressed can be obtained. it can.

  Further, since the fuse is simply connected to the fuse latch circuit using a certain wiring layer, the degree of freedom of connection is high. That is, the difference between the pitch P1 and the pitch P2 does not make it difficult to connect the fuse and the fuse latch circuit.

  Next, a modification of the first embodiment will be described.

  FIG. 4 is a layout diagram showing a modification of the first embodiment.

  In FIG. 4, the mark indicated by reference numeral 54 indicates the direction of the fuse latch circuit laid out in the second layout unit 4. A similar mark 54 is also shown in FIG.

  In the first embodiment shown in FIG. 1, the orientations of the marks 54 are all the same, which indicates that the orientations of the basic patterns arranged in the second layout unit 4 are the same.

  On the other hand, in the modification of the first embodiment shown in FIG. 4, the orientations of the marks 54 are alternately reversed. This is because the basic pattern arranged in the second layout unit 4 is alternately a mirror pattern. It is shown that.

  Thus, the basic pattern arranged in the second layout unit 4 may be a mirror pattern alternately.

  Furthermore, the orientation of the basic pattern arranged in the second layout unit 4 may be a variation different from that in FIGS.

  This modification can be applied not only to the first embodiment but also to all the embodiments described below.

  In the first embodiment and its modification, the number of fuse latch circuits corresponding to the same address is four. However, if this number increases, the first layout section 3 and the second layout section 4 will The deviation is integrated accordingly. For this reason, it is possible to make 2nd pitch P2 close to the 1st pitch P1, ie, to enlarge. Thereby, for example, it is possible to reduce the length of the second layout unit 4 in the major axis direction, or it is possible to obtain an advantage that the degree of freedom of layout in the second layout unit 4 is improved. This advantage can be obtained more remarkably as the semiconductor memory has a larger capacity and the number of redundancy circuits further increases.

[Second Embodiment]
FIG. 5 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the second embodiment of the present invention. FIG. 5 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 5, the second embodiment differs from the first embodiment in that the third layout portion 6 ′ is adjacent to each other and corresponds to two different addresses in the fuse latch circuit. That is, it is arranged in the space S generated between the fuse latch circuits.

  In the second embodiment, the same effects as those of the first embodiment can be obtained, and the following effects can be further obtained.

  In the first embodiment, the local address signal lines 5 are arranged one by one in the third layout section 6.

  On the other hand, in the second embodiment, the two third layout sections 6 are combined into one, and the local address signal lines 5 are arranged two by two in the combined third layout section 6 '. By doing so, the width of the third layout portion 6 ′ can be made smaller than the width obtained by adding the two third layout portions 6.

  This is because when one local address signal line 5 is arranged in the third layout section 6, a space is generated on both sides of one local address signal line 5. Therefore, when two local address signal lines 5 are arranged, four spaces are generated on both sides of each of the two signal lines 5. However, if two local address signal lines 5 are arranged in the third layout portion 6 ', only two spaces on one side of the two signal lines 5 and one space therebetween are generated in total. Because.

  Thereby, compared with the first embodiment, the second embodiment can make the second pitch P2 closer to the first pitch P1, and the length of the second layout unit 4 in the major axis direction. Can be reduced, or advantages such as an improvement in the degree of freedom of layout in the second layout section 4 can be obtained.

[Third Embodiment]
The third embodiment is a specific layout example of a fuse and a fuse latch circuit to which the present invention is applied.

  6 and 7 are layout diagrams showing the layout of the semiconductor integrated circuit device according to the third embodiment of the present invention.

  The specific layout example shown in FIG. 6 conforms to the second embodiment, and the basic pattern of the fuse latch circuit arranged in the second layout unit 4 is laid out so as to be a mirror pattern alternately. Is.

  In the layout example shown in FIG. 6, the local address signal line 5 is formed in the third layout portion 6 '. In the second layout portion 4, a wiring 5 ′ formed of the same conductor layer as the local address signal line 5 is formed. The wiring 5 'is a wiring for connecting the MOSFETs constituting the fuse latch circuit.

  FIG. 7 shows a plane pattern of a wiring layer different from the wiring layer shown in FIG.

  As shown in FIG. 7, another wiring pattern is formed under the wiring pattern shown in FIG. 6. In particular, in the third layout portion 6 ′, a wiring 11 ′ for supplying a potential to the well is formed. ing. Further, a well contact 10 is formed on the wiring 11 'to a well in which either an N-channel MOSFET or a P-channel MOSFET constituting the fuse latch circuit is formed.

  In the second layout portion 4, the basic pattern address signal line 11 and the wiring 11 ″ formed of the same conductor layer as the wiring 11 ′ for supplying a potential to the well are formed. Similarly to the wiring 5 ′, the wiring 11 ″ is also a wiring for connecting the MOSFETs constituting the fuse latch circuit.

  Thus, in the third layout portion 6 ′, not only the local address signal line 5, but also the wiring to the well in which either the N-channel MOSFET or the P-channel MOSFET constituting the fuse latch circuit is formed. 11 'or well contact 10 may be formed. The wiring 11 'and the well contact 10 are patterns that do not necessarily have to be repeated in each fuse latch circuit.

  If the wiring 11 ′ and the well contact 10 are arranged in the third layout portion 6 ′ in this way, a pattern that does not necessarily need to be repeated is not repeated unnecessarily, and the area of the fuse latch circuit is further increased. It can be effectively suppressed.

[Fourth Embodiment]
FIG. 8 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 8 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 8, the fourth embodiment differs from the first embodiment in the direction in which the fuse latch circuit is arranged. In the first embodiment, the direction in which the second layout unit 4 is arranged is matched with the direction in which the first layout unit 3 is arranged. On the other hand, in the fourth embodiment, the second layout unit 4 is rotated 90 degrees, and the direction in which the second layout unit 4 is arranged crosses the direction in which the first layout unit 3 is arranged. Are arranged as follows. In the fourth embodiment, the four second layout units 4 are rotated 90 degrees at a time.

  In this case, the second repetition pitch P2 is larger than the first repetition pitch P1. Specifically, the second repetition pitch P2 is less than the first repetition pitch P1 × 4. In the fourth embodiment, the third layout unit 6 is arranged in the space S generated by the difference between the first repetition pitch P1 × 4 and the second repetition pitch P2.

  In the fourth embodiment, the same effect as that of the first embodiment can be obtained.

[Fifth Embodiment]
FIG. 9 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG. 9 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 9, the fifth embodiment is an application of the fourth embodiment to the second embodiment.

  In the fifth embodiment, the same effect as that of the second embodiment can be obtained.

[Sixth Embodiment]
FIG. 10 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the sixth embodiment of the present invention. FIG. 10 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 10, in the sixth embodiment, for example, four fuse latch circuits are collectively set as a basic pattern and arranged in the second layout unit 4. The sixth embodiment is particularly similar to the first embodiment, and the third layout portion 6 is provided in the space S generated by the difference between the first repeat pitch P1 × 4 and the second repeat pitch P2. It is arranged.

  In such a sixth embodiment, the same effect as that of the first embodiment can be obtained.

  Furthermore, if the four fuse latch circuits are collectively used as the basic pattern, the degree of freedom in layout is increased, so that the area of the second layout portion 4 can be further reduced as compared with the first embodiment.

  FIG. 10 shows an example in which the second pitch P2 is made larger than the first pitch P1, but when a plurality of fuse latch circuits corresponding to a plurality of fuses are collectively used as a basic pattern, The pitch P2 of 2 can be made smaller than the first pitch P1. Such a modification is the same in the seventh, eighth, and ninth embodiments described below.

[Seventh Embodiment]
FIG. 11 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the seventh embodiment of the present invention. FIG. 11 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 11, in the seventh embodiment, for example, four fuse latch circuits corresponding to four fuses are collectively set as a basic pattern, and this is arranged in the second layout section 4. The seventh embodiment is particularly similar to the second embodiment, and the first repetition pitch P1 × 4 and the second repetition pitch P2 are provided between the fuse latch circuits corresponding to two different addresses adjacent to each other. The third layout portion 6 ′ is disposed in the space generated by the difference between the third layout portion 6 ′ and the third layout portion 6 ′.

  Even in the seventh embodiment, the same effect as that of the second embodiment can be obtained.

  Furthermore, in the seventh embodiment, since four fuse latch circuits are collectively set as a basic pattern, the degree of freedom in layout can be increased as in the sixth embodiment. Therefore, the area of the second layout portion 4 can be further reduced as compared with the second embodiment.

[Eighth Embodiment]
FIG. 12 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the eighth embodiment of the present invention. FIG. 12 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 12, in the eighth embodiment, for example, four fuse latch circuits corresponding to, for example, four fuses are collectively set as a basic pattern, and this is arranged in the second layout unit 4. The eighth embodiment is different from the sixth and seventh embodiments in that the third layout section 6 is arranged in the second layout section 4. In this case, the second repetition pitch P2 is an integer multiple of the first repetition pitch P1.

  In the eighth embodiment, as in the sixth and seventh embodiments, the third layout is formed in the space generated by the difference between the first repeat pitch P1 × 4 and the second repeat pitch P2. The configuration is not such that the portion 6 is arranged. However, in the eighth embodiment, only one space (or region) for arranging patterns that cannot be repeated or does not need to be repeated in each fuse latch circuit is provided for four fuse latch circuits. It will be enough. Therefore, the same effects as those of the sixth and seventh embodiments can be obtained.

[Ninth Embodiment]
FIG. 13 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the ninth embodiment of the present invention. FIG. 13 shows an example of a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory.

  As shown in FIG. 13, the ninth embodiment is different from the first to eighth embodiments in that fuse latch circuit areas 2R and 2L are arranged on both sides of the fuse area 1, respectively. In each of the fuse latch circuit areas 2R and 2L, half of the four fuses (FUSE), that is, fuse latch circuits (FUSE LAT.) Corresponding to the two fuses are arranged.

  By adopting the configuration of the first embodiment in an apparatus having such an arrangement, the same effects as those of the first embodiment can be obtained.

  As shown in FIG. 13, the second pitch P2 may be larger than, for example, the first pitch P1, but the second pitch P2 may be equal to or less than the first pitch P1.

  Further, as shown in FIG. 13, when the second pitch P2 is made larger than the first pitch P1, the length in the direction crossing the direction in which the second layout portion 4 is arranged may be shortened. Is possible.

  Note that although the ninth embodiment has been described in particular according to the first embodiment, it is also possible to incorporate the configurations of the second to eighth embodiments.

[Tenth embodiment]
In the tenth embodiment, the pitch when arranging a plurality of fuses continuously is irregular.

  Conventionally, when a plurality of fuses are continuously arranged, if the pitch between adjacent fuses is X [μm], the center coordinate of each fuse is located at a position of nX [μm] around the center of a certain fuse. (N is an integer). However, if miniaturization proceeds in the future, the positioning accuracy of the fuse blow machine (for example, laser blow machine) may not be sufficient with respect to the fuse pitch.

  FIG. 14 is a view for explaining the layout of the semiconductor integrated circuit device according to the tenth embodiment of the present invention.

  As shown in FIG. 14, it is assumed that the pitch of fuses (FUSE1 to FUSEm + 2) is X [μm], and the minimum grid on the layout (minimum point for position designation on the layout) is X / 100 [μm]. Further, it is assumed that the minimum positioning pitch of the blow points (BLOW0 to BLOWm + 2) determined by the performance of the fuse blow machine is X ′ [μm] slightly larger than X [μm].

  At this time, the difference between the center coordinates of the fuse and the coordinates of the blow point increases by (X′−X) [μm] every time one fuse moves. Then, when m displacement (m × (X′−X) [μm]) reaches X / 100 [μm], the center coordinate of the mth fuse is set to the coordinate of the mth blow point. It is sufficient to move one grid so as to match.

  By doing so, it is possible to make up for the lack of positioning accuracy of the fuse blow machine, and it is possible to suppress the probability of occurrence of a blow miss due to a coordinate shift. In the above description, X ′ [μm] is the minimum positioning pitch of the blow point. However, when a certain fuse is blown, it may be considered as a pitch limited from the laser accuracy so as not to damage the adjacent fuse.

[Eleventh embodiment]
In the eleventh embodiment, as in the tenth embodiment, the pitch when arranging a plurality of fuses continuously is irregular.

  FIG. 15 is a view for explaining how to determine fuse coordinates according to the eleventh embodiment of the present invention.

  As shown in FIG. 15, it is assumed that the fuse coordinates are 1.25 [μm] pitch, and the minimum digit for specifying the position of the blow point of the blow machine is up to 0.1 [μm]. In this case, the coordinates of 1.25 [μm] must be specified as 1.2 [μm] or 1.3 [μm]. For this reason, an error occurs between the two. Therefore, in the eleventh embodiment, the fuse coordinates are corrected to 1.2 [μm] or 1.3 [μm] in anticipation of the accuracy of the blow machine from the beginning.

  There is no problem if the fuse pitch can be changed to 1.2 [μm] from the beginning, but due to the severe layout of the fuse latch circuit, there may be cases where it cannot be 1.2 [μm] pitch, and the relaxed 1.3 [μm] pitch. In some cases, the necessary number of fuses cannot be arranged in a limited area. In addition, when the redundancy circuit layout is used for several generations, it may be used by multiplying the design data by a reduction ratio. Depending on the reduction ratio, the number of the minimum digit of the fuse coordinates will be the position of the blow point. Often less than the specified minimum digit.

  Even in such a case, according to the eleventh embodiment, since the lack of positioning accuracy of the fuse blow machine can be compensated, the probability of occurrence of a blow miss due to this coordinate shift can be suppressed.

FIG. 1 is a layout diagram showing a layout of a semiconductor integrated circuit device according to a first embodiment of the present invention. 2A is a diagram illustrating a fuse, and FIG. 2B is a circuit diagram illustrating a circuit example of a fuse latch circuit. 3A is a diagram showing a relationship between a local address signal line and a global address signal line, and FIG. 3B is a cross-sectional view taken along line BB in FIG. 3A. FIG. 4 is a layout diagram showing a modification of the first embodiment. FIG. 5 is a layout diagram showing a layout of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 6 is a layout diagram showing a layout of a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 7 is a layout diagram showing a layout of a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 8 is a layout diagram showing a layout of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. FIG. 9 is a layout diagram showing a layout of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. FIG. 10 is a layout diagram showing a layout of a semiconductor integrated circuit device according to a sixth embodiment of the present invention. FIG. 11 is a layout diagram showing a layout of a semiconductor integrated circuit device according to a seventh embodiment of the present invention. FIG. 12 is a layout diagram showing a layout of a semiconductor integrated circuit device according to an eighth embodiment of the present invention. FIG. 13 is a layout diagram showing a layout of a semiconductor integrated circuit device according to the ninth embodiment of the present invention. FIG. 14 is a view for explaining the layout of a semiconductor integrated circuit device according to the tenth embodiment of the present invention. FIG. 15 is a view for explaining how to determine fuse coordinates of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention. FIG. 16 is a layout diagram showing a layout of a conventional semiconductor integrated circuit device. FIG. 17 is a layout diagram showing the layout of another conventional semiconductor integrated circuit device.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Fuse area, 2 ... Fuse latch circuit area, 3 ... 1st layout part, 4 ... 2nd layout part, 5 ... Local address signal line, 6 ... 3rd layout part, 7 ... Local address signal line Areas for placement, 8 ... contacts, 9 ... global address signal lines, 10 ... well contacts, 11 ... wiring.

Claims (7)

A fuse area in which a first layout portion in which fuses are laid out is repeatedly arranged at a first repetition pitch;
A fuse latch circuit area in which a second layout portion in which a fuse latch circuit corresponding to the fuse is laid out is repeatedly arranged at a second repetition pitch smaller than the first repetition pitch;
In each of the second layout portions provided in the fuse latch circuit area and disposed in a space generated by the difference between the first repeat pitch and the second repeat pitch, and And a third layout portion in which at least one of the patterns that do not need to be repeated is laid out. The relationship between the first and second repetition pitches and the space is:
n × P1 = n × P2 + S
(Where n is a natural number, P1 is the first repetition pitch, P2 is the second repetition pitch, and S is the space)
The semiconductor integrated circuit device according to claim 1, wherein:   In the third layout portion, at least one of a wiring for supplying a signal to the fuse latch circuit and a contact to a semiconductor substrate on which the fuse latch circuit is formed is arranged. The semiconductor integrated circuit device according to claim 1. The fuse and the fuse latch circuit are a fuse and a fuse latch circuit used in a redundancy circuit of a semiconductor memory,
A plurality of global address lines are arranged in the direction in which the second layout portion is repeatedly arranged,
2. The local address wiring that connects any one of the plurality of global address wirings arranged to the corresponding fuse latch circuit is arranged in the third layout section. Item 3. The semiconductor integrated circuit device according to any one of Items 2 above.   5. The semiconductor integrated circuit device according to claim 4, wherein the third layout portion exists between fuse latch circuits corresponding to two different addresses that are adjacent to each other in the fuse latch circuit.   A semiconductor integrated circuit device, wherein a layout portion in which fuses are laid out includes fuse areas arranged at irregular and repeating pitches.   7. The semiconductor integrated circuit device according to claim 6, wherein the irregular repetition pitch is matched with a pitch limited by a blow point positioning accuracy of a fuse blow machine or a blow accuracy of a fuse blow machine.

Images