JP2006237447A - Electro-optical device, its manufacturing method, thin film transistor, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electro-optical device providing an excellent and highly accurate display by improving a voltage application effect to both gate electrodes, in a thin film transistor where the gate electrodes are arranged on both the sides of a semiconductor layer, and by sufficiently displaying the switching characteristic of the thin film transistor. <P>SOLUTION: The electro-optical device is provided with: a semiconductor layer 42; and a TFT 30 including a first gate wire 15b (first gate electrode) opposed to one-surface side of a channel area of the semiconductor layer 42 through a ground insulating film 12 (first insulating film), and a gate electrode 32 (second gate electrode) opposed to the other surface side of the channel area through an insulating thin film 2 (second insulating film). The semiconductor layer 42 consists of a lamination film of a first polysilicon film 42a opposed to the first gate wire 15b and a second polysilicon film 42b opposed to the gate electrode 32 (33). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electro-optical device, a manufacturing method thereof, a thin film transistor, and an electronic apparatus.

As a display device such as a liquid crystal device or an EL (electroluminescence) device, an active matrix type electro-optical device using a TFT (thin film transistor) as a pixel switching element has been conventionally known. In these electro-optical devices as well, there is a strong general demand for high-quality display, and there is a demand for high definition (narrow pitch of pixels) without impairing the aperture ratio and holding characteristics of the pixels.
In general, in a TFT with a top gate structure where the gate electrode is provided on the opposite side of the substrate across the semiconductor layer, a light shielding layer is formed between the semiconductor layer and the substrate to prevent light from entering from the back side of the substrate. is doing. However, when the light shielding layer is formed, parasitic capacitance may be generated between the source / drain regions and the light shielding layer, and the image voltage may vary. Therefore, as a means for solving this problem, a TFT having a structure in which gate electrodes are provided on both sides of a semiconductor layer is known (see, for example, Patent Document 1).
Japanese Patent Application Laid-Open No. 09-090405

  Recently, a technique for obtaining a polysilicon film by crystallizing an amorphous silicon film formed on a substrate by laser irradiation is known. In the process of forming TFTs using this technology, called low-temperature polysilicon technology, laser irradiation for crystallization of amorphous silicon can be performed at room temperature, so the dehydrogenation process and impurity activation process of the amorphous silicon film It is possible to form a polysilicon film at a temperature not exceeding the heating temperature (about 600 ° C.) in the process, and the process temperature is greatly reduced as compared with the conventional technique for heating the entire substrate to crystallize the amorphous silicon film. Can be reduced.

  In addition, in the TFT using the low-temperature polysilicon technology, it is considered that an electro-optical device including a TFT having good electrical characteristics can be manufactured at low cost if the gate electrode is provided on both sides of the semiconductor layer. . However, when the present inventor has studied such a configuration, even if an operating voltage is applied from both the gate electrodes provided above and below the semiconductor layer made of the low-temperature polysilicon film, the voltage applied from one gate electrode is applied. It was found that the effect was weak and the switching characteristics of the TFT could not be fully exhibited.

  Therefore, an object of the present invention is to sufficiently exhibit the switching characteristics of the thin film transistor by making the voltage application effect of the both gate electrodes good in the thin film transistor in which the gate electrodes are arranged on both sides of the semiconductor layer. It is an object of the present invention to provide an electro-optical device capable of obtaining a fine display and a manufacturing method thereof.

The electro-optical device of the present invention is an electro-optical device including a transistor formed on a substrate, the transistor including a semiconductor layer and a first insulating film on one surface side of a channel region of the semiconductor layer. And a second gate electrode opposed to the other surface side of the channel region via a second insulating film, and the semiconductor layer is opposed to the first gate electrode. It is characterized by comprising a laminated film of a first semiconductor film and a second semiconductor film facing the second gate electrode.
According to this configuration, since the semiconductor layer is a stacked film of the first semiconductor film and the second semiconductor film, the first semiconductor film facing the first gate electrode with the first insulating film interposed therebetween, For example, the crystal structure of each of the second semiconductor films facing the second gate electrode through the two insulating films is adjusted so that good electrical characteristics can be obtained in relation to the first gate electrode and the second gate electrode. Thus, the performance of the thin film transistor including the gate electrode on both sides of the semiconductor layer can be sufficiently exhibited. Therefore, according to the present invention, it is possible to provide an electro-optical device capable of switching pixels at high speed by the thin film transistor and sufficiently supporting high-definition display.

The electro-optical device of the present invention is an electro-optical device including a thin film transistor formed on a substrate, and the thin film transistor includes a semiconductor layer and a first insulating film on one surface side of a channel region of the semiconductor layer. And a second gate electrode opposed to the other surface side of the channel region via a second insulating film, and the semiconductor layer is opposed to the first gate electrode. It is characterized by comprising a laminated film of a first polysilicon film and a second polysilicon film facing the second gate electrode.
That is, according to the present invention, in order to solve the above-mentioned problem, the semiconductor layer made of a polysilicon film has a two-layer structure, so that the first gate electrode and the second gate electrode respectively disposed on both sides of the semiconductor layer are sandwiched. It is possible to form a polysilicon film having an optimized structure for each, and to improve the electrical characteristics of the TFT (thin film transistor).
According to this configuration, the state of the crystal structure of the first polysilicon film facing the first gate electrode is optimized, and the state of the crystal structure of the second polysilicon film facing the second gate electrode is optimized. Therefore, both the voltage application effect of the first gate electrode and the voltage application effect of the second gate electrode can be improved, and the characteristics of the TFT can be improved. In addition, since the gate electrode is formed on both sides of the channel region, light incident on the TFT can be blocked by the gate electrode, and the off-leak current of the TFT can be reduced. Therefore, according to the present invention, there is provided an electro-optical device capable of sufficiently switching high-definition display capable of switching a pixel at high speed with a low off-current TFT having excellent electrical characteristics and maintaining a good voltage. be able to.

In the electro-optical device according to the aspect of the invention, the thin film transistor is formed by sequentially stacking the first gate electrode, the first insulating film, the semiconductor layer, the second insulating film, and the second gate electrode on a base. Preferably, the first polysilicon film formed on the base side of the semiconductor layer is thicker than the second polysilicon film.
With such a configuration, energy (for example, laser energy) necessary for forming the second polysilicon film can be reduced, and both the first polysilicon film and the second polysilicon film have good crystallinity. A semiconductor film can be obtained.
In the case of forming a semiconductor layer formed by laminating the above two layers of polysilicon films, in the present invention, after forming a first amorphous silicon film on a substrate, annealing is performed under optimum conditions to crystallize the first polycrystal silicon film. Forming a silicon film; forming a second amorphous silicon film on the first polysilicon film; and crystallizing the second amorphous silicon film under optimum annealing conditions to form a second polysilicon film Forming the step. Therefore, since the crystallization of the second amorphous silicon film for obtaining the second polysilicon film is performed on the already formed first polysilicon film, the crystallization of the existing first polysilicon film is performed. In consideration of the influence, it is preferable that the second amorphous silicon film is formed thin so that the thickness of the obtained second polysilicon film is thinner than that of the first polysilicon film. With this configuration, most of the heat generated during crystallization of the second layer (second amorphous silicon film) is used as energy for melting the second amorphous silicon. The influence of thermal energy on the first polysilicon film can be reduced, and an appropriate crystal structure can be obtained in both the first polysilicon film and the second polysilicon film.

The electro-optical device of the present invention includes a storage capacitor electrically connected to the thin film transistor, the storage capacitor being formed in the same layer as the first gate electrode, and the second gate electrode. And a second capacitor electrode formed in the same layer and a third capacitor electrode formed in the same layer as the semiconductor layer.
According to this configuration, the first capacitance electrode formed simultaneously with the formation of the first gate electrode, the third capacitance electrode formed simultaneously with the formation of the semiconductor layer, and the second gate electrode are formed. Since the storage capacitor can be configured by the second capacitor electrode formed at the same time, the electro-optical device can be improved in performance without increasing the number of steps. In the present invention, the off-current of the TFT can be reduced as described above, so that the storage capacity can be reduced. Therefore, the aperture ratio can be improved by reducing the area of the storage capacitor, and an electro-optical device that can obtain a bright display can be obtained.

The electro-optical device according to the aspect of the invention includes a signal wiring that is electrically connected to the thin film transistor and extends on the base, and a part of the first capacitor electrode and a part of the third capacitor electrode are The signal wiring is arranged so as to overlap with the signal wiring, and a part of the storage capacitor is formed at the position.
According to this configuration, a part of the storage capacitor can be formed in a region overlapping with the signal wiring in a plane, so that the storage capacitor and the signal wiring, which are light shielding members, can share the planar region. The aperture ratio of the electro-optical device can be improved.

  In the electro-optical device according to the aspect of the invention, a plurality of the channel regions are formed in the semiconductor layer of the thin film transistor, and the first gate electrode and the second gate electrode are provided corresponding to each channel region. Features. That is, the electro-optical device of the present invention can be an electro-optical device including a multi-gate TFT. By adopting the multi-gate structure, the voltage across one channel region can be reduced, so that the off-current can be further reduced.

  The thin film transistor of the present invention includes a semiconductor layer, a first gate electrode facing the one surface side of the channel region of the semiconductor layer via a first insulating film, and a second insulating film on the other surface side of the channel region. The semiconductor layer is formed of a stacked film of a first polysilicon film facing the first gate electrode and a second polysilicon film facing the second gate electrode. It is characterized by that. According to this thin film transistor, for the first gate electrode, the crystal structure of the first polysilicon film facing the first gate electrode is optimized so that a good voltage application effect can be obtained, and for the second gate electrode, the second poly Since the crystal structure of the silicon film can be optimized to obtain a good voltage application effect, good switching characteristics can be obtained.

The electro-optical device manufacturing method of the present invention includes a step of forming a metal film on a substrate to form a first gate electrode, a step of forming a first insulating film covering the first gate electrode, Forming a first amorphous silicon film on one insulating film and crystallizing the first amorphous silicon film to form a first polysilicon film; and a second on the first polysilicon film. A process of forming an amorphous silicon layer, crystallizing the second amorphous silicon film to form a second polysilicon film, and patterning a laminated film of the first polysilicon film and the second polysilicon film Forming a semiconductor layer having a predetermined shape, forming a second insulating film so as to cover the semiconductor layer, and patterning a metal film on the second insulating film, thereby forming the first gate. A process for forming the second gate electrode at a position overlapping the electrode in a plane. Characterized in that it has and.
According to this manufacturing method, since the crystallization of the amorphous silicon film is performed in two steps, the amorphous silicon film formed at one time can be thinned, thereby reducing the incident energy required for crystallization. Therefore, the crystal structure of each polysilicon film can be easily controlled. Therefore, the voltage effect applied from the first and second gate electrodes can be made equal, and the effect of improving the transistor performance can be obtained. Furthermore, since the total thickness of the homogeneous semiconductor layer can be increased, the manufacturing yield is also improved.

  The method of manufacturing an electro-optical device according to the present invention is characterized in that the amorphous silicon film is crystallized by irradiating the amorphous silicon film with a laser. According to this manufacturing method, when the crystallization of the amorphous silicon film is performed in two steps, the influence of heat on the existing polysilicon film can be reduced, so that the first polysilicon film and the second polysilicon film can be reduced. It becomes easy to optimize the crystal structure on both sides of the film, and an electro-optical device can be manufactured efficiently with a high yield.

  The method of manufacturing an electro-optical device according to the present invention is characterized in that the first amorphous silicon film is formed thicker than the second amorphous silicon film. According to this manufacturing method, after the first amorphous silicon film is crystallized to form the first polysilicon film, the energy required for the crystallization is reduced when the second amorphous silicon film is crystallized. Therefore, a polysilicon film having a desired crystal structure can be obtained without affecting the first polysilicon film, and both the first polysilicon film and the second polysilicon film are optimized. A crystal structure can be obtained. Therefore, it is possible to manufacture a TFT with excellent switching characteristics that can obtain a good voltage application effect on both the first gate electrode and the second gate electrode.

  An electronic apparatus according to the present invention includes the electro-optical device according to the present invention described above. According to this configuration, an electronic device including a stable display unit with high brightness and high definition is provided.

The present invention will be described below with reference to the drawings.
FIG. 1A is a plan view of a liquid crystal device as an example of an electro-optical device according to the present invention as viewed from the counter substrate side together with each component, and FIG. FIG. 2 is a block diagram showing an electrical configuration of various wirings and peripheral circuits provided on an active matrix substrate constituting the liquid crystal device, and FIG. 3 is a pixel region of the liquid crystal device. FIG.

[Overall configuration of liquid crystal device]
As shown in FIGS. 1A and 1B, in this liquid crystal device (electro-optical device), a TFT array substrate 10 and a counter substrate 20 are bonded together by a sealing material 52 having a substantially rectangular frame shape in plan view. The liquid crystal layer 50 is enclosed in a region surrounded by the sealing material 52. A peripheral parting part 53 having a rectangular frame shape in plan view is formed along the inner peripheral side of the sealing material 52, and an area inside the parting part is set as an image display area 51. A data line driving circuit 201 and an external circuit mounting terminal 202 are formed along one side (the lower side in the drawing) of the TFT array substrate 10 in the region outside the sealing material 52, and the two sides adjacent to this one side are formed. Scanning line driving circuits 204 and 204 are formed along the lines to form peripheral circuits. On the remaining one side (illustrated upper side) of the TFT array substrate 10, a plurality of wirings 205 are provided for connecting the scanning line drive circuits 204 on both sides of the image display area 51. Further, an inter-substrate conductive material 206 for providing electrical continuity between the TFT array substrate 10 and the counter substrate 20 is disposed at each corner of the counter substrate 20. The liquid crystal device of this embodiment is configured as a transmissive liquid crystal device, and modulates light from a light source (not shown) arranged on the TFT array substrate 10 side and emits it from the counter substrate 20 side. .

  Instead of forming the data line driving circuit 201 or the scanning line driving circuits 204 and 204 on the TFT array substrate 10, for example, a COF (Chip On Film) substrate on which a driving LSI is mounted and a TFT array substrate 10 are mounted. You may make it electrically and mechanically connect with the terminal group formed in the periphery part via an anisotropic conductive film. In the liquid crystal device, the type of liquid crystal to be used, that is, an operation mode such as a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, a vertical alignment mode, or a normally white mode / normally black mode is used. Accordingly, a retardation plate, a polarizing plate, and the like are arranged in a predetermined direction, but the illustration is omitted here.

  In the image display area 51 of the liquid crystal device having such a structure, as shown in FIG. 2, a plurality of scanning lines 3a and data lines 6a are formed in the horizontal direction and the vertical direction, respectively. Pixel regions 41 each including a TFT (thin film transistor) 30, a pixel electrode 9, and a storage capacitor 70 are arranged in a matrix at the intersection of the data lines 6 a. The gate and source of the TFT 30 are connected to the scanning line 3 a and the data line 6 a, respectively, and the drain is connected to the pixel electrode 9. In addition, the storage capacitor 70 provided to improve the retention characteristic of the pixel is connected in parallel with the pixel electrode 9.

As shown in the circuit configuration diagram of FIG. 2, the scanning line driving circuit 204 is mainly composed of a vertical shift register, and a pulse based on a reference clock input from an external control device via a clock signal line (not shown). The scanning signals G1, G2,... Gm are applied to the scanning line 3a line-sequentially within one vertical scanning period. In addition, a predetermined voltage or a pulsed electric signal can be applied to the capacitor line 3b as necessary.
The data line driving circuit 201 sequentially supplies sampling driving signals S1, S2,... Sn to each sampling driving signal line 111 based on a reference clock input from an external control device via a clock signal line (not shown). A horizontal shift register 201a and a sampling circuit 201b for sampling the image signals VID1 to VID6 supplied via the image signal line 112 are provided.

  The sampling circuit 201b includes a sampling switch (circuit thin film transistor) 131 provided for each data line. Each sampling switch 131 receives sampling drive signals S1, S2,... Sn from the horizontal shift register 110. The image signals VID1 to VID6 sampled for each of the six image signal lines 112 are sequentially applied to each group of six adjacent data lines 6a. Thereby, the sampled image signal is supplied to each data line 6a in one horizontal scanning period (a period in which the scanning signal is supplied to one scanning line 3a by the scanning line driving circuit 204). It has become.

[Detailed pixel configuration]
3 is a plan configuration diagram showing one pixel region on the TFT array substrate 10 constituting the liquid crystal device of the present embodiment. FIG. 4 is a cross-sectional configuration diagram taken along the line AA ′ in FIG. These are the cross-section block diagrams which follow the BB 'line | wire.
As shown in FIG. 3, a data line 6a and a second gate wiring (scanning line) 3a are provided on the TFT array substrate so as to intersect with each other, and further, a second extending along the second gate wiring 3a. One gate wiring 15b is formed. A substantially planar bowl-shaped semiconductor layer 42 is provided in a substantially rectangular pixel area 41 partitioned by the data line 6a and the second gate wiring 3a. The second gate wiring 3a includes a scanning line main line portion 31 extending in a direction intersecting with the data line 6a, and two gate electrodes branched from the scanning line main line portion 31 and extended toward the center side of the pixel region 41 ( Second gate electrodes) 32 and 33, and these gate electrodes 32 and 33 are arranged so as to intersect with a portion extending in parallel with the scanning line main line portion 31 of the semiconductor layer 42. A TFT having a gate (double gate) structure is formed. The TFT 30 is not limited to the illustrated dual gate structure, and may have a structure (triple gate structure) including three gate electrodes.

One end of the substantially L-shaped semiconductor layer 42 in plan view is electrically connected to the data line 6a through the source contact hole 55 provided at the intersection with the data line 6a, while the other end of the pixel region 41 is connected. A storage capacitor electrode (third capacitor electrode) 42a extending inward and having an L shape in plan view is formed.
The storage capacitor electrode 42c is disposed so as to overlap the capacitor line (second capacitor electrode) 3b extending in parallel with the scanning line main line portion 31 in a plane. A portion of the L-shaped storage capacitor electrode 42 c extending in the vertical direction in the figure overlaps with the data line 6 a in the plan view and extends to the side edge of the pixel region 41.

  The pixel electrode 9 formed in a planar region substantially overlapping with the pixel region 41 is made of a transparent conductive material such as ITO, and is electrically connected to the semiconductor layer 42 via the intermediate electrode layer 58. That is, the pixel electrode 9 and the intermediate electrode layer 58 are electrically connected through the pixel contact hole 57, and the intermediate electrode layer 58 and the semiconductor layer 42 of the TFT 30 are electrically connected through the drain contact hole 56. Thus, the pixel electrode 9 and the TFT 30 are electrically connected. The intermediate electrode layer 58 is disposed at a position overlapping the capacitor line 3b in plan view.

  The pixel region 41 is provided with a capacitor electrode portion (first capacitor electrode) 15a having substantially the same shape as the L-shaped storage capacitor electrode 42c in plan view and disposed at substantially the same position as the storage capacitor electrode 42c in plan view. The capacitor electrode portion 15a extends along the second gate wiring 3a, and is formed in the same layer as the first gate wiring 15b arranged in a plane overlapping with a portion extending in the horizontal direction of the semiconductor layer 42 in the drawing. Has been. The capacitor electrode portion 15a and the first gate wiring 15b are formed in the same layer below the semiconductor layer 42 by using the same light shielding material, and shield the light incident on the TFT 30 and the like in the pixel region 41. The member 15 is configured. The light shielding member 15 is formed in a predetermined planar shape using a light shielding material such as WSi.

  The first gate wiring 15b functions as a first gate electrode of the TFT 30 at a position where the first gate wiring 15b overlaps the gate electrodes 32 and 33 in plan view. The capacitor electrode portion 15a is disposed so as to substantially overlap the storage capacitor electrode 42c in a plan view, and is electrically connected to the capacitor line 3b via the contact hole 59, so that one electrode of the storage capacitor 70 is provided. Is configured. In this manner, by providing the conductive connection portion between the capacitive line 3b and the capacitive electrode portion 15a in the pixel region 41, it is not necessary to route the capacitive electrode portion 15a to the outside of the image display region. The disconnection of the line 6a) and the crosstalk between the wirings can be effectively prevented.

  4 and 5, the TFT array substrate 10 has a base insulating film 11 formed on one surface side of a substrate body (base) 10a made of, for example, quartz, glass, plastic, or the like. On the base insulating film 11, a light shielding member 15 (capacitance electrode portion 15a, first gate wiring 15b) is formed. A first interlayer insulating film 12 is formed on the base insulating film 11 including the light shielding member 15, and a semiconductor layer 42 is provided on the first interlayer insulating film 12. That is, a layer between the base insulating film 11 and the first interlayer insulating film 12 is a layer of the light shielding member 15.

  The base insulating film 11 functions as a buffer layer against overetching in the patterning process of the light shielding member 15, and the first interlayer insulating film 12 insulates the light shielding member 15 from the semiconductor layer 42. Therefore, the first interlayer insulating film 12 constitutes a first insulating film that insulates the semiconductor layer 42 from the first gate wiring 15 b functioning as the first gate electrode of the TFT 30. In addition, the base insulating film 11 and the first interlayer insulating film 12 have an effect of suppressing deterioration of the characteristics of the TFT 30 due to surface roughness or contamination of the substrate body 10a.

  As described above, the TFT 30 has a dual gate structure and an LDD (Light Doped Drain) structure. More specifically, the TFT 30 includes gate electrodes 32 and 33, two channel regions 1 a formed in regions of the semiconductor layer 42 facing the gate electrodes 32 and 33, gate electrodes 32 and 33, and the semiconductor layer 42. And an insulating thin film (second insulating film) 2 constituting a gate insulating film that insulates the main body. Then, a low concentration source region 1b and a low concentration drain region 1c formed on both sides of the two channel regions 1a to form an LDD portion, and a high concentration source region 1d and a high concentration source region formed on both sides of these LDD portions, respectively. A concentration drain region 1e and a high concentration source / drain region 1f formed between the channel regions 1a are provided.

  The semiconductor layer 42 according to the present invention is made of a polysilicon film. As the polysilicon film of the semiconductor layer 42, an amorphous silicon film (amorphous silicon film) formed on the substrate is polycrystallized by a low-temperature process such as laser annealing or Ni-assisted solid phase growth. It is preferable to use a low-temperature polysilicon film. The reason for the low temperature process is that the process temperature can be greatly reduced as compared with the method of crystallizing the amorphous silicon film formed on the substrate by heating the entire substrate. That is, in a TFT manufacturing process using a polysilicon film crystallized by laser irradiation, the laser irradiation process can be performed at room temperature, so that an amorphous silicon film dehydrogenation process or impurity activation process can be performed. Manufacturing at a process temperature not exceeding the temperature (about 600 ° C.) becomes possible. In addition, in the Ni-assisted solid phase growth method, since the temperature at which the amorphous silicon is heated and crystallized can be suppressed, the dehydrogenation process of the amorphous silicon film and the Ni gettering process are included. Can be produced at a process temperature of 600 ° C. or lower.

  The semiconductor layer 42 according to the present invention has a structure in which two upper and lower polysilicon films are stacked on the substrate body 10a. FIG. 6 shows an enlarged cross-sectional structure in the vicinity of the semiconductor layer 42 forming the channel region of the TFT according to the present invention. In the present invention, in addition to the LDD structure of the TFT, a storage capacitor electrode is formed in the semiconductor layer 42. In FIG. 6, the description will focus on the channel region of the TFT.

  As shown in FIG. 6, the first gate wiring 15b (first gate electrode) is formed on the substrate body 10a via the base insulating film 11, and the first interlayer insulating film 12 ( A first insulating film) is formed. On the first interlayer insulating film 12, a semiconductor layer 42 having a two-layer structure in which a first polysilicon film 42a and a second polysilicon film 42b are sequentially stacked is provided. Then, the gate electrodes 32 and (33) are formed on the second polysilicon film 42b via the insulating thin film (second insulating film) 2 to constitute the TFT 30. The first gate wiring 15b and the gate electrodes 32 (33) are electrically connected to each other through a contact hole 60 that penetrates the first interlayer insulating film and the insulating thin film 2.

  In order to form the semiconductor layer 42 having the two-layer structure, first, a first amorphous silicon film is formed on the first interlayer insulating film 12. Thereafter, the first amorphous silicon film is crystallized by means of laser irradiation, for example, to obtain a first polysilicon film 42a. Next, a second amorphous silicon film is formed on the first polysilicon film 42a, and then the second amorphous silicon film is crystallized by means such as laser irradiation to form a second polysilicon film 42b. obtain. In crystallization of each of the amorphous silicon films, appropriate electrical characteristics can be obtained by applying voltage from the first gate wiring 15b and the gate electrodes 32 and 33 facing the first polysilicon film 42a and the second polysilicon film 42b, respectively. The crystallization conditions are set so that is obtained. Since the electrical characteristics of the TFT are greatly affected by the crystal structure of the semiconductor layer, particularly the size and uniformity of the crystal grains, in setting the crystallization conditions, the first polysilicon film 42a and the second polysilicon film 42b Conditions are set so that the crystal grain size can be uniformly formed at a predetermined size.

  When the second polysilicon film 42b on the upper layer side is formed, crystallization is performed on the existing first polysilicon film 42a. The heat generated during the crystallization of the second amorphous silicon film is Since most of the energy used for melting the amorphous silicon is used, the heat does not cause the first polysilicon film 42a to be melted and recrystallized, and the influence is small. Therefore, by adopting the above formation method, appropriate crystal structure control can be performed in each of the first polysilicon film 42a and the second polysilicon film 42b.

  The crystal structure of the semiconductor layer 42 obtained by the above manufacturing method is schematically shown in FIG. In FIG. 7A, the amorphous silicon layer is crystallized by irradiating a laser from the upper side of the figure. However, as in the present invention, the semiconductor layer 42 is divided into the first polysilicon film 42a and the second polysilicon film 42b. If the layers are formed separately, the difference in size between the lower crystal grain 45a and the upper crystal grain 45c in each polysilicon film is reduced, and a more uniform semiconductor layer 42 is obtained. On the other hand, when a single layer amorphous silicon film is formed and crystallized as in the prior art, when the amorphous silicon film is crystallized by laser irradiation, the crystal Since the crystallization time becomes non-uniform, as shown in FIG. 7B, the upper crystal grain 45b after crystallization becomes larger than the crystal grain of the lower crystal grain 45a. For this reason, the size of the crystal grains is different between the upper and lower portions of the semiconductor layer 42, and in the TFT having the structure in which the gate electrodes are provided on both sides of the semiconductor layer, the electric characteristics with respect to the respective gate electrodes become non-uniform. It becomes impossible to fully exhibit the characteristics of.

  In the manufacturing method according to the present invention, the second amorphous silicon film formed on the first polysilicon film 42a is crystallized under optimum heating conditions as the second polysilicon film 42b. Considering the influence of heat on the first polysilicon film 42a on the side, the thickness of the second amorphous silicon film is preferably thinner than the first polysilicon film 42a (first amorphous silicon film). . Thus, by thinning the second amorphous silicon film on the upper layer side, the volume melted during crystallization can be reduced, and the laser energy required for crystallization can be reduced. The influence of heat on the polysilicon film 42a can be further reduced, and the yield can be improved.

  As in the present invention, the crystal structures of the first polysilicon film 42a corresponding to the first gate wiring 15b as the first gate electrode and the second polysilicon film 42b corresponding to the gate electrodes 32 and 33 are respectively optimized. As a result, the electrical characteristics of the TFT can be improved. Here, FIG. 8 schematically illustrates the operating state of the TFT 30. When a voltage is applied to the upper and lower gate electrodes in the TFT, charges (holes) 115 and 116 are formed at the interface between the insulating thin film 2, the first interlayer insulating film 12, and the channel region 1a of the semiconductor layer 42 as shown in FIG. It is formed. In the present invention, as described above, since the first polysilicon film 42a and the second polysilicon film 42b have their crystal structures appropriately controlled, the first gate wiring 15b, the gate electrode 32, According to the voltage applied via 33, the holes are formed well in the vicinity of each electrode, and the switching characteristics of the TFT can be sufficiently exhibited.

4 and 5 again, the second interlayer insulating film 13 is formed so as to cover the gate electrodes 32, 33, the capacitor line 3b, and the insulating thin film 2, and the second interlayer insulating film 13 is formed. The data line 6a and the intermediate electrode layer 58 are formed on the same layer. The data line 6a and the intermediate electrode layer 58 are formed using a low resistance metal such as Al.
A source contact hole 55 and a drain contact hole 56 that penetrate the second interlayer insulating film 13 and reach the semiconductor layer 42 are formed, and the high concentration source of the data line 6 a and the semiconductor layer 42 is formed via the source contact hole 55. The region 1 d is electrically connected, and the intermediate electrode layer 58 and the high concentration drain region 1 e of the semiconductor layer 42 are electrically connected through the drain contact hole 56.

A third interlayer insulating film 14 is formed so as to cover the data line 6 a and the intermediate electrode layer 58, and a pixel electrode 9 is formed on the third interlayer insulating film 14. In the planar region of the intermediate electrode layer 58, a pixel contact hole 57 that reaches the intermediate electrode layer 58 through the third interlayer insulating film 14 is formed, and the pixel electrode 9 and the intermediate electrode are connected via the pixel contact hole 57. The layer 58 is electrically connected. With the above configuration, the high concentration drain region 1 e of the semiconductor layer 42 and the pixel electrode 9 are electrically connected via the intermediate electrode layer 58.
Further, an alignment film 17 made of a polyimide film or the like subjected to an alignment process such as a rubbing process is provided on the pixel electrode 9 and the third interlayer insulating film 14.

As shown in FIGS. 3 to 5, in the liquid crystal device of this embodiment, the plane of the storage capacitor electrode 42 c formed by extending the high-concentration drain region 1 e of the semiconductor layer 42 toward the center of the pixel region 41. In the region, a storage capacitor 70 is configured by laminating members made of a plurality of conductive materials via the insulating thin film 2 and the interlayer insulating films 12 to 14.
More specifically, in the formation region of the storage capacitor 70, the capacitor electrode portion 15a of the light shielding member layer is disposed opposite to the lower side of the storage capacitor electrode 42c via the first interlayer insulating film 12, and the storage capacitor electrode A part of 42c and a part of the capacitive electrode portion 15a are extended to the data line 6a side, and are opposed to each other in the layer thickness direction at a position overlapping the data line 6a in a plane. On the upper layer side of the storage capacitor electrode 42c, the capacitor line 3b is disposed so as to face the insulating thin film 2. Further, the capacitor line 3 b and the intermediate electrode layer 58 are disposed to face each other with the second interlayer insulating film 13 interposed therebetween.
As shown in FIG. 5, the capacitor electrode portion 15a sandwiching the storage capacitor electrode 42c and the capacitor line 3b are electrically connected via the contact hole 59, and as shown in FIG. The intermediate electrode layer 58 is electrically connected through the drain contact hole 56.

  As described above, the storage capacitor 70 includes the first storage capacitor unit including the capacitor electrode unit 15a and the storage capacitor electrode 42c, the second storage capacitor unit including the storage capacitor electrode 42c and the capacitor line 3b, and the capacitor line. 3b and a third storage capacitor portion composed of the intermediate electrode layer 58 are stacked in the layer thickness direction. With this configuration, in the storage capacitor 70, a large capacity can be obtained while saving the plane area occupied in the pixel region 41. As a result, the liquid crystal device according to the present embodiment increases the aperture ratio of the pixel region 41. It is possible to obtain a bright display even when the pixel pitch is narrowed to increase the definition.

  In the liquid crystal device according to the present embodiment, as shown in FIGS. 3 and 5, the storage capacitor 70 is formed in the planar regions of the capacitor electrode portion 15 a, the storage capacitor electrode 42 c, the capacitor line 3 b, and the intermediate electrode layer 58. The region is formed so as to become smaller (narrower) sequentially from the substrate body 10a side. As a result, the formation region of the member laminated on one member can be prevented from covering the step portion of the insulating film, and the capacity leak at the step portion where the insulating film tends to be thin can be prevented well. It has a structure.

  On the other hand, the counter substrate 20 includes a common electrode 21 formed in a solid shape on the liquid crystal layer 50 side of the substrate body 20 a and an alignment film 22 formed so as to cover the common electrode 21. The common electrode 21 can be formed of a transparent conductive material such as ITO, and the alignment film 22 can have the same configuration as the alignment film 17 of the TFT array substrate 10 described above. Further, when performing color display, a color filter including, for example, R (red), G (green), and B (blue) color material layers corresponding to each pixel region 41 is provided on the substrate body 10a or 20a. What is necessary is just to form.

In the liquid crystal device including the image display region having the above-described configuration, the first gate wiring 15b made of a light-shielding material and the capacitor electrode portion 15a are provided in the light-shielding member layer between the semiconductor layer 42 and the substrate body 10a. . The first gate wiring 15b is formed so as to cover the channel region of the TFT 30 from the substrate body 10a side, and also functions as a light shielding film that blocks light incident on the TFT 30 from the substrate body 10a side.
Furthermore, in the liquid crystal device of this embodiment, the TFT 30 has a multi-gate structure, thereby reducing the voltage on both sides of one channel region 1a and reducing off-leakage current. Since the LDD structure in which the low concentration source region 1b and the low concentration drain region 1c are formed is employed, the off-current can be reduced.

  For example, in a high-definition liquid crystal device such as a 2.4-inch diagonal QVGA (pixel size 51 μm × 153 μm, 166 ppi (pixel / inch)) display panel, the sum of the liquid crystal capacity and the storage capacity of the pixel is small. If the leakage current of the TFT 30 as a switching element is large, the display quality cannot be maintained due to the leakage of charges. In a polycrystalline silicon TFT, an on-current is large but an off-current is also large. Therefore, it is particularly important to suppress leakage current. In the liquid crystal device of the present embodiment, the leakage current can be suppressed to a low level by the above-described actions. In addition, the leakage current can be effectively reduced in this way, and the storage area 70 having the above-described stacked structure can reduce the plane area of the storage capacity 70 and increase the aperture ratio of the pixel. It is like that. The present invention can obtain a particularly great effect when the pixel area is reduced as in a high-definition liquid crystal device of 250 ppi (for example, pixel size: 24 μm × 102 μm) or more.

  In the present embodiment, as shown in FIG. 3, the first gate wiring 15b and the second gate wiring 3a are disposed so as to be spaced apart in a plane. With this configuration, it is possible to prevent crosstalk between the first gate wiring 15b and the second gate wiring 3a that can receive an electric signal. By adopting a configuration in which both are separated in this way, the insulating film (the first interlayer insulating film 12 and the insulating thin film 2) between the first gate wiring 15b and the second gate wiring 3a can be thinned. Therefore, the capacitance formed by the capacitor electrode portion 15a and the storage capacitor electrode 42c formed in the same layer as the first gate wiring 15b can be increased, which contributes to the reduction of the storage capacitor area.

  Furthermore, the reduction in the plane area of the storage capacitor 70 effectively works to improve the manufacturing yield when using a low temperature process. If the film forming temperature when forming the insulating film of each layer is low, the covering property of the insulating film is likely to deteriorate, and pinholes are likely to occur particularly in the thin insulating film (gate insulating film) 2. In the capacitor formed between the capacitor line 3b, leakage is likely to occur. Therefore, if the plane area of the storage capacitor 70 can be reduced, the probability that a pinhole is disposed in the region sandwiched between the capacitor line 3b and the storage capacitor electrode 42c is reduced, so that the operation failure due to the capacitor leak is reduced and high. A liquid crystal device can be manufactured with a manufacturing yield.

  Further, as shown in FIG. 3, a part of the capacitor electrode portion 15a extends so as to overlap the data line 6a in plan view, and the capacitor electrode portion 15a is made of a light shielding material. Therefore, the capacitor electrode portion 15 a also functions as a light shielding film (black matrix) that partitions the pixel region 41 in the TFT array substrate 10. With such a configuration, it is not necessary to provide the light shielding film in the direction along the data line 6a on the counter substrate 20, and the aperture ratio of the pixel region 41 can be improved. That is, in the case where the light shielding film is provided on the counter substrate 20 side, it is necessary to form it thicker than the width of the data line 6a in consideration of the misalignment between the TFT array substrate 10 and the counter substrate 20, but on the TFT array substrate 10 side. This is because when the light shielding film is provided, it is not necessary to take a margin for the above-described misalignment, and it is possible to reduce the width to the same extent as the data line 6a as shown in FIG.

[Peripheral circuit]
Next, circuit thin film transistors mounted on peripheral circuits (the data line driving circuit 201 and the scanning line driving circuit 204) in the liquid crystal device of this embodiment will be described. FIG. 9 is a diagram illustrating a configuration example of a circuit TFT that can be mounted on the peripheral circuit illustrated in FIGS. 1 and 2.

FIG. 9A is a plan configuration diagram of a circuit TFT, and FIG. 9B is a sectional configuration diagram taken along line FF ′ shown in FIG. As shown in FIG. 9A, this example has a configuration that can be suitably used when two circuit TFTs 80 and 81 are arranged adjacent to each other.
The circuit TFT 80 includes a semiconductor layer 800 having a rectangular shape in plan view, a gate electrode 810 disposed at the center of the semiconductor layer 800, a channel region 800a, and source regions 800b provided on both sides of the channel region 800a. And a drain region 800c. Then, as shown in FIG. 9B, the source region 800b and the source wiring 820 are electrically connected via two contact holes 830 provided through the insulating thin film 2 and the second interlayer insulating film 13. The drain region 800c and the drain wiring 840 are electrically connected through two contact holes 850.

  The circuit TFT 81 is disposed substantially parallel to the circuit TFT 81, and has a rectangular semiconductor layer 801 in plan view, a second gate electrode 811 disposed at the center of the semiconductor layer 801, and a channel region 801a. And a source region 801b and a drain region 801c formed on both sides thereof. As shown in FIG. 9B, the source region 801b and the source wiring 821 are electrically connected through two contact holes 831 provided through the insulating thin film 2 and the second interlayer insulating film 13. The drain region 801c and the drain wiring 841 are electrically connected through two contact holes 851.

  When two circuit TFTs are arranged adjacent to each other in this way, the gate of one circuit TFT 80 is constituted by the gate electrode 810 provided on the upper layer side of the semiconductor layer 800, and the other circuit TFT 81 is provided. Even if the distance between the TFTs 80 and 81 is shortened by configuring the second gate electrode 811 provided on the lower layer side of the semiconductor layer 800, the gate electrode 810 and the second gate electrode 811 are Since they are formed in different layers, the gate electrode can be arranged without being limited by the limit of workability. Therefore, if the circuit TFT having this configuration is employed, a peripheral circuit suitable for a high-definition liquid crystal device in which circuit TFTs are arranged at high density can be realized.

  In addition, the semiconductor layer 800 can have a two-layer structure in which a first polysilicon film and a second polysilicon film are stacked, similarly to the semiconductor layer 42 provided in the pixel region 41. In the semiconductor layer formed by using the manufacturing method according to the present invention, the difference in crystal grain size in the layer thickness direction is small, so that each gate electrode 810 like the circuit TFTs 80 and 81 is provided. , 811 are different in formation layer, and even when the semiconductor layer surfaces facing them are different, the gate electrodes 810 and 811 can obtain substantially the same voltage application effect.

  Further, as shown in FIG. 9B, the second gate electrode 811 of the circuit TFT 81 is formed in a layer between the base insulating film 11 and the first interlayer insulating film 12 on the substrate body 10a. In the same layer as the first gate wiring 15b provided in the pixel region 41, the same light shielding material is used. Therefore, when the circuit TFTs 80 and 81 having this configuration are manufactured, the second gate electrode 811 can be formed at the same time as the light shielding member 15 in the pixel region 41, and the degree of integration is increased without increasing the number of processes. Peripheral circuits can be formed.

  For example, the circuit TFT is used in the sampling switch 131 of the sampling circuit 201b shown in FIG. 2, the inverter (complementary TFT) of the latch circuit applied to the horizontal shift register 201a and the scanning line driving circuit 204, the transmission gate, and the like. Can be applied. By using the circuit TFT according to this embodiment, the TFT can be reduced in size and density, and the peripheral circuit can be highly integrated corresponding to the increase in the number of drive pixels due to the higher definition of the pixel. .

As described above in detail, in the liquid crystal device, in the image display region, the semiconductor layer 42 sandwiched between the first gate wiring 15b and the gate electrodes 32 and 33 is formed by the first polysilicon film 42a and the second polysilicon film. By adopting a laminated structure with the silicon film 42b, it is possible to control the crystal structure of the polysilicon films 42a and 42b so as to be optimized with respect to the gate electrode acting on each, and both sides sandwiching the channel region The TFT having the gate electrode provided thereon can sufficiently exhibit the electrical characteristics, and excellent pixel switching characteristics can be obtained.
In addition, since the capacitor electrode portion 15a and the first gate wiring 15b made of a light-shielding material are provided on the lower layer side of the semiconductor layer 42, the leakage current of the TFT 30 and the flat area of the storage capacitor 70 are reduced. Thus, the pixel area 41 can have a high aperture ratio.
On the other hand, in the peripheral circuit, the gate electrode can be formed on either the upper layer side or the lower layer side of the semiconductor layer, so that the circuit TFT can be reduced in size and increased in density. It is possible to realize a peripheral circuit that can sufficiently cope with the increase in the number of pins. Therefore, according to the liquid crystal device of this embodiment provided with the image display area and the peripheral circuit, it is possible to obtain a high-quality display even if the pixels are made high definition.

(Electronics)
FIG. 10 is a perspective view showing an example of an electronic apparatus according to the invention. A cellular phone 1300 shown in this figure includes the liquid crystal device of the above embodiment as a small-sized display portion 1301, and includes a plurality of operation buttons 1302, an earpiece 1303, and a mouthpiece 1304.

  The display device of each of the above embodiments is not limited to the mobile phone, but is an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type or a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook. , Calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, etc., can be suitably used as image display means, and any electronic device can display bright and high-definition. Yes.

2A is a plan view of a liquid crystal device, and FIG. FIG. 3 is a circuit configuration diagram of the liquid crystal device. FIG. 2 is a plan configuration diagram showing one pixel region. FIG. 4 is a cross-sectional configuration diagram taken along line A-A ′ of FIG. 3. FIG. 4 is a cross-sectional configuration diagram taken along line B-B ′ of FIG. 3. FIG. 4 is an enlarged cross-sectional configuration diagram in the vicinity of a semiconductor layer of a TFT according to an embodiment. Explanatory drawing which shows typically the crystal structure of a semiconductor layer. Explanatory drawing which shows the operation | movement of TFT typically. FIG. 2A is a plan configuration diagram (a) and a cross-sectional configuration diagram (b) of a circuit TFT. FIG. 11 is a perspective configuration diagram illustrating an example of an electronic device.

Explanation of symbols

  10 TFT array substrate, 20 counter substrate, 10a, 20a substrate body, 1a channel region, 3a second gate wiring (scanning line), 3b capacitance line (second capacitance electrode), 6a data line, 9 pixel electrode, 15 light shielding member , 15a capacitive electrode portion (first capacitive electrode), 15b first gate wiring (first gate electrode), 30 TFT (thin film transistor), 32, 33 gate electrode (second gate electrode), 41 pixel region, 42 semiconductor layer, 42a first polysilicon film, 42b second polysilicon film, 42c storage capacitor electrode (third capacitor electrode), 50 liquid crystal layer, 58 intermediate electrode layer, 70 storage capacitor.

Claims (10)

An electro-optical device including a transistor formed on a substrate,
The transistor opposes a semiconductor layer, a first gate electrode facing the one surface side of the channel region of the semiconductor layer via a first insulating film, and a second gate electrode facing the other surface side of the channel region. A second gate electrode,
The electro-optical device, wherein the semiconductor layer is a stacked film of a first semiconductor film facing the first gate electrode and a second semiconductor film facing the second gate electrode. An electro-optical device including a thin film transistor formed on a substrate,
The thin film transistor opposes a semiconductor layer, a first gate electrode facing the one surface side of the channel region of the semiconductor layer via a first insulating film, and a second gate electrode facing the other surface side of the channel region. A second gate electrode,
2. The electro-optical device according to claim 1, wherein the semiconductor layer is a stacked film of a first polysilicon film facing the first gate electrode and a second polysilicon film facing the second gate electrode. The thin film transistor has a structure in which the first gate electrode, the first insulating film, the semiconductor layer, the second insulating film, and the second gate electrode are sequentially stacked on a base;
3. The electro-optical device according to claim 2, wherein a film thickness of the first polysilicon film formed on the base side of the semiconductor layer is thicker than a film thickness of the second polysilicon film. A storage capacitor electrically connected to the thin film transistor;
The storage capacitor is formed in the same layer as the first capacitor electrode formed in the same layer as the first gate electrode, a second capacitor electrode formed in the same layer as the second gate electrode, and the semiconductor layer. The electro-optical device according to claim 1, further comprising a third capacitor electrode. A signal wiring electrically connected to the thin film transistor and extending on the substrate;
A part of the first capacitor electrode and a part of the third capacitor electrode are arranged so as to overlap the signal wiring in a planar manner, and form a part of the storage capacitor at the position. The electro-optical device according to claim 4.   The plurality of channel regions are formed in a semiconductor layer of the thin film transistor, and the first gate electrode and the second gate electrode are provided corresponding to each channel region. The electro-optical device according to any one of the above. A semiconductor layer; a first gate electrode opposed to one surface side of the channel region of the semiconductor layer via a first insulating film; and a second gate electrode opposed to the other surface side of the channel region via a second insulating film. And
The thin film transistor according to claim 1, wherein the semiconductor layer is a laminated film of a first polysilicon film facing the first gate electrode and a second polysilicon film facing the second gate electrode. Forming a first gate electrode by patterning a metal film on a substrate;
Forming a first insulating film covering the first gate electrode;
Forming a first amorphous silicon film on the first insulating film and crystallizing the first amorphous silicon film to form a first polysilicon film;
Forming a second amorphous silicon layer on the first polysilicon film and crystallizing the second amorphous silicon film to form a second polysilicon film;
Patterning a laminated film of the first polysilicon film and the second polysilicon film to form a semiconductor layer having a predetermined shape;
Forming a second insulating film so as to cover the semiconductor layer;
Forming a second gate electrode at a position overlapping with the first gate electrode by patterning a metal film on the second insulating film. .   9. The method of manufacturing an electro-optical device according to claim 8, wherein the amorphous silicon film is crystallized by irradiating the amorphous silicon film with a laser.   An electronic apparatus comprising the electro-optical device according to claim 1.

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