JP2006234610A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate a DC test of an output buffer by suppressing increase in cell area or increase in delay time to the utmost. <P>SOLUTION: The semiconductor integrated circuit is provided with the output buffers 21, 22, and 23A to be subjected to the DC test; FF circuits 11-13 connected to inputs of the output buffers, directly or via combination logic circuits 41 and 42; and selectors 51-53 connecting the plurality of FF circuits so that a shift register is constituted. During the DC test, the shift register is constituted by the FF circuits by means of the selectors 51-53 so that test pattern data can be inputted to the shift register. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit capable of performing a DC test of an output buffer while suppressing an increase in chip area and an increase in delay time as much as possible.

  In the DC test of the output buffer of the semiconductor integrated circuit, H level or L level data is input to the input side of the output buffer, and the H level and L level (VOH / L) voltages appearing on the output side are within a predetermined range. It is a test to determine whether or not it is within. When a test circuit that can be used for such a DC test is not incorporated in the semiconductor integrated circuit, conventionally, the following method has been used.

  In the first method, taking into account a user function incorporated in the semiconductor integrated circuit, test pattern data that changes the output voltage of the output buffer from L to H and from H to L is input from the outside. This is a technique for performing a DC test.

  In the second method, a selector (MUX) that switches between power supply voltage or ground is connected to the input side of each output buffer so that the output voltage of the output buffer changes from L → H and H → L. Or by directly inputting H level and L level data from the outside and changing the output voltage of each output buffer from L to H and H to L, and performing a DC test.

  The third method is a method of performing a DC test by controlling the output buffer in the JTAG test mode by using a JTAG boundary scan register. JTAG is standardized as IEEE 1149.1. A DC test method using a JTAG boundary scan register is described in, for example, Patent Documents 1 and 2.

JP 2000-314765 A JP 2002-131381 A

  However, the first method, when creating test pattern data using a user function, has a problem that the pattern becomes complicated or long, and the pattern generation itself requires a great amount of man-hours. .

  In addition, since the second method adds a selector specially, in addition to the problem that the cell area near the output buffer increases, a delay is added to the output system, which is preferable from the viewpoint of timing convergence and speedup. Absent. In addition, since switching of multiple output buffers (H / L level change) occurs simultaneously during the DC test, from the viewpoint of evaluating the performance of the output buffer, other fault factors such as noise are included, and a correct test is performed. It is hard to be done.

  Furthermore, the third method has no problem when a boundary scan register is originally incorporated, but this cannot be used in a semiconductor integrated circuit that is not a JTAG-equipped project, and is not available in a semiconductor integrated circuit having a high-speed output buffer. Since the scan register is not added, it is not perfect.

  An object of the present invention is to provide a semiconductor integrated circuit in which an increase in cell area and an increase in delay time are suppressed as much as possible, and an output buffer DC test can be easily performed.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention includes a plurality of output buffers, a plurality of FF circuits that are directly connected to inputs of the output buffers or connected through combinational logic circuits, and the plurality of FF circuits. And connecting means for connecting to form a shift register using only the FF circuit.

  Here, needless to say, the output buffer includes an output buffer included in the bidirectional input / output buffer.

  Here, another logic circuit that can change the output of the combinational logic circuit between the FF circuit and the output buffer to a desired logic value may be connected.

  As described above, according to the present invention, since the FF circuit that constitutes the shift register during the DC test of the output buffer can be used as it is in the data output path to the output buffer, the increase in cell area can be suppressed. In addition, an increase in delay time can be suppressed, and the invention can be applied to a semiconductor integrated circuit that does not support JTAG boundary scan. In addition, if test pattern data is input to the shift register, it can be output to each output buffer with a predetermined time lag, making it easy to perform DC testing of the output buffer, and controlling the number of output buffers that are switched at the same time. It becomes possible. Further, even when an FF circuit and connection means are added, they are few, and wiring resources are also little.

  Generally, very few semiconductor integrated circuits are composed of only combinational logic circuits without using FF (flip-flop) circuits, and most semiconductor integrated circuits use FF circuits. A scan circuit is configured using this FF circuit, and failure detection (stuck-at-fault detection) is performed by a test method called internal scan.

  Therefore, in the present invention, the FF circuit is used exclusively for the DC test of the output buffer. In other words, the FF circuit included in the data output path to the output buffer is used exclusively for the DC test of the output buffer, so that the DC test of the output buffer is performed while preventing an increase in cell area and an increase in delay time. Like that.

  For this purpose, a shift register as a scan chain circuit is configured by an FF circuit directly connected to the output buffer or an FF circuit indirectly connected to the output buffer via a combinational logic circuit. Can be controlled from the outside by a connecting means such as a selector, and arbitrary data is set in each FF circuit by the shift register, so that the output voltages of a plurality of output buffers are changed from H → L and L → H. Control and make DC test feasible.

  According to the present invention, since an existing FF circuit is used, an increase in cell area is suppressed, and a delay time of an output system is not increased. Further, compared with the case where an internal scan circuit or JTAG is specially added, the increase in wiring resources is small. When the DC test circuit according to the present invention is not incorporated, it takes much time and time to execute the DC test, so that the burden of increasing the wiring resources to this extent is not great. In addition, the number of output buffers that are simultaneously switched can be controlled, and an output buffer that does not support JTAG boundary scan can be used. Although it can be used in combination with an existing internal scan circuit, in this case, it becomes easier to create test pattern data if the DC test portion is made independent.

  A portion of the semiconductor integrated circuit near the output buffer is, for example, as shown in FIG. Reference numerals 11 to 13 denote FF circuits, 21 and 22 denote output buffers, 23 denotes input / output buffers, 31 to 33 denote pads, and 41 and 42 denote combinational logic circuits (not including FF circuits). The input / output buffer 23 includes an output buffer 23A and an input buffer 23B. In this way, in the vicinity of the output buffer, the output buffer 21 is directly connected to the output side of the FF circuit 11, or the output buffer 22 is connected to the output side of the FF circuit 12 via the combinational logic circuit 41. The output side of the FF circuit 13 is connected to the output buffer 23A of the input / output buffer 23 via the combinational logic circuit 42.

  Therefore, in the first embodiment, as shown in FIG. 1, the selectors 51 to 53 are used as connection means, and a part of the output of the FF circuit is input to the selector. In this way, a part of wiring is added, and the FF circuits 11 to 13 constitute a shift register as a scan chain circuit. As for the FF circuit, if the FF circuit that is not directly / indirectly connected to the output buffer is also included in the scan chain circuit, the DC test pattern becomes long and complicated, so only the FF circuit connected to the output buffer is included. Are included in the scan chain circuit.

  With the configuration described above, during the DC test of the output buffers 31 to 33, the control terminal S of the selectors 51 to 53 is controlled from the outside so that the input terminal S1 is connected to the output side, and the FF circuits 11 to 11 are connected. After the shift register is configured by 13, the test pattern data may be input. At this time, the output buffer 23A is controlled to be enabled for the input / output buffer 23. If the test pattern data is input to the input terminal S1 of the selector 51, the test pattern data is shifted and input to the output buffers 21, 22, 23A according to the input timing of the clock CK input to the FF circuits 11-13. By measuring the H level and L level voltages (VOH / L) of the pads 31 to 33, the DC tests of the output buffers 21, 22, and 23A can be executed.

  When the FF circuit and the output buffer are not in a 1: 1 connection relationship, for example, as shown in FIG. 2, a logic circuit 43 that receives the outputs of the two FF circuits 14 and 15 (an example of an AND gate is shown here) .) Is connected to the output buffer 24, the test pattern data is shifted and input to the FF circuits 14 and 15 by the selectors 54 and 55, and the outputs of the FF circuits 14 and 15 are input to the logic circuit 43. The processed logic value is input to the output buffer 24, and the H level and L level voltages (VOH / L) appearing on the pad 34 are measured. In this case, if test pattern data corresponding to the type of the logic circuit 43 is input, the H level and L level voltages (VOH / L) can be reliably output to the pad 34.

  When a combinational logic circuit is interposed between the FF circuit and the output buffer and it is difficult to control the logic circuit, for example, the output of the output buffer is H level even if various data set in the FF circuit are tried. If there is no change from the above, a scan chain circuit as shown in FIG. 3 is configured. That is, in addition to the FF circuit 16 on the input side of the combinational logic circuit 44 in question, a FF circuit 17 is newly added, a selector 57 is added in addition to the selector 56 provided in relation to the FF circuit 16, and the combinational logic is further added. A logic circuit (in this case, an AND gate) 45 for inputting the output of the circuit 44 and the output of the additional FF circuit 17 is added, and the output of the logic circuit 45 is connected to the input of the output buffer 25 to be tested. Is connected to the pad 35.

  In this way, when the output of the combinational logic circuit 44 does not change from the H level, the output of the logic circuit 45 is changed between the H level and the L level by changing the test pattern data between the H level and the L level. Thus, the DC test of the output buffer 25 can be executed.

  In the third embodiment, since the FF circuit 17, the selector 57, the logic circuit 45, and the like are newly added compared to the first and second embodiments, the cell area occupied in the test circuit is increased. Compared with the case where the test pattern data is generated by analyzing the logic of the circuit 44, the number of steps is reduced. The logic circuit 45 may be an OR gate or other appropriate logic gate in accordance with the combinational logic circuit 44. The test pattern data to be input to the additional selector 57 may be determined according to the combinational logic circuit 44.

1 is a circuit diagram in the vicinity of an output buffer according to a first embodiment of a semiconductor integrated circuit of the present invention. FIG. It is a circuit diagram of the vicinity of the output buffer of Example 2 of the semiconductor integrated circuit of the present invention. It is a circuit diagram of the vicinity of the output buffer of Example 3 of the semiconductor integrated circuit of the present invention. FIG. 6 is a circuit diagram in the vicinity of an output buffer of a general semiconductor integrated circuit.

Explanation of symbols

11-17: FF circuits 21, 22, 23A, 24, 25: output buffers 31-35: pads 41-45: logic circuits 51-57: selectors

Claims (2)

  A plurality of output buffers, a plurality of FF circuits that are directly connected to inputs of the output buffers or connected through combinational logic circuits, and a shift register that uses only the plurality of FF circuits are connected. A semiconductor integrated circuit comprising a connecting means. The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit, wherein another logic circuit capable of changing the output of the combinational logic circuit between the FF circuit and the output buffer to a desired logic value is connected.

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