JP2006228833A - Ic chip with through-electrode - Google Patents

Ic chip with through-electrode Download PDF

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JP2006228833A
JP2006228833A JP2005038272A JP2005038272A JP2006228833A JP 2006228833 A JP2006228833 A JP 2006228833A JP 2005038272 A JP2005038272 A JP 2005038272A JP 2005038272 A JP2005038272 A JP 2005038272A JP 2006228833 A JP2006228833 A JP 2006228833A
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electrode
chip
dicing tape
protruding electrode
protruding
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Inventor
Taihei Sugita
大平 杉田
Manabu Asada
学 浅田
Munehiro Hatai
宗宏 畠井
Masateru Fukuoka
正輝 福岡
Satoshi Hayashi
聡史 林
Kazuhiro Shimomura
和弘 下村
Giichi Kitajima
義一 北島
Yasuhiko Oyama
康彦 大山
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Sekisui Chemical Co Ltd
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Sekisui Chemical Co Ltd
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Priority to JP2005038272A priority Critical patent/JP2006228833A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an IC chip with a through-electrode which can be easily picked up without being damaged even if the conventional energy beam-hardening dicing tape is used. <P>SOLUTION: The IC chip with a through-hole has a salient electrode, and the salient electrode has a tapered shape. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、従来のエネルギー線硬化タイプのダイシングテープを用いた場合でも、容易にかつ破損することなくピックアップすることのできる貫通電極付きＩＣチップに関する。 The present invention relates to an IC chip with a through-hole electrode that can be picked up easily and without being damaged even when a conventional energy ray curable dicing tape is used.

従来の電子回路の製造方法では、基板上に設置したＩＣチップをワイヤボンディングにより導電接続することが行われていた。近年、電子回路の大容量化、高機能化に対応して、複数のＩＣチップを立体的に積層した積層回路の開発が進んでいる。このような積層回路においては、従来はＩＣチップの導電接続をワイヤボンディングにより行うことが一般的であったが、近年の小型化・高機能化の必要性より、ワイヤボンディングをすることなく、ＩＣチップに貫通電極を設けて、直接ＩＣチップ間に上下の導電接続する方法が効果的な手法として開発されている。 In the conventional electronic circuit manufacturing method, an IC chip placed on a substrate is conductively connected by wire bonding. In recent years, development of a laminated circuit in which a plurality of IC chips are three-dimensionally laminated has been advanced in response to the increase in capacity and functionality of electronic circuits. Conventionally, in such a laminated circuit, the conductive connection of the IC chip is generally performed by wire bonding. However, due to the recent need for miniaturization and high functionality, the IC chip can be connected without wire bonding. A method of providing a through electrode on a chip and directly connecting the upper and lower conductive parts between IC chips has been developed as an effective technique.

このような貫通電極付きＩＣチップの製造方法としては、例えば、半導体ウエハの所定の位置にプラズマ等により貫通孔を設け、この貫通孔に銅等の導電体を流し込んだ後、エッチング等を施して半導体ウエハの表面に回路と貫通電極とを設ける方法等が挙げられる。回路及び貫通電極が設けられた半導体ウエハは、常法によりダイシングされて、個々の貫通電極付きＩＣチップが得られる。 As a method of manufacturing such an IC chip with a through electrode, for example, a through hole is formed in a predetermined position of a semiconductor wafer by plasma or the like, and a conductor such as copper is poured into the through hole, and then etching or the like is performed. Examples thereof include a method of providing a circuit and a through electrode on the surface of a semiconductor wafer. A semiconductor wafer provided with a circuit and a through electrode is diced by a conventional method to obtain individual IC chips with through electrodes.

通常のダイシング工程においては、半導体ウエハは、ダイシングテープと呼ばれる粘着テープに貼付して固定した状態でダイシングされて、個々のＩＣチップに成形される。ダイシングして得られた個々のＩＣチップは、通常、ダイシングテープの基材側よりニードルで突き上げる等してダイシングテープから剥離され、ピックアップされてダイパッド上に固定される。 In a normal dicing process, a semiconductor wafer is diced in a state of being stuck and fixed to an adhesive tape called a dicing tape, and is formed into individual IC chips. Individual IC chips obtained by dicing are usually peeled off from the dicing tape by being pushed up with a needle from the substrate side of the dicing tape, picked up, and fixed on the die pad.

ダイシングテープとしては、紫外線等のエネルギー線を照射することにより硬化する粘着剤層を有するものが用いられる（例えば、特許文献１等）。このようなダイシングテープを用いれば、ダイシング時には半導体ウエハが揺動したりしないにように充分に高い接着強度で半導体ウエハを固定できる一方、ピックアップに先立って粘着剤層を硬化させて粘着力を低下させることにより、より容易にＩＣチップをダイシングテープから剥離し、ピックアップが可能であるとされている。
しかしながら、回路及び貫通電極が設けられた半導体ウエハを従来のエネルギー線硬化タイプのダイシングテープに貼付してダイシングを行った場合、得られたＩＣチップをピックアップできなかったり、ピックアップ時に破損してしまったりする等の問題点があった。
特開平８−２３９６３６号公報 As the dicing tape, one having an adhesive layer that is cured by irradiation with energy rays such as ultraviolet rays (for example, Patent Document 1) is used. If such a dicing tape is used, the semiconductor wafer can be fixed with a sufficiently high adhesive strength so that the semiconductor wafer does not swing during dicing, while the adhesive layer is cured prior to pick-up to reduce the adhesive strength. By doing so, the IC chip is more easily peeled off from the dicing tape, and pickup is possible.
However, when a semiconductor wafer provided with a circuit and a through electrode is attached to a conventional energy ray curable dicing tape and then diced, the obtained IC chip cannot be picked up or damaged during picking up. There were problems such as.
JP-A-8-239636

本発明は、上記現状に鑑み、従来のエネルギー線硬化タイプのダイシングテープを用いた場合でも、容易にかつ破損することなくピックアップすることのできる貫通電極付きＩＣチップを提供することを目的とする。 An object of the present invention is to provide an IC chip with a through electrode that can be picked up easily and without being damaged even when a conventional energy ray curable dicing tape is used.

本発明１は、突起電極を有する貫通電極付きＩＣチップであって、前記突起電極はテーパー状の形状を有する貫通電極付きＩＣチップである。
本発明２は、突起電極を有する貫通電極付きＩＣチップであって、前記突起電極は粗面処
理が施されている貫通電極付きＩＣチップである。
本発明３は、突起電極を有する貫通電極付きＩＣチップであって、前記突起電極は鏡面処理が施されている貫通電極付きＩＣチップである。
以下に本発明を詳述する。 The present invention 1 is an IC chip with a through electrode having a protruding electrode, and the protruding electrode is an IC chip with a through electrode having a tapered shape.
The present invention 2 is an IC chip with a through electrode having a protruding electrode, and the protruding electrode is an IC chip with a through electrode subjected to a rough surface treatment.
The present invention 3 is an IC chip with a through electrode having a protruding electrode, and the protruding electrode is an IC chip with a through electrode subjected to a mirror finish.
The present invention is described in detail below.

貫通電極が設けられた半導体ウエハでは、一方又は両方の面に貫通電極が１０〜３０μｍ程度の高さに突出して突起電極が形成されている。この突起電極は、ＩＣチップとしたときに、基板や他のＩＣチップと導電接続するためのバンプの役割を果たすものである。このような突起電極を有する半導体ウエハにダイシングテープを貼付した場合、ダイシングテープの粘着剤層が突起電極に追従して、ここに引っかかりが生じてしまうと考えられる。ダイシング後に個々のＩＣチップをピックアップする際にこのような引っかかりがあると、たとえ粘着剤層を硬化させて粘着力を低下させた場合であっても容易にはピックアップすることができず、無理に剥がそうとすると、貫通電極自体を傷つけたり破壊したりしてしまったりすることがある。
本発明者らは、鋭意検討の結果、突起電極の形状をテーパー状にしたり、突起電極に粗面処理又は鏡面処理を施したりすることにより、このような引っかかりの発生を防止し、容易にかつ破損することなくピックアップすることができることを見出し、本発明を完成するに至った。 In a semiconductor wafer provided with a through electrode, the through electrode protrudes to a height of about 10 to 30 μm on one or both surfaces to form a protruding electrode. When the protruding electrode is used as an IC chip, it functions as a bump for conductive connection with the substrate or another IC chip. When a dicing tape is affixed to a semiconductor wafer having such protruding electrodes, it is considered that the adhesive layer of the dicing tape follows the protruding electrodes and gets caught here. If there is such a catch when picking up individual IC chips after dicing, even if the adhesive layer is hardened and the adhesive strength is reduced, it cannot be picked up easily, forcibly. If it is peeled off, the through electrode itself may be damaged or destroyed.
As a result of intensive studies, the present inventors have prevented the occurrence of such catches by making the shape of the protruding electrode tapered, or by subjecting the protruding electrode to a rough surface treatment or a mirror surface treatment. The present inventors have found that the pickup can be performed without breakage and have completed the present invention.

本発明１の貫通電極付きＩＣチップは、突起電極を有するものであって、上記突起電極はテーパー状の形状を有するものである。
本明細書においてテーパー状とは、突起電極において、ＩＣチップの表面に近い部分（根元部分）よりも遠い部分（先端部分）のほうの径が小さくなっている形状を意味する。上記テーパー状の突起電極としては、具体的には例えば、図１に示したもの等が挙げられるが、これらに限定されるものではない。 The IC chip with a through electrode according to the first aspect of the invention has a protruding electrode, and the protruding electrode has a tapered shape.
In the present specification, the taper shape means a shape in which the diameter of a portion (tip portion) farther from the portion near the surface of the IC chip (base portion) is smaller in the protruding electrode. Specific examples of the tapered protruding electrode include, but are not limited to, those shown in FIG.

テーパー状の突起電極とすることにより、ダイシングテープを剥離する際に引っかかりが生じるのを防止することができる。これは、テーパー状とすることにより粘着剤層との接触面積が減少すること、及び、ダイシングテープを剥離する際の剥離の角度が緩やかになること等によるものと考えられる。 By using the tapered protruding electrode, it is possible to prevent the occurrence of catching when the dicing tape is peeled off. This is considered to be because the contact area with the pressure-sensitive adhesive layer is reduced by making the taper shape, and the angle of peeling when peeling the dicing tape becomes gentle.

上記テーパー状の突起電極を形成する方法としては特に限定されず、例えば、貫通電極の形成時にテーパー状の突起電極を形成させる方法、常法により突起電極を形成した後にエッチング等の方法により突起の形状を整える方法等が挙げられる。 The method of forming the tapered protruding electrode is not particularly limited. For example, the method of forming the tapered protruding electrode when forming the through electrode, the method of forming the protruding electrode after forming the protruding electrode by a conventional method, and the like. For example, a method of adjusting the shape.

図２に、貫通電極の形成時にテーパー状の突起電極を形成させる方法の一例を示した。
図２に示した方法では、まず、半導体ウエハ（ＩＣチップ）に第１のレーザー照射を行い、ウエハの中程までに孔を開ける（図２Ａ、Ｂ）。次いで、第１のレーザー照射よりも径を絞った第２のレーザー照射を行う（図２Ｃ）。これにより、ウエハにはテーパー状の孔が形成される（図２Ｄ）。この孔に銅等の導電体を流し込んだ後（図２Ｅ）、片面にエッチングを施せば、テーパー状の突起電極を有するウエハが得られる（図２Ｆ）。 FIG. 2 shows an example of a method for forming a tapered protruding electrode when forming the through electrode.
In the method shown in FIG. 2, first, a semiconductor wafer (IC chip) is irradiated with a first laser, and a hole is formed in the middle of the wafer (FIGS. 2A and 2B). Next, a second laser irradiation with a diameter smaller than that of the first laser irradiation is performed (FIG. 2C). Thereby, a tapered hole is formed in the wafer (FIG. 2D). After pouring a conductor such as copper into this hole (FIG. 2E), if one surface is etched, a wafer having a tapered protruding electrode can be obtained (FIG. 2F).

本発明２の貫通電極付きＩＣチップでは、上記突起電極は粗面処理が施されており、また、本発明３の貫通電極付きＩＣチップでは、上記突起電極は鏡面処理が施されている。粗面処理と鏡面処理とは相反するものであるが、用いるダイシングテープの粘着剤層の状態によって選択することにより、同様に剥離時の引っかかりの発生を抑え、容易にかつ破損することなくピックアップできるという効果が得られる。
即ち、ダイシングテープの粘着剤層が比較的高粘度のものである場合には、粗面処理が施された本発明２の貫通電極付きＩＣチップが有効である。これは、高粘度の粘着剤層は凹凸追従性に劣ることから、粗面処理が施された突起電極の表面には充分には追従せず、突
起電極と粘着剤層との接触面積が小さくなる結果、引っかかりが生じにくくなるためと考えられる。
ダイシングテープの粘着剤層が比較的低粘度のものである場合には、鏡面処理が施された本発明３の貫通電極付きＩＣチップが有効である。これは、低粘度の粘着剤層は凹凸追従性が高く突起電極の表面に完全に追従するが、鏡面処理を施すことにより、突起電極と粘着剤層との摩擦が小さくなる結果、引っかかりが生じにくくなるためと考えられる。 In the IC chip with a through electrode of the present invention 2, the protruding electrode is subjected to a rough surface treatment, and in the IC chip with a through electrode of the present invention 3, the protruding electrode is subjected to a mirror surface treatment. Rough surface treatment and mirror surface treatment are contradictory, but by selecting according to the state of the pressure-sensitive adhesive layer of the dicing tape to be used, the occurrence of catching at the time of peeling can be similarly suppressed and pickup can be performed easily and without being damaged. The effect is obtained.
In other words, when the pressure-sensitive adhesive layer of the dicing tape has a relatively high viscosity, the IC chip with a through electrode of the present invention 2 subjected to the rough surface treatment is effective. This is because the high-viscosity pressure-sensitive adhesive layer is inferior in unevenness followability, so it does not sufficiently follow the surface of the roughened bump electrode, and the contact area between the bump electrode and the pressure-sensitive adhesive layer is small. As a result, it is thought that it becomes difficult to cause catching.
When the pressure-sensitive adhesive layer of the dicing tape has a relatively low viscosity, the IC chip with a through electrode of the present invention 3 that has been subjected to a mirror finish is effective. This is because the low-viscosity pressure-sensitive adhesive layer has high unevenness-following ability and follows the surface of the protruding electrode completely, but by applying a mirror finish, the friction between the protruding electrode and the pressure-sensitive adhesive layer is reduced, resulting in catching. This is thought to be difficult.

本明細書において粗面とは、ＪＩＳ Ｂ ０６０１に準拠した十点平均表面粗さ（基準長さ２．５ｍｍ）Ｒｚが３００ｎｍ以上であることを意味し、鏡面とは、ＪＩＳ Ｂ ０６０１に準拠した十点平均表面粗さ（基準長さ２．５ｍｍ）Ｒｚが５０ｎｍ以下であることを意味する。 In this specification, the rough surface means that the ten-point average surface roughness (reference length 2.5 mm) Rz conforming to JIS B 0601 is 300 nm or more, and the mirror surface conforms to JIS B 0601. Mean 10-point surface roughness (reference length 2.5 mm) Rz is 50 nm or less.

上記粗面処理としては特に限定されず、例えば、エッチング処理、サンドブラスト処理等の従来公知の方法が挙げられる。また、表面に微小突起を付着させる処理も粗面処理に含まれる。
上記鏡面処理としては特に限定されず、例えば、バフ研磨等の機械的研磨や、浸漬式電解研磨、電解砥粒研磨、高速電解研磨等の電解研磨等の従来公知の方法が挙げられる。 The rough surface treatment is not particularly limited, and examples thereof include conventionally known methods such as etching treatment and sand blast treatment. Also, the rough surface treatment includes a process of attaching minute protrusions to the surface.
The mirror surface treatment is not particularly limited, and examples thereof include conventionally known methods such as mechanical polishing such as buff polishing, electrolytic polishing such as immersion electrolytic polishing, electrolytic abrasive polishing, and high-speed electrolytic polishing.

本発明１と本発明２、３とは、それぞれ単独で行ってもよいが、本発明１と本発明２、又は、本発明１と本発明３とを組み合わせることにより、より高い効果が得られる。 The present invention 1 and the present invention 2, 3 may be performed independently, but by combining the present invention 1 and the present invention 2, or the present invention 1 and the present invention 3, higher effects can be obtained. .

本発明によれば、従来のエネルギー線硬化タイプのダイシングテープを用いた場合でも、容易にかつ破損することなくピックアップすることのできる貫通電極付きＩＣチップを提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, even when the conventional energy ray hardening type dicing tape is used, the IC chip with a through-hole electrode which can be picked up easily and without being damaged can be provided.

以下に実施例を掲げて本発明を更に詳しく説明するが、本発明はこれら実施例のみに限定されるものではない。 Hereinafter, the present invention will be described in more detail with reference to examples. However, the present invention is not limited to these examples.

（実施例１）
Ｓｉウエハに口径１００μｍのレーザーを照射し、ウエハの厚さ方向半ばにまで孔を開けた後、レーザーの口径を５０μｍに絞って照射して貫通孔を開けた。この貫通孔にめっきを充填することにより電極を形成した。次いで、回路が形成されている面とは反対側の面をフッ硝酸によりウェットエッチングした。これにより、直径１５０ｍｍ、厚さ５０μｍであり、図３に示した形状の２０μｍの高さの突起電極が４００μｍの間隔で縦横１２５個並んで形成された、図５のように配置された貫通電極を有する半導体ウエハを得た。 Example 1
The Si wafer was irradiated with a laser having a diameter of 100 μm and a hole was drilled to the middle of the wafer thickness direction, and then the laser was narrowed to a diameter of 50 μm and irradiated to form a through hole. An electrode was formed by filling the through hole with plating. Next, the surface opposite to the surface on which the circuit was formed was wet etched with hydrofluoric acid. As a result, through electrodes arranged as shown in FIG. 5, each having a diameter of 150 mm and a thickness of 50 μm, and having 125 μm high and 20 μm high protruding electrodes arranged side by side at 400 μm intervals. A semiconductor wafer having

（実施例２）
実施例１で得られた半導体ウエハの突起した貫通電極に対して、各貫通電極に対して、エアーブラスト方式にてサンドブラストを行い、突起電極の表面に粗面処理を施した。 (Example 2)
With respect to the projecting through electrodes of the semiconductor wafer obtained in Example 1, each through electrode was sandblasted by an air blast method, and the surface of the projecting electrode was subjected to a rough surface treatment.

（実施例３）
実施例１で得られた半導体ウエハを、電解研磨法により金属突起表面だけを選択的に処理し、突起電極の表面に鏡面処理を施した。 (Example 3)
The semiconductor wafer obtained in Example 1 was selectively treated only on the surface of the metal protrusions by the electrolytic polishing method, and the surface of the protrusion electrodes was subjected to a mirror surface treatment.

（比較例１）
Ｓｉウエハにドライエッチングを施してバイアホールを開けた後、めっきを充填することにより電極を形成した。次いで、回路が形成されている面とは反対側の面をフッ硝酸によりウェットエッチングした。これにより、直径１５０ｍｍ、厚さ５０μｍであり、図４に
示した形状の２０μｍの高さの突起部分が４００μｍの間隔で縦横１２５個並んで形成された、図５のように配置された貫通電極を有する半導体ウエハを得た。 (Comparative Example 1)
After dry etching was performed on the Si wafer to open a via hole, an electrode was formed by filling with plating. Next, the surface opposite to the surface on which the circuit was formed was wet etched with hydrofluoric acid. As a result, through-electrodes arranged as shown in FIG. 5, each having a diameter of 150 mm and a thickness of 50 μm, and 125 protrusions 20 μm high in the shape shown in FIG. A semiconductor wafer having

（評価）
粘着剤層の特性としてゲル分率及び剪断弾性率をそれぞれ、８０％、１×１０６ＰａであるダイシングテープＡと、５０％、５×１０５ＰａであるダイシングテープＢとの２種類のＵＶ硬化型ダイシングテープを準備した。
各々のダイシングテープを実施例１〜３及び比較例１で作製した貫通電極を有する半導体ウエハに貼付したうえでダイシング装置に取りつけダイシングを行った。いずれの場合も、特に問題なくダイシングすることができた。
ダイシング後、所定の紫外線照射によりＵＶ硬化させた後、切断された個々の貫通電極付きＩＣチップを吸引しながら真上に引っ張り上げるようにしてピックアップした。このときピックアップに要した力を測定し、これを剥離強度とした。ピックアップを各々１０個行い、その平均の剥離強度を算出した。
結果を表１に示した。 (Evaluation)
As the characteristics of the pressure-sensitive adhesive layer, two types of UVs are used: a dicing tape A having a gel fraction and a shear elastic modulus of 80% and 1 × 10 6 Pa, and a dicing tape B having 50% and 5 × 10 5 Pa, respectively. A curable dicing tape was prepared.
Each dicing tape was affixed to a semiconductor wafer having through electrodes produced in Examples 1 to 3 and Comparative Example 1, and then attached to a dicing apparatus for dicing. In either case, dicing could be performed without any particular problem.
After dicing, UV curing was performed by irradiation with a predetermined ultraviolet ray, and each IC chip with through electrodes cut was picked up while being pulled up while being sucked. At this time, the force required for the pickup was measured, and this was taken as the peel strength. Ten pickups were performed for each, and the average peel strength was calculated.
The results are shown in Table 1.

Figure 2006228833
Figure 2006228833

本発明によれば、従来のエネルギー線硬化タイプのダイシングテープを用いた場合でも、容易にかつ破損することなくピックアップすることのできる貫通電極付きＩＣチップを提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, even when the conventional energy ray hardening type dicing tape is used, the IC chip with a through-hole electrode which can be picked up easily and without being damaged can be provided.

テーパー状の突起電極の形状の例を示す模式図である。It is a schematic diagram which shows the example of the shape of a taper-shaped projection electrode. 貫通電極の形成時にテーパー状の突起電極を形成させる方法の一例を示す模式図である。It is a schematic diagram which shows an example of the method of forming a taper-shaped projection electrode at the time of formation of a penetration electrode. 実施例１で作製した半導体ウエハの突起電極の形状を示す模式図である。3 is a schematic diagram showing the shape of a protruding electrode of a semiconductor wafer manufactured in Example 1. FIG. 比較例１で作製した半導体ウエハの突起電極の形状を示す模式図である。6 is a schematic diagram showing the shape of a protruding electrode of a semiconductor wafer manufactured in Comparative Example 1. FIG. 実施例１、比較例１で作製した半導体ウエハの突起電極の配置を示す模式図である。6 is a schematic diagram showing the arrangement of protruding electrodes of a semiconductor wafer manufactured in Example 1 and Comparative Example 1. FIG.

Claims (3)

突起電極を有する貫通電極付きＩＣチップであって、前記突起電極はテーパー状の形状を有することを特徴とする貫通電極付きＩＣチップ。 An IC chip with a through electrode having a protruding electrode, wherein the protruding electrode has a tapered shape. 突起電極を有する貫通電極付きＩＣチップであって、前記突起電極は粗面処理が施されていることを特徴とする貫通電極付きＩＣチップ。 An IC chip with a through electrode having a protruding electrode, wherein the protruding electrode is roughened. 突起電極を有する貫通電極付きＩＣチップであって、前記突起電極は鏡面処理が施されていることを特徴とする貫通電極付きＩＣチップ。 An IC chip with a through electrode having a protruding electrode, wherein the protruding electrode is mirror-finished.
JP2005038272A 2005-02-15 2005-02-15 Ic chip with through-electrode Pending JP2006228833A (en)

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