JP2006228291A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress deterioration due to a load on a nonvolatile memory and increase the frequency of access to a memory cell as the result suppression, in a nonvolatile memory performing destructive read out using a ferroelectric capacitor. <P>SOLUTION: In a nonvolatile semiconductor memory device having the nonvolatile memory cell using the ferroelectric capacitor and performing a destructive read out operation and rewriting operation after that, the nonvolatile memory is connected selectively to a bit line by a switching element, after destructive read out operation without rewriting operation is repeated several times for the nonvolatile memory in a state the nonvolatile memory is electrically separated from the bit line by the switching element by an external signal, the rewriting operation is performed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile memory using a ferroelectric capacitor.

  In recent years, ferroelectrics have been used as storage elements as one of the nonvolatile semiconductor memories that are superior in characteristics such as the number of rewrites, access speed, and power consumption compared to conventional rewritable nonvolatile semiconductor memory devices such as flash memory and EEPROM. Ferroelectric memories (FeRAM) using capacitors have been developed by various companies in recent years, but in recent years, miniaturization technology and reliability technology have advanced rapidly, and small fields such as IC cards and tags have small bit capacities. However, the market is expanding. Due to its excellent characteristics, it is expected that the need for ferroelectric memories will continue to increase, especially in portable information devices.

  However, in the present situation, it is never the case that the level has been sufficiently satisfied in the future for all the characteristics demanded by the market. In particular, the number of times of rewriting or reading is currently guaranteed to be about 1E12 times, and the value is not far from that of a semiconductor memory such as a DRAM or an SRAM that achieves an infinite number of accesses.

  In such a ferroelectric memory, data recording is performed by utilizing the property of being polarized in two different polarities depending on the direction of the electric field applied to both electrodes of the ferroelectric capacitor. In addition, the data rewrite operation is performed by applying a new electric field between both electrodes of the ferroelectric capacitor. In this case, polarization inversion is always performed, and the number of data rewrites increases beyond the capability. As a result, the characteristics of the ferroelectric capacitor deteriorate.

  In the data read operation, since the data read operation is destructive read, it is necessary to rewrite the same data. When reading “1” (high) data accompanied by the rewrite, Similar to the data rewrite operation, there arises a problem of deterioration of characteristics of the ferroelectric capacitor.

  Regarding a similar problem, as a means for guaranteeing stored data, a means for suppressing capacitor deterioration associated with a refresh operation in a ferroelectric memory equipped with a refresh operation has been proposed (for example, see Patent Document 1). . Here, in the future market of ferroelectric memories, it is inevitable that an increase in the number of times of access to memory cells including the number of times of data rewriting as well as the number of times of data rewriting is increasingly required.

Data reading in a conventional ferroelectric memory will be described in detail below.
FIG. 9 shows a circuit configuration diagram of the memory array section in the ferroelectric memory. In FIG. 9, reference numeral 1 denotes a 1T1C (1-transistor 1-capacitor) type memory cell constituting a memory array, which includes a transistor 11 and a capacitor 12.

  BL0, BL1, and BL2 are bit lines, and / BL0, / BL1, and / BL2 are inverted bit lines. These are arranged so as to sandwich the plurality of memory cells 1 arranged in the row direction from above and below in the figure. The bit line and the inverted bit line constitute a bit line pair.

  WL0, WL1, and WL2 are word lines, and CP0, CP1, and CP2 are cell plate lines. These are arranged so as to sandwich the plurality of memory cells 1 arranged in the column direction from the horizontal direction in the figure. The line WL0 is connected to the gate of the transistor 11 of the memory cell 1, and the cell plate line CP0 is connected to the other end of the capacitor 12 which is the capacitor side end of the transistor 11 and the capacitor 12 connected in series. The drain of the transistor 11 which is the transistor side end of the connection body is connected to the bit line BL0.

  The memory cell 1 ′ adjacent to the memory cell 1 in the row direction and sandwiched between the word line WL1 and the cell plate line CP1 is connected to the word line WL1 at the gate of the transistor 11 like the memory cell 1. The other end of the capacitor 12 is connected to the cell plate line CP1, but the drain of the transistor 11 which is the transistor side end of the series connection body of the transistor 11 and the capacitor 12 is connected to the inverted bit line / BL1. Yes.

  Reference numeral 2 denotes a sense amplifier, which has a plurality of memory cells arranged in the row direction and is arranged so as to sandwich the bit line and the inverted bit line BL0, / The voltage difference between BL0 is detected and amplified. Reference numeral 3 denotes a bit line precharge circuit which precharges a voltage between the bit line pair BL0 and / BL0 in advance.

  Next, FIG. 10 shows a timing chart of main signals during the read operation. FIG. 11 shows an operation explanatory diagram using a hysteresis curve of the ferroelectric capacitor.

  When the data recorded in the memory cell 1 before the read operation is “1”, the Ta period in the timing chart of FIG. 10 before the selected word line WL0 and the selected plate line CP0 change from “L” to “H”. The polarization state in the hysteresis curve of FIG.

  Next, when the bit line precharge control signal BPE is changed from “H” to “L” and the selected word line WL0 and the selected plate line CP0 are changed from “L” to “H”, the storage data from the selected memory cell 1 is stored. Are read out to the bit line BL0. In this period Tb, the polarization state in the hysteresis curve in FIG. 11 shifts from the A point to the B point. Point B at this time is an intersection of the polarization inversion curve of the hysteresis curve and the bit line capacitive load line. At the same time, a reference potential for potential comparison is supplied to the bit line / BL0.

  Next, when the sense amplifier control signal SAE changes from “L” to “H”, the potentials of the bit lines BL0 and / BL0 are amplified to the power supply voltage difference of the sense amplifier circuit. In this period Tc, the polarization state in the hysteresis curve of FIG. 11 shifts from the B point to the C point. Further, when the potential difference between the bit lines BL0 and / BL0 is amplified to the power supply voltage difference of the sense amplifier circuit, the data in the memory cell 1 is normally extracted as read data, and then to the data bus line. Is finally transmitted to the outside of the memory device. The fact that the polarization state in the hysteresis curve in FIG. 11 has changed from point A to point C means that the amount of polarization charge from the beginning has decreased and destructive readout has been performed.

In a normal read operation, a rewrite operation described below is performed in order to reproduce the initial polarization state.
That is, when the selected plate line CP0 changes from “H” to “L” and enters the period Td in FIG. 10, the polarization state in the hysteresis curve in FIG. 11 shifts from the point C to the point D.

Next, after the sense amplifier control signal SAE is changed from “H” to “L”, the bit line precharge control signal BPE is changed from “L” to “H”, so that the selected bit line BL0 is set to “L”. The state of polarization in the hysteresis curve of FIG. 11 returns from the point D to the initial point A.
This means that a rewrite operation has been performed.

On the other hand, when the data recorded in the memory cell 1 before the read operation is “0”, the polarization state in the initial hysteresis curve is at the point A ′, and when the same operation timing is executed, the polarization state is B The process shifts sequentially to ', C', D '(= A'). In this case, unlike the case of “1” data, there is no decrease in the amount of polarization charge from the beginning, and destructive reading is not performed.
JP 2002-197887 A

  In the conventional ferroelectric memory as described above, when “1” data is read in the operation as described above, destructive reading in which the polarization charge amount decreases is performed, and then the initial polarization state is changed. A rewrite operation is being performed to reproduce. In this case, the degree is small compared with data rewriting from “0” to “1” or “1” to “0” with complete polarization reversal. As in the case of rewriting, the capacitor is loaded and its characteristics deteriorate.

  In general, in such a ferroelectric memory, although it depends on the system specification that employs the dielectric memory, the number of times of data reading is usually larger than the number of times of data rewriting operation. Characteristic degradation was never negligible. In addition, the rewriting in this read operation is different from the additional read operation accompanying the refresh operation, and the memory characteristic deterioration in the read operation including the rewrite cannot be easily solved. There was a problem that the number of accesses to the memory cell could not be increased.

  The present invention has been made in view of the above problems, and in a non-volatile memory that performs destructive reading, it is possible to suppress deterioration in characteristics of the non-volatile memory due to destructive reading and increase the number of accesses to the memory cell. It is an object to provide a conductive semiconductor memory device.

  In order to solve the above problems, a nonvolatile semiconductor memory device according to claim 1 of the present invention is a nonvolatile semiconductor memory device having nonvolatile memory cells that perform a destructive read operation and a subsequent rewrite operation. The rewrite operation is performed on the cell after the destructive read operation without the rewrite operation is repeated a plurality of times.

  As a result, the number of rewrite operations in the read operation for the memory cell can be reduced, deterioration of the capacitor due to the load on the ferroelectric capacitor can be suppressed, and the number of accesses to the memory cell can be increased as a result. It becomes possible.

  In the nonvolatile semiconductor memory device according to claim 2 of the present invention, the nonvolatile memory cell can be selectively connected to a bit line by a switching element. Before performing destructive read operation with rewrite operation, the destructive read operation without rewrite operation is performed in a state in which the switching element electrically separates the nonvolatile memory cell and the bit line by an external signal. Is repeated several times.

  Thereby, a destructive read operation without a rewrite operation can be easily performed by electrically separating the nonvolatile memory and the bit line by controlling the switching element.

  In the nonvolatile semiconductor memory device according to claim 3 of the present invention, the external signal is a word line signal.

  Thus, a destructive read operation without a rewrite operation can be performed by controlling the timing of the word line signal.

  In the nonvolatile semiconductor memory device according to claim 4 of the present invention, the predetermined number of times of repeating the destructive read operation without the rewrite operation is set in advance.

  As a result, the number of destructive read operations that do not involve a rewrite operation is limited, and the guarantee of stored data can be ensured.

  In addition, a nonvolatile semiconductor memory device according to claim 5 of the present invention is a count circuit that measures the number of times the destructive read operation without the rewrite operation is repeated, a memory circuit that stores the counted number, A comparator is provided that compares the number of times the destructive read operation without the rewrite operation stored in the storage circuit is repeated with the preset number of times set in advance.

  As a result, a circuit configuration that limits the number of destructive read operations that do not involve a rewrite operation can be easily realized using existing circuits such as a counter, a storage circuit, and a comparator.

  A nonvolatile semiconductor memory device according to a sixth aspect of the present invention includes the count circuit and the memory circuit for each word.

  As a result, the number of read operations for each memory cell can be counted by the number of read accesses by the word line, and the number of counters and storage circuits that are essentially required for each memory cell is greatly reduced. can do.

  According to a seventh aspect of the present invention, the nonvolatile semiconductor memory device includes an ECC circuit that detects a read error bit in a read operation with respect to the nonvolatile memory cell, and repeats the destructive read operation without the rewrite operation. Is determined by the bit error detection signal of the ECC circuit.

  Thus, the number of times that the destructive read operation without the rewrite operation is repeated can be determined by an existing ECC circuit, and an increase in circuit area due to the provision of a dedicated circuit for determining the number of times can be avoided. it can.

  In the nonvolatile semiconductor memory device according to claim 8 of the present invention, the nonvolatile memory cell is constituted by a ferroelectric capacitor.

  As a result, it is possible to suppress deterioration of characteristics associated with memory capacitor destructive reading in the ferroelectric memory, and to increase the number of accesses to the ferroelectric memory and reduce power consumption.

  According to the nonvolatile semiconductor memory device of the present invention, in the nonvolatile semiconductor memory device having the nonvolatile memory cell that performs the destructive read operation and the subsequent rewrite operation, the nonvolatile memory cell is not accompanied by the rewrite operation. Since the rewrite operation is performed after the destructive read operation is repeated a plurality of times, it is possible to reduce the load on the nonvolatile memory while guaranteeing the storage data in the read operation. It is possible to increase the number of readings and hence the number of accesses, and at the same time, it is possible to reduce power consumption.

(Embodiment 1)
Hereinafter, the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A shows a circuit configuration diagram of a memory array unit and a word system control unit in the ferroelectric memory according to the first embodiment of the present invention. In FIG. 1A, 1 is a 1T1C (1-transistor 1-capacitor) type memory cell constituting a memory array, BL0, BL1, and BL2 are bit lines, and / BL0, / BL1, and / BL2 are inverted bit lines. Both constitute a bit line pair, WL0, WL1, WL2 are word lines, CP0, CP1, CP2 are cell plate lines, 2 is a sense amplifier, 3 is a bit line precharge circuit, These are the same as those in the conventional circuit shown in FIG.

  Reference numeral 5 denotes a word-related control circuit, which is provided for each word line, and counts and stores the number of times the word line and the plate line are selected, and the drive driver that drives each word line and the plate line. Count memory / driver 53 including a circuit, and a comparison / word control circuit for controlling the word line by comparing the count number obtained by counting the number of times the word line and the plate line are selected with a predetermined number of times. 57.

  FIG. 2 shows a timing chart of main signals during a read operation in the ferroelectric memory according to the first embodiment, and FIG. 3 shows a basic operation explanatory diagram using a hysteresis curve of the ferroelectric capacitor.

  FIG. 4 is an operation explanatory diagram for explaining a read operation and a rewrite operation of an arbitrary memory cell in the ferroelectric memory according to the first embodiment. FIG. 5 is a diagram for explaining the strong operation according to the first embodiment. FIG. 6 is a schematic block diagram of a dielectric memory, and FIG. 6 is a control flow diagram of a read operation in the ferroelectric memory according to the first embodiment.

  In FIG. 5 showing a schematic block configuration diagram of the ferroelectric memory, 58 is an input / output circuit for inputting / outputting read / write data to / from the memory, and 56 is a control circuit including a row decoder for selecting a bit line. A certain control circuit decoder 54 is a comparator that compares a count obtained by counting the number of times the above-described word line and plate line are selected with a predetermined number of times, and 20 is a sense composed of a plurality of sense amplifiers 2. The amplifier group 10 includes a cell array in which each of a plurality of memory cells 1 is arranged in a matrix at each intersection of a plurality of word lines and a plurality of bit lines, and 53 represents each of the word lines and plate lines described above. A count storage / word driver including a drive driver and a circuit for counting and storing the number of times a word line and a plate line are selected.

  Further, in FIG. 6 showing a control flowchart of the read operation in the ferroelectric memory, S61 is a step of reading from the count storage circuit, and S62 is the number of read operations from the count storage circuit. S63 is a step for performing reading (no rewriting) when the number of readings is smaller than the limit value, that is, when the number of readings is less than the limit value, in the comparison determination in step S62, S64. Is a step of counting up the counter after step S63, and S65 is a case where the number of readings is equal to the limit value in the comparison determination in step S62, that is, the number of readings is equal to the limit value. The step of performing reading (with rewriting), S66, is performed after step S65. A step of performing pointer reset.

  First, a basic read operation without rewriting operation in the first embodiment will be described with reference to FIGS.

A. When the recorded data in the memory cell 1 is “1” When the data recorded in the memory cell 1 before the read operation is “1”, the selected word line WL0 and the selected plate line CP0 are changed from “L” to “H”. In the period Ta shown in the timing chart of FIG. 2 before the polarization state, the polarization state in the hysteresis curve is at the point A.

  Next, when the bit line precharge control signal BPE changes from “H” to “L” and the selected word line WL0 and the selected plate line CP0 change from “L” to “H”, the selected memory cell 1 starts. The stored data is read out to the bit line BL0. In this period Tb, the polarization state in the hysteresis curve of FIG. 3 shifts from the A point to the B point. Point B at this time is an intersection of the polarization inversion curve of the hysteresis curve and the bit line capacitive load line. At the same time, a reference potential for potential comparison is supplied to the bit line / BL0.

  Next, when the sense amplifier control signal SAE changes from “L” to “H”, the potentials of the bit lines BL0 and / BL0 are amplified to the power supply voltage difference of the sense amplifier circuit. In this period Tc, the polarization state in the hysteresis curve of FIG. 3 shifts from the B point to the C point. When the potential difference between the bit lines BL0 and / BL0 is amplified to the power supply voltage difference of the sense amplifier circuit, the data in the memory cell 1 is normally extracted as read data, and then is transferred to the data bus line. It is possible to normally output data to the outside of the memory device. Here, the fact that the polarization state in the hysteresis curve in FIG. 3 has changed from the point A to the point C means that the polarization charge amount from the initial stage has decreased and destructive readout has been performed.

  In a normal read operation, a rewrite operation described below is always performed in order to reproduce the initial polarization state, but this is not performed in the “read operation without rewrite operation” in the present invention. Specifically, at timing T2 before T3 when the selected plate line CP0 changes from “H” to “L”, the selected word line WL0 is changed from “H” using a transistor (not shown) as a switching element. It is set to “L” to separate the memory cell capacitor and the bit line. Thereafter, the selected plate line CP0 changes from “H” to “L” at the timing T3. Since the memory cell capacitor and the bit line are separated before this, the hysteresis of FIG. 3 in the period Td of FIG. The polarization state D point in the curve is the same as the C point.

  Next, after the sense amplifier control signal SAE is changed from “H” to “L”, the bit line precharge control signal BPE is changed from “L” to “H”, so that the selected bit line BL0 is set to “L”. Although charged, since the memory cell capacitor and the bit line are already separated, there is no change in the polarization state (period Ta on the right in the figure).

  Therefore, when this series of read operations is performed, the initial polarization state of data “1” is not reproduced after the read operation, and the polarization charge amount is reduced.

B. When the data recorded in the memory cell 1 is “0” On the other hand, when the data recorded in the memory cell 1 before the read operation is “0”, the polarization state in the initial hysteresis curve is at the point A ′. When the same operation timing is executed, the polarization state sequentially shifts to B ′, C ′, and D ′ (= A ′). Thus, in the case of “0” data, the read operation is the same as the conventional read operation, the polarization charge amount does not decrease from the initial stage, and destructive read is not performed.

  Next, a plurality of read operations for an arbitrary memory cell in the ferroelectric memory according to the first embodiment will be described with reference to FIG.

  The polarization state of the ferroelectric capacitor after performing the read operation without the rewrite operation described above is at a point D shown in FIG.

  When the second read access to the memory cell is performed, the polarization state is the same as the first read operation starting from the point D (in FIG. 6, steps S61, S62, S63, and S64 are performed). After that, a point D1 is finally reached via the intersection B1 with the bit line capacitive load line.

  In the second read operation, if the read potential difference that can be normally amplified by the sense amplifier can be secured between the selected bit lines BL0 and / BL0 in the period Tb in the timing chart of FIG. The data is taken out and then transmitted to the data bus line, and finally data can be normally output to the outside of the memory device.

  Further, when the third read access to the memory cell is performed, the polarization state is the same as the first and second read operations starting from the point D1 (in FIG. 6, steps S61 and S62). , S63, and S64), and finally reaches the point D2 via the intersection B2 with the bit line capacitive load line.

  Thus, when this read operation is repeated a plurality of times, the amount of polarization charge gradually decreases from the initial polarization state A (this is explained by the inventor in Japanese Patent No. 3191549). In the first embodiment, the number of times of normal reading is determined in advance by prior evaluation or the like, and it is determined that the reading operation can be repeated up to that number.

Thus, when the number of times of reading reaches a predetermined number of times (in FIG. 6, operations through steps S61, S62, S65, and S66 are performed), the selected word line WL0 is set to “H” in the read operation cycle. At T1, which is the timing of changing from “L” to “L”, the polarization state finally returns to the initial state point A via the points Cn and Dn (period Ta at the right end in FIG. 2).
This means that rewriting has been performed.

  When the data recorded in the memory cell 1 is “0”, it is not necessary to explain and there is no influence when the repeated read operation is performed.

  As described above, the feature of the first embodiment is that a rewrite operation is performed before the next data write to the same memory cell is performed on an arbitrary memory cell to which data has been written. This means that a predetermined number of read operations can be executed at the maximum, and the read operation involving the rewrite operation is executed when the number of times the same data is read reaches the predetermined number.

  Further, the rewrite operation can be executed as a separate operation cycle as in the normal refresh operation, or the rewrite operation can be executed for all cells on the same word line.

  As described above, in the read operation of the stored data “1”, in the read operation that was previously accompanied by the rewrite operation, the rewrite operation is not performed a plurality of times. Therefore, it is possible to increase the number of times of reading and hence the number of times of access.

  Here, as the initial polarization charge amount is larger, the setting of the number of readings without rewriting can be increased, and the load on the nonvolatile memory due to destructive reading can be reduced, which is advantageous in the first embodiment. Although described in the configuration of the 1T1C type cell, the same configuration and operation are possible in the 2T2C type cell, and when the initial polarization charge amount can be further increased, the number of reading without rewriting is further increased. Is possible.

  Next, the configuration of the counter circuit and the control flow of the reading operation in the first embodiment will be described with reference to FIGS. 1, 5, and 6. FIG.

  A count storage circuit 51 included in the count storage / driver 53 shown in FIG. 1 and including a count circuit 51a for counting the number of reads and a storage circuit 51b for storing the number of counts shown in FIG. Install every ward. This is because providing the count circuit for each memory cell leads to an increase in the area of the non-volatile memory, and it is considered most desirable to provide the count circuit for each word.

  In FIG. 1B, As is a drive signal output from the driver 52 that drives the word line and the cell plate line, and the count circuit 51a counts this. Rs is a reset signal for resetting the count circuit 51a from the driver 52.

  In FIG. 1C, 54 and 56 are comparators and driver control circuits constituting the comparison / word control circuit 57, Rc is a count value from the count storage circuit 51, and Cr A word line and a cell plate line output by the driver control circuit 56 based on the row selection signal output Sd from the row decoder (not shown) and the comparison output Sc of the number of counts from the comparator 54. Is a control signal for controlling the driving of the motor.

  FIG. 5 is a schematic block configuration diagram of the ferroelectric memory according to the first embodiment as described above, and FIG. 6 shows a control flow of a read operation in the block configuration of FIG. A case will be described in which all the memory cells on the same selected word are accessed simultaneously.

  First, in step S61 of FIG. 6, the number of read accesses to the selected word so far is read from the count storage circuit 51 included in the count storage / driver 53. Here, the number of read accesses means the number of times that a read operation without a rewrite operation is performed before the next data write to the same memory cell is performed after the data is written.

Next, the number of read times is compared with the limit number set in the comparator 54 in advance by the comparator 54 (step S62). If the number of access times is smaller, a rewrite operation is further performed. A non-read operation is executed (step S63).
Thereafter, the counter in the count storage circuit 51 is counted up (step S64).

Then, this read operation flow is repeated while changing the address, and when the read count reaches the limit count, a read operation involving a rewrite operation is executed based on the comparison result in the comparator 54 (step S65). The stored data “1” returns to the initial polarization state at this time.
Thereafter, the count number in the count storage circuit 51 is reset (step S66).

  Although not shown in FIG. 6, the count number in the count storage circuit 51 is similarly reset when the write operation is performed.

  When a memory array is configured with a plurality of columns on the same word line, the read operation flow is somewhat complicated. However, by controlling the timing for resetting the count circuit for each column, The same effect can be realized while enabling the guarantee.

  Although the configurations of the count circuit and the count memory circuit are not enumerated, any configuration that can be easily conceived from existing technology can be adopted.

  In the first embodiment, the case where the cell plate line is set to “H” when the sense amplifier is activated has been described. However, the present invention is not limited to this, and as shown in FIG. That is, even in the plate driving method from “H” to “L” before starting the sense amplifier, the same configuration as described above is possible, and the same effect can be obtained.

  FIG. 7 is a timing diagram of main signals during a read operation in the cell plate driving method of the ferroelectric memory according to the first embodiment. In this type of read operation, the cell plate line changes from “H” to “L” before the word line changes from “H” to “L”, and the sense amplifier control signal SAE indicates that the word line is “H”. After going from “L” to “L”, it goes from “L” to “H”.

  Also in this case, when the sense amplifier control signal SAE changes from “L” to “H” (timing T4), the potential difference between the pair of bit lines is amplified and data is read. At this timing T4, the word line has already been transferred. Since it is “L” at the time of T2, writing to the ferroelectric memory is not performed as in the operation shown in FIG.

  Thus, according to the first embodiment, before any data is written to the same memory cell before the next data is written to the same memory cell, the read without the rewrite operation is performed. The operation can be performed with a predetermined number of times as much as possible, and when the same data read count reaches this predetermined number of times, the stored data is guaranteed by executing the read operation with the rewrite operation. On the other hand, the load on the ferroelectric capacitor can be reduced, the number of readings to the ferroelectric memory, and hence the number of accesses can be increased, and at the same time, the effect of reducing power consumption can be obtained.

  In addition, since the destructive read operation without rewrite operation is performed by controlling the switching element with the word line signal and electrically separating the nonvolatile memory and the bit line, the circuit configuration is complicated. Therefore, a destructive read operation without a rewrite operation can be easily performed.

(Embodiment 2)
Hereinafter, a nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described with reference to the drawings.

The ferroelectric memory according to the second embodiment of the present invention is premised on a configuration having an ECC (error correction) bit and an ECC circuit for performing data operation for error correction in a memory cell array configuration. It is.
The circuit configuration diagram of the memory array portion in the ferroelectric memory according to the second embodiment is the same as FIG. 9 of the conventional example.

  Also, FIG. 2 shows a timing diagram of main signals during a read operation in the ferroelectric memory of the second embodiment, and FIG. 3 shows a basic operation explanatory diagram using a hysteresis curve of the ferroelectric capacitor. The operation explanatory diagrams of the memory cell read operation and rewrite operation are the same as those in FIG.

  FIG. 8A shows a schematic block diagram of the ferroelectric memory according to the second embodiment, and FIG. 8B shows a read operation flow chart of the ferroelectric memory.

  In FIG. 8A showing a schematic block diagram of the ferroelectric memory, reference numeral 78 denotes an input / output circuit for inputting / outputting read / write data to / from the memory, and 77 a book having ECC (error correction) bits. In the configuration of the memory cell array, an ECC circuit that performs data operation and performs error correction, 76 is a control circuit decoder that is a control circuit including a row decoder that selects a bit line, and 73 is a driver for driving each of word lines and plate lines It is a word system driver.

  Further, in FIG. 8B showing a control flow chart of the read operation of the ferroelectric memory, S81 is a step of performing a data read operation, S82 is a determination step of performing ECC determination of the read data, and S83 is When the determination result in step S82 is “determination flag = 0”, the step of no rewriting for changing the address and moving to the next reading operation without performing rewriting is performed, and step S84 is performed. When the determination result in S82 is “determination flag = 1”, after rewriting, the address is changed to move to the next reading operation, and there is a step of rewriting.

  The basic read operation without the rewrite operation in the second embodiment is shown in FIGS. 1 to 3, and the description of the operation is the same as in the first embodiment, and the description is omitted.

  First, a plurality of read operations for an arbitrary memory cell of the ferroelectric memory according to the second embodiment will be described with reference to FIG.

  As in the case of the first embodiment, the polarization state of the ferroelectric capacitor after performing the read operation without the rewrite operation once is at a point D in FIG.

  When the second read access to the memory cell is performed, the polarization state in FIG. 4 is the same as the first read operation starting from the point D, and passes through the intersection with the bit line capacitive load line. Finally, the point becomes D1.

  If the read potential difference that can be normally amplified by the sense amplifier can be secured between the selected bit lines BL0 and / BL0 in the period Tb in the timing diagram of FIG. 2 in the second read operation, the read data is normally extracted. Then, the data is transmitted to the data bus line, and finally, data can be normally output to the outside of the memory device.

  Further, when the third read access to the memory cell is performed, the polarization state in FIG. 4 starts from the point D1 and the same read operation as the first and second times is performed. It finally becomes point D2 via the intersection with the line.

  As described above, when this reading operation is repeated a plurality of times, the polarization charge amount gradually decreases from the initial polarization state A to the point D2 in FIG. In the second embodiment, it is determined that the read operation can be repeated until the read error bit is detected in the ECC circuit.

  In this way, when a read error bit is detected in the ECC circuit, if the timing from “H” to “L” of the selected word line WL0 in the same read operation cycle is T1, memory cells other than the error bit Is finally returned to the initial state point A via the points Cn and Dn.

Here, for the error bit, the stored data has already been destroyed, and the initial data cannot be reproduced.
The case where the data recorded in the memory cell 1 is “0” is not described, and there is no influence when the repeated read operation is performed.

  As described above, the feature of the second embodiment is that a rewrite operation is performed before the next data write to the same memory cell is performed on an arbitrary memory cell to which data has been written. Can be executed until an error bit is detected in the ECC circuit, and when the error bit is detected, a read operation with a rewrite operation is executed, and the rewrite operation is performed until no error is detected by data rewriting. The accompanying read operation is executed.

  With such a configuration, in the read operation of the stored data “1”, if the rewrite operation is not performed a plurality of times, the load on the ferroelectric capacitor is reduced correspondingly, so that the number of read operations, and consequently It is possible to increase the number of accesses.

  This is more advantageous as the initial polarization charge amount is larger because the number of readings without rewriting can be set larger. In the second embodiment, the case of the configuration of the 1T1C type cell has been described. However, the same configuration and operation can be performed in the 2T2C type cell, and in this case, the number of reading without rewriting can be further increased. It is.

Next, the control flow of the read operation according to the second embodiment will be described with reference to FIGS. 8 (a) and 8 (b).
In the second embodiment, the count circuit for the number of reading times as in the first embodiment is not required, and the error detection function by the existing ECC circuit shown in FIG. 8A can be used. It is possible to obtain the merit that the area does not increase.

  FIG. 8B shows a read operation control flow in the second embodiment. Here, all the memory cells on the same selected word are accessed simultaneously, and the number of bits that can be error-corrected is 1 bit. The case will be described.

  First, a normal read operation is performed (step S81), and if no error is detected in the ECC circuit (determination flag = 0), a read operation that does not involve a rewrite operation is executed (step S83). Here, when an error is detected (determination flag = 1), a read operation accompanied by a rewrite operation is executed (step S84), and other than the error bit, the stored data “1” is stored in FIG. The initial polarization state A shown in FIG. Regarding the error bit, the stored data has already been destroyed, and the initial data cannot be reproduced even if a read operation involving a rewrite operation is executed.

  In the read operation, when the same word is accessed again, the error detection in the ECC circuit 77 is continued by the remaining error bits, and therefore, a rewrite operation is performed through steps S81, S82, and S84 in FIG. The read operation is repeated.

  When the error bit is rewritten by the ECC circuit 77, the error detection in the ECC circuit disappears, so that the read operation without the write operation through steps S81, S82, and S83 in FIG. This is repeated until an error is detected.

  When a memory array is configured with a plurality of columns on the same word, a bit failure is not detected in a column that is not ECC-determined. Therefore, it is considered effective only when the number of bits that can be error-corrected is a plurality of bits.

  In the second embodiment, the case where the plate line at the time of starting the sense amplifier is set to “H” has been described. However, the present invention is not limited to this, and as shown in FIG. Even in the plate driving method from “H” to “L” before starting the sense amplifier, the same configuration as described above can be realized, and the same effect can be obtained.

  As described above, according to the second embodiment, before any data is written to the same memory cell before the next data is written to the same memory cell, reading without rewriting operation is performed. The operation can be executed until an error bit is detected in the ECC circuit. When the error bit is detected, a read operation with a rewrite operation is executed. Until there is no error detection by data rewriting, a read operation with a rewrite operation is performed. By executing, it is possible to reduce the load on the ferroelectric capacitor while guaranteeing the stored data, and it is possible to increase the number of reads and therefore the number of accesses, and at the same time achieve a reduction in power consumption. It becomes possible to do.

  Further, in the second embodiment, since the error detection function by the existing ECC circuit is used, there is an advantage that the area is not increased.

  The nonvolatile semiconductor memory device of the present invention can suppress deterioration due to a load on the nonvolatile memory, and is useful as a nonvolatile memory that requires a high number of accesses to a memory cell and low power consumption.

FIG. 5 is a circuit configuration diagram (FIG. (A)) of the memory array unit and the word system control unit in the ferroelectric memory according to the first embodiment of the present invention, and a circuit configuration diagram of the count storage / driver 53 (FIG. (B)) And a circuit configuration diagram of the comparison / word control circuit 57 (FIG. 2C). Timing chart of main signals at the time of read operation in Embodiment 1 of the present invention Basic operation explanatory diagram using hysteresis curve of ferroelectric capacitor in Embodiment 1 of the present invention Operation explanatory diagram of read operation and rewrite operation in the first embodiment of the present invention 1 is a block schematic diagram of a ferroelectric memory according to a first embodiment of the present invention. Flow chart of read operation in Embodiment 1 of the present invention Timing chart of main signals at the time of reading operation in the plate driving method in the first and second embodiments of the present invention A block schematic diagram of a ferroelectric memory according to the second embodiment of the present invention (FIG. (A)), and a read operation flow diagram according to the second embodiment of the present invention (FIG. (B)). A circuit configuration diagram of a memory array portion in a conventional ferroelectric memory (FIG. (A)) and a detailed circuit configuration diagram of memory cells 1 and 1 '(FIG. (B)) Timing diagram of main signals during read operation in conventional ferroelectric memory Operation explanatory diagram using hysteresis curve of conventional ferroelectric capacitor

Explanation of symbols

MC memory cell S.M. A. Sense amplifier B. P bit line precharge circuit 1 1T1C type memory cell 2 constituting memory array 2 sense amplifier 3 bit line precharge circuit 5 word system control circuit 58 input / output circuit 56 control circuit decoder 54 comparator 20 sense amplifier group 10 cell array 57 count Step S62 for reading from the memory / word driver S61 Counting Step S63 for comparing with the read limit number Step S63 for reading (without rewriting) Step S65 for counting up the counter Step S66 for reading (with rewriting) Counter resetting Step 78 I / O circuit 77 ECC circuit 76 Control circuit decoder 73 Word driver S81 Step S82 of read operation ECC judgment step S83 No rewrite step S84 Rewrite present, Steps

Claims (8)

In a nonvolatile semiconductor memory device having a nonvolatile memory cell that performs a destructive read operation and a subsequent rewrite operation,
For the nonvolatile memory cell, after repeating the destructive read operation without the rewrite operation a plurality of times, the rewrite operation is performed.
A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The nonvolatile memory cell can be selectively connected to a bit line by a switching element,
Before the destructive read operation involving the rewrite operation is performed on the nonvolatile memory cell, the switching element is electrically separated from the nonvolatile memory cell and the bit line by an external signal. The destructive read operation without the rewrite operation was repeated a plurality of times.
A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 2,
The external signal is a word line signal.
A non-volatile semiconductor memory device. The nonvolatile semiconductor device according to claim 1 or 2,
The number of times of repeating the broken read operation without the rewrite operation is set to a predetermined number in advance.
A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 4,
A count circuit for measuring the number of times the destructive read operation without the rewrite operation is repeated;
A storage circuit for storing the measured number of times;
A comparator that compares the number of times the destructive read operation without the rewrite operation is repeated and the preset number of times stored in the memory circuit;
A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 5,
The count circuit and the storage circuit are provided for each word.
A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1 or 2,
An ECC circuit for detecting a read error bit in a read operation for the nonvolatile memory cell;
The number of times to repeat the destructive read operation without the rewrite operation is determined by a bit error detection signal of the ECC circuit.
A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1 or 2,
The nonvolatile memory cell is composed of a ferroelectric capacitor.
A non-volatile semiconductor memory device.

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