JP2006228256A - Data recording device and data reader - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent digital data from being copied illegally. <P>SOLUTION: This data recording device includes: a means for holding a data storage medium; a means for acquiring identification from a semiconductor memory element; a means for holding a first code; a means for generating a second code according to the first code and the acquired identification; a means for encoding the data according to the second code; and a means for writing the encoded data to a semiconductor memory element. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data storage medium for storing digital data. It is another object of the present invention to provide a data recording apparatus for recording data on a data storage medium for storing digital data, and a data reading apparatus for reading data stored in the data storage medium.

  In recent years, various information such as characters, images, video, music, and voice has been handled as digital data. As a data storage medium for recording such digital data and program data, various media such as a tape, a floppy (registered trademark) disk, a hard disk, and a magneto-optical disk are used.

  For example, a floppy disk is a widely used medium, but it requires a motor and a rotating mechanism because the medium needs to be driven to rotate. Therefore, the electronic equipment that handles this data storage medium is reduced in size and weight. Is not a suitable medium.

  As an external data storage medium used in a portable electronic device, it is a challenge to achieve both compatibility with other electronic devices and reduction in size and weight suitable for portable use.

  As such a data storage medium, in recent years, a nonvolatile memory capable of electrically rewriting data has attracted attention as a data storage medium. As such a data storage medium, for example, a data storage medium in which a nonvolatile memory element is packaged in the form of a small memory card is known. Applications for recording contents such as still images, sounds, and music on the data storage media are also progressing. Unlike analog signals, content captured as digital data in a data storage medium does not cause deterioration in quality. Therefore, it is required to establish a technology for preventing unauthorized copying of unprotected content.

  Moreover, when authentication information used for electronic commerce, electronic banking, etc. is stored as digital data in a data storage medium, the situation is even more serious, and establishment of a technique for preventing unauthorized copying of digital authentication information is required. Yes.

  The present invention has been made to solve such problems. That is, an object of the present invention is to provide a semiconductor data storage medium having a read-only area. It is another object of the present invention to provide a semiconductor data storage medium having an area that can be written only once and then becomes read-only.

  It is another object of the present invention to provide a data storage medium capable of improving system security such as data communication and electronic commerce and preventing unauthorized copying.

  Another object of the present invention is to provide a data recording device and a data reading device that can prevent unauthorized copying of digital data.

  In order to prevent unprotected digital data from being copied and distributed to the world, individual recognition of the data storage medium itself is useful.

  For example, if the data storage medium itself composed of a semiconductor element individually has individual identification information of the data storage medium, the individual identification information can be used as a part of the encryption key, or the encryption key can be used again. It can be used as an encryption key for encryption. Based on such individual identification information, for example, contents such as music data are encrypted and recorded on a data storage medium having the individual identification information. This encrypted data is valid only when it is recorded on a data storage medium having individual identification information used for encryption. This is because when the encrypted data is decoded, the individual identification number of the data storage medium itself is involved. Even if music data recorded on a data storage medium having a certain individual identification number is copied to a data storage medium having another individual identification number, the music data is not transferred from the data storage medium having another individual identification number. Since the encryption key is different, it can never be read out, so it becomes meaningless music data for data storage media having other individual identification numbers.

  Therefore, in the rewritable nonvolatile memory constituting the data storage medium, as a method by which the manufacturer of the memory can individually identify individual data storage media at the manufacturing stage, A method of embedding means capable of individual identification has been taken. This means is particularly effective in a data storage medium called smart media that is configured only by a rewritable nonvolatile memory itself.

  In many cases, a special area dedicated to reading is set as a special area as a method by which the memory supplier can individually identify individual data storage media at the manufacturing stage. However, conventional special read-only special number areas are usually created as a mask ROM during the wafer manufacturing process, or are specially configured to make the special number area OTP. It was. However, the above method is complicated in terms of manufacturing process or device configuration, which increases the number of process days, which in turn increases the cost.

  Furthermore, as a method often used by a manufacturer of the memory to individually identify individual data storage media at the manufacturing stage, an individual identification number is written using a data signal line at the manufacturing stage, and the data is written. As a means for making the area read-only, there is a method of cutting the fuse portion of the line from the write signal with a laser or the like so that a signal necessary for writing is not applied again after writing.

  However, the method of cutting the fuse by the laser is complicated and expensive due to an additional step in the manufacturing process. In fact, it seems to be a physically absolute and perfect method of cutting a fuse, but if a human or process error occurs and it is not blown, it is judged whether the process is completed by visual inspection. However, there is a problem that the reliability of whether or not a specific area is completely read-only is lacking.

  In the present invention, a read-only special number area can be set in a rewritable nonvolatile memory with a simple configuration, and a memory device manufacturer can individually identify individual data storage media at the manufacturing stage. It is an object of the present invention to provide a method capable of giving individual identification information to a data storage medium.

  The data storage medium of the present invention includes a first connection terminal having a first memory cell and a second memory cell, the first connection terminal being connected to a wiring for controlling writing of data to the first memory cell, A semiconductor element having a second connection terminal connected to a wiring for controlling writing or erasing of the data to the second memory cell; connected to the first connection terminal; and the second connection terminal; Is electrically connected to the external connection terminal and the semiconductor element is sealed inside, and the external connection terminal is led out to the outside or exposed to the surface or side surface. And a means for holding the connection terminal.

  A data storage medium according to the present invention includes a wiring board having a first surface and a second surface, and is mounted on the first surface of the wiring board, and includes a first memory cell and a second memory cell. And a first connection terminal connected to a wiring for controlling writing of data to the first memory cell, and a wiring for controlling writing or erasing of the data to the second memory cell. A semiconductor element having a second connection terminal; and disposed on the second surface of the wiring board, connected to the first connection terminal, and electrically arranged independently of the second connection terminal. And an external connection terminal provided, and a sealing resin disposed so as to cover the semiconductor element and the second surface of the wiring board so as to seal the semiconductor element. .

  A data storage medium according to the present invention includes a wiring board having a first surface and a second surface, and is mounted on the first surface of the wiring board, and includes a first memory cell and a second memory cell. And a first connection terminal connected to a wiring for controlling writing or erasing of data to the first memory cell, and a wiring for controlling writing or erasing of the data to the second memory cell. A semiconductor element having a second connection terminal formed on the wiring board, and disposed on the second surface of the wiring board, connected to the first connection terminal, and electrically independent of the second connection terminal. A module having an external connection terminal disposed on the semiconductor device, a sealing means disposed on the second surface of the wiring board and covering the semiconductor element so as to seal the semiconductor element, and the external Hold the module so that the connection terminals are exposed on the surface. A holding member of a card type having a recess, characterized by comprising a.

  In the data storage medium of the present invention, the second connection terminal may be connected so as to control the conduction state of the wiring that controls writing or erasing of the data in the second memory cell.

  The second connection terminal may be connected to a gate electrode of a transistor interposed in the wiring that controls writing or erasing of data in the second memory cell.

  The second memory cell may hold identification information for identifying the semiconductor element. Further, user authentication information may be held in the first memory cell, and identification information may be held in the second memory cell.

  The semiconductor element may be substantially composed of a nonvolatile memory element. Further, a logic circuit may be provided in part of the nonvolatile memory element.

  As the nonvolatile memory element, for example, a flash EEPROM of NAND type, AND type, NOR type or the like may be used.

  The semiconductor element has a data register, and the writing and reading of the data to the semiconductor element are performed via the data register, and the memory capacity formed by the second memory cell is the data register of the data register. You may make it set below capacity.

  The semiconductor element has a logic circuit, and the first memory cell has a first area that can be directly accessed from the outside of the semiconductor element, and a second area that can be accessed only through the logic circuit. You may make it have this area | region.

  The data recording apparatus of the present invention is a data recording apparatus for recording data on a data storage medium provided with a semiconductor memory element having identification information, and means for holding the data storage medium; and the identification information from the semiconductor memory element. Means for acquiring, means for holding a first code, means for generating a second code based on the first code and the acquired identification information, and the data based on the second code Encoding means, and means for writing the encoded data into the semiconductor memory device.

  The data reading device of the present invention is a data reading device that reads data from a data storage medium having a semiconductor memory element having identification information, and obtains the identification information from the means for holding the data storage medium and the semiconductor memory element Means for holding the first code, means for generating a second code based on the first code and the acquired identification information, and means for reading the data from the semiconductor memory element And means for decoding the read data with the second code. The means for holding the first code may be a semiconductor element, and the individual identification information for identifying the semiconductor element holding the first code may be used as the first code.

  Further, it may be further provided with means for supplying the first code to the means for holding the first code. For example, a smart card may be used as means for supplying the first code to the means for holding the first code. That is, the first code is stored in the nonvolatile semiconductor memory element of a smart card having a semiconductor element having at least a logic circuit and a nonvolatile semiconductor memory accessed from the outside through the logic circuit. Alternatively, a read-only second area may be provided in the semiconductor element, and the first code may be stored in the second area. Of course, the identification information of the semiconductor element may be used as the first code.

  The data reading device may further include means for converting the decoded data into analog data, and the data stored in the memory cell may be output as analog data.

  According to a method of manufacturing a semiconductor device of the present invention, a plurality of connection terminals connected to a wiring for controlling writing or erasing of data are connected to the element region of a wafer having a plurality of element regions, and the first can hold the data. A step of forming a semiconductor memory device having a first region and a second region, a step of writing identification information of the semiconductor device in the second region of the semiconductor memory device, and an external connection terminal leading to the outside or a surface And the external connection terminal and the wiring for controlling writing or erasing of the data in the first region of the semiconductor memory element are connected to each other, and the second of the semiconductor memory element The semiconductor memory device is configured such that the connection terminal connected to the wiring for controlling writing or erasing of the data in a region is electrically independent of the external connection terminal. Characterized in that it and a step of sealing the.

  The step of writing the identification information in the second area of the semiconductor memory element may be performed before the wafer is separated into the element areas.

  The data storage medium of the present invention is a rewritable nonvolatile memory in which identification information capable of identifying individual memory devices is stored in a fixed memory area. The area for storing identification information is a read-only area. At the time of forming the area for storing the identification information, at least one or more dedicated electrode pads used only for writing provided on the memory chip are provided, and the electrode pads are used as memory devices. When packaged, it is not connected to the external electrode terminals but remains in the packaged state. The dedicated electrode pad used only for writing provided on the memory chip reads the data signal connected to the area for storing the identification information when the voltage is set to a certain specified voltage, and converts it into a dedicated signal It has a function that can be done.

  In addition, the dedicated electrode pad provided only on writing provided on the memory chip can not be applied with a high voltage for writing in the area for storing the identification information unless the voltage is set to a certain specified voltage. It has such a function.

  Only when the word line corresponding to each bit connected to the read-only area formed of the area for storing the identification information is used at the same time as the dedicated electrode pad used only for writing provided on the memory chip. The word line is maintained in a write state.

  Further, it is characterized in that the dedicated electrode pad used only for writing provided on the memory chip is controlled so as not to generate a writing high voltage necessary for the flash memory on the word line.

  When the tester test is performed by bringing the probe into contact with the electrode pad that is performed when the memory device is completed in a wafer state, the identification information is stored in the dedicated electrode pad that is used only for writing provided on the memory chip. You may make it write from the data signal connected with the area | region which stores identification information, applying a certain voltage.

  As described above, in the data recording medium of the present invention, a predetermined memory cell array can be a read-only area or an area that can be written only once but cannot be erased. Therefore, illegal copying can be prevented by storing management information such as identification information of semiconductor elements in these areas. In addition, system security can be improved. According to the manufacturing method of the data recording medium and the semiconductor device of the present invention, the second memory cell can be formed with high reliability, and the process can be realized very easily and at a low cost. .

  According to the data recording device and data reading device of the present invention, the identification information stored in the protected second memory cell of the data recording medium is used as the first encryption stored in the data recording device and the data reading device. It is possible to generate a second encryption key by encoding with the key, encode the data stored with this second encryption key, and decode the data to be read. Therefore, illegal copying of data can be prevented and system security can be improved.

  Hereinafter, the present invention will be described in more detail.

(Embodiment 1)
1 and 2 are diagrams schematically showing an example of a data recording medium of the present invention. Here, an IC card will be described as an example of a data recording medium. FIG. 1 illustrates an IC card with a CPU called a smart card, and FIG. 2 illustrates an IC card substantially consisting of memory elements called a memory card. IC cards can be broadly classified into those not equipped with a CPU. Here, an IC card (for example, an ISO compliant IC card) equipped with a CPU and memory is called a smart card. An IC card of a type that is not substantially equipped with a CPU composed of memory elements is called a memory card.

  The smart card 11 is 85.6 mm long, 54.0 mm wide, 0.76 ± 0.08 mm thick and conforms to ISO 7810, and includes a flat terminal 12 exposed on one surface. The flat terminal 12 of the smart card 11 is also compliant with ISO7816, and the IC built in the smart card 11 is accessed via the flat terminal.

  The size of the memory card 21 shown in FIG. 2 is 45.0 ± 0.1 mm in length, 37.0 ± 0.1 mm in width, 0.76 ± 0.08 mm in thickness, and JEDEC MO-186 (FLOPPY DISK). CARD / FLOPPY is a registered trademark). Although the shape and the number of pins are different from the planar electrode 12 of the smart card 11, the memory card 21 also has a planar terminal 22 exposed on one surface, and the IC built in through the planar terminal 22 is provided. Is accessed. In the data recording medium of the present invention, among the connection terminals of the semiconductor element, the wiring for controlling the erase operation / write operation of the memory cell storing the identification information is electrically connected without being connected to the planar terminal 22. They are arranged independently and in isolation. Therefore, in the data recording medium of the present invention, the identification information can only be read after packaging.

  Here, the smart card 11 will be described in more detail. FIG. 3 is a diagram schematically showing a configuration of a smart card 11 which is one type of IC card having a CPU and a memory. An MPU 13 chip is built in the smart card 11, and the MPU 13 includes a CPU 14, a program memory (ROM) 15, and an EEPROM 16 that is a data memory. One side of such a chip is molded, and the planar terminal 12 is formed on the other side.

  FIG. 4 shows an example of the pattern of the planar terminal 12 of the smart card 11. Pin 12a is a power supply (VCC), pin 12b is a reset (RST), pin 12c is a clock (CLK), pin 12e is a ground (GND), pin 12g is a transmission (I / O), and pins 12d and 12h are The spare pin 12f is unused.

  Next, the memory card 21 will be described in more detail. This memory card 21 is a flash memory card on which a NAND type EEPROM is mounted on one chip, and the size thereof is 45.0 ± 0.1 mm in length, 37.0 ± 0.1 mm in width, and 0.76 ± in thickness. 0.08 mm, which conforms to JEDEC MO-186 (FLOPPY DISK CARD). As an example of the form of this memory card, there can be mentioned what is called SmartMedia or SSFDC (Solid State Floppy Disk Card / Floppy is a registered trademark).

  This memory card 21 is mainly composed of two parts. As shown in FIG. 5, one is a package 23 on which a memory chip is mounted and provided with a planar terminal, and a base card 24 that holds this package.

  As shown in FIG. 6, the schematic structure of the package 23 is obtained by molding one side of a resin substrate 26 on which a memory chip 25 is mounted with a molding resin 27. The connection between the memory chip 25 and the wiring substrate 26 is here. In this case, wire bonding 28 is used. In order to make an electrical connection with the outside, a planar terminal 22 is provided on the opposite side of the package from the surface on which the memory chip 25 is mounted. Via connection is made through the provided through hole 26a. Further, the surface of the planar terminal 22 is gold-plated, and here, the gold-plating is performed to improve the mechanical wear resistance by reducing the purity of the gold to about 99.5%. By adopting such a configuration, the thickness of the package is as thin as about 0.65 mm.

  On the other hand, the base card 24 holding the package 23 has a recessed portion with a step for fitting the package 23 therein. In a step portion formed on the base card 24, the package 23 is fixed to the base card 24 by bonding in an unmolded region of the wiring board. The planar terminals 22 of the package 23 are fixed so as to form substantially the same plane as the surface of the base card 24. Note that the bottom of the concave portion of the base card 24 is formed slightly deeper than the thickness of the mold layer 27 of the package 23 to relieve the stress applied to the memory chip 25 and increase the thickness control margin in the molding process. ing.

  Since the thin portion of the base card 24 corresponding to the memory chip 25 is very thin, it is formed by injection molding using, for example, PC / ABS alloy having high fluidity.

  The package 23 and the base card 24 are fixed by using a thermocompression-bonding sheet mainly made of rubber. The thermocompression-bonding sheet is placed on the step portion of the basecard 24 and the package 23 is mounted. Crimped.

  The planar configuration of this memory card is such that the contact area where the planar terminal 22 is exposed, the area 81 where the write-protection sticker is pasted, the area 82 where the index label is pasted, the capacity, power supply voltage, type, etc. of the mounted memory chip It is composed of a notation area 83 to be indicated. Note that the cut-out portion 84 at one corner of the distal end in the insertion direction of the base card 24 is formed on the left and right according to the power supply voltage. For example, a memory card with a power supply voltage of 5V has a notch on the left side in the insertion direction, and a memory card with a power supply voltage of 3.3V has a notch on the right side in the insertion direction. This notch functions together with a slot mis-insertion prevention mechanism. For example, a power supply voltage of 5V is applied to a memory card having a power supply voltage of 3.3V to prevent the memory chip 25 from being electrically destroyed.

  In order to prohibit writing, a conductive seal is attached to the write protect area. The connection electrode 35 on the slot 34 side has two terminals in contact with the portion corresponding to the write protect area, and detects the presence / absence of the sticker on the basis of the conductive state, thereby enabling the memory card 21 in terms of software or hardware. You can protect the writing to.

  A NAND flash EEPROM mounted on the memory card 12 will be described. For example, in the case of 8 MB, this memory is a 3.3 V single power supply operation flash memory having a configuration of 528 bytes × 16 pages × 1,024 blocks. The memory chip is provided with a static register of 528 bytes, and data is transferred in units of 528 bytes between this register and the memory cell array in the program operation and the read operation. Erasing is executed in blocks (4 k bytes + 256 bytes). One page is not 512 bytes, but 528 bytes and an extra 16 bytes are added. This redundant area can be used as an ECC (error correction) code storage area or an area for storing management information. In the data recording medium of the present invention, a part of the redundant area may be read and used as a dedicated memory cell to store element identification information.

  This memory is a complete serial type memory that serially inputs / outputs addresses, data, and commands from the I / O terminal of the planar terminal, and is a type that automatically executes program and erase operations within the memory chip.

  FIG. 7 is a diagram showing the specifications and pin layout of a memory card using 2 MB, 4 MB, and 8 MB NAND type EEPROMs. FIG. 8 is a diagram schematically showing the configuration of the memory chip 25. Thus, the memory chip 25 does not have an address pin, and the address is input in a plurality of times from the I / O pin. For this reason, it is not necessary to increase the number of pins even if the number of pins is reduced and the memory capacity is increased. This is shown in the pin layout of the 32 MB and 64 MB NAND EEPROM illustrated in FIG. Therefore, the memory cards 21 having different capacities can be received without changing the configuration of the connection electrodes 35 on the connection device side such as the data recording device and the data reading device of the present invention. Further, the connection electrode 35 can be shared, and there is an advantage that different types of memory cards can be used in one connection device.

(Embodiment 2)
FIG. 9 is a diagram illustrating a plan configuration diagram of an NAND structure memory cell and an example of an equivalent circuit diagram. 9A shows a configuration of a 16M bit NAND memory cell, FIG. 9C shows a configuration of a 4M bit NAND memory cell, and FIG. 9B shows a 16M bit NAND memory cell. FIG.

  The memory cell transistor has a self-aligned two-layer gate structure, and both the floating gate FGi and the control gate CGi are formed of polysilicon. In the structure of 1 NAND, in the case of 4M bits, 8 memory cell transistors are inserted in series between two select transistors SG1 and SG2, and in the case of 16M bits, 16 memory cell transistors are connected in series. It is inserted. In FIG. 9, 101 is a contact hole, and 102 is a source line.

In order to write data into the flash memory, it is necessary to store electrons in the floating gate FGi in the memory cell. For this reason, the control gate CGi above the floating gate FGi is used.
It is necessary to apply a high voltage Vpp for writing. In the NAND flash memory, electrons are injected into the floating gate FGi by a tunnel phenomenon, and the NOR flash memory is executed by injecting hot electrons. Since the physical phenomenon called tunneling can be executed at a relatively low voltage even though it is a high voltage, the NAND flash memory has a booster circuit inside to generate this high voltage. Yes.

  In this example, a case where the present invention is applied to a NAND flash memory will be described as an example. However, the present invention can be similarly applied to a NOR flash memory and an AND flash memory.

  As a method for erasing / writing data in the memory cell, for example, a method in which a tunnel current is passed over the entire channel surface of the memory cell may be adopted.

  FIG. 10 is a diagram for explaining the erase operation of 1 bit of the memory cell, and FIG. 11 is a diagram for explaining the write operation of 1 bit of the memory cell. At the time of erasing, VEE is applied to the N-type substrate 103 and the P-well 104 by setting the control gate CGi to 0V. As a result, a tunnel current flows from the gate FGi to the N-type substrate, and the threshold value of the memory cell becomes negative. At this time, the tunnel current flows over the entire channel of the memory cell.

  On the other hand, in the case of writing, Vpp is applied to the control gate CGi to bring the N-type substrate 103 and the P well 104 to 0 V, contrary to erasing. Thereby, the tunnel current flows from the N-type substrate 103 to the floating gate FGi, and the threshold value of the memory cell becomes positive. The tunnel current flows over the entire channel of the memory cell at the time of writing as in the case of erasing.

Further, the memory cell not to be written is given an intermediate potential VP1 of 0V and VPP to the drain 106 to prevent erroneous writing. In the operation method in which a tunnel current is applied to the entire channel surface for both erase and write, an electric field is applied to the tunnel oxide film in both directions, so that the reliability of the element can be improved. In order to perform the operation of flowing a tunnel current over the entire surface of the channel in both erasing / writing, the memory cell array and the peripheral circuit are formed on the P-well 104 separated on the N-type substrate 103, respectively. The wiring structure is, for example, three-layer polysilicon, one-layer Al, and the third-layer polysilicon is a laminated structure with MoSi ₂ , and the Al metal wiring is formed with a Ti / TiN barrier metal as a base.

  In this NAND EEPROM chip configuration, a data register having a size corresponding to one row of the main body memory cell array also serving as a sense amplifier is arranged in the chip peripheral portion for page-by-page programming. In addition, a booster circuit (high voltage generation circuit) that generates a high voltage for erasing / writing for 5V or 3.3V power supply operation is provided, and the operation mode is controlled by command input. For example, redundancy has 4 blocks and 2 columns.

  FIG. 12 is a diagram schematically showing an internal configuration of an 8 MB memory cell array. In the main memory cell array, 16 bytes of redundant bits are added every 512 bytes. Data writing and reading uses a method of performing page units via a data register. In the case of 8 MB, 16k rows having 8 bits in the depth direction are prepared as memory areas. Individual identification information may be provided in this memory area, or may be provided in a block prepared as redundancy.

  The read operation includes page access for transferring selected one row of data from the memory cell to the data register, and serial access for reading data from the data register to the output terminal.

  FIG. 13 is a diagram for explaining the serial reading operation. As shown in FIG. 13, page access is started from the first input address, and when reading for one page is completed, page access of the next page is automatically performed. The external system can determine whether the page access is completed based on the level of the Ready / Busy terminal.

  In addition to the mode in which one page is read serially, the reading method includes a mode in which only the redundant portion is continuously read. These read modes can be used properly by inputting a command. This redundant part can store, for example, error correction codes, individual identification information, encryption keys, and the like.

  In this way, this device can adopt a reading method optimal for the file system.

  FIG. 14 is a flowchart for explaining an example of the write operation. In this example, the write time is controlled for each bit in order to narrow the threshold distribution and secure a sufficient power margin.

  First, a page address to be written is input, and then data to be written to the data register is input and then written for a predetermined time. Next, data is automatically read to check whether the threshold value of the memory cell is positive. Writing is performed again for bits for which the amount of writing is insufficient, and rewriting is prohibited for bits for which the threshold value is positive.

  FIG. 15 is a flowchart for explaining an example of the erasing operation. The erasing method may employ multi-block erase that can erase only selected arbitrary blocks.

  First, an address of an arbitrary block (a plurality of blocks) to be erased is input, and the block address is stored in an internal register. Erasing is performed by applying 0 V to the control gate CGi of the memory cell in the block corresponding to the stored block address. At this time, since the erase voltage is applied to the control gates of the memory cells in the non-selected block, only the selected block is erased.

  After erasing, the erased block address is read from the internal register, and it is checked whether the threshold value is sufficiently negative for the memory cells in the erased block. If erasure is insufficient, erasure is performed again. This series of operations is automatically repeated until all the blocks to be erased are erased.

(Embodiment 3)
FIG. 16 is a diagram schematically showing an example of the configuration of the memory cell of the NAND flash memory. By turning on the transistors SG1 and SG2 of the select S1 connected to the bit line and the select S2 connected to the ground line, a set of cell regions constituted by eight memory cell transistor units is activated.

  Then, the write and read states are set in the state of the word lines Wi (W1 to W8) connected to the control gates CGi of the eight memory cell transistors. For example, the other word lines of W1, W2, and W4 to W8 apply a voltage at which each memory cell transistor is turned on, for example, a voltage of about 3V to 5V. On the other hand, for example, when reading data written in W3, W3 is maintained in a floating state, and a voltage at which each transistor is turned on, for example, a voltage of about 3V to 5V is applied to the other word lines. The S2 conduction and non-conduction are sensed and read as data corresponding to the states of “0” and “1”.

  17 and 18 are diagrams schematically showing an example of the configuration of the data recording medium of the present invention. As described with reference to FIG. 16, the data write operation is executed by applying the high voltage Vpp to each word line Wi. For this reason, the word line Wi has a circuit configuration that is connected to Vpp when in the write state. At this time, a control circuit is further provided in a circuit that is connected to Vpp in the write state in all of the word lines Wi connected to a special area in which an arbitrary number that can be individually identified is written. A circuit configuration in which a dedicated line for controlling is set (FIG. 17). In FIG. 17, for example, the control circuit can generate the high voltage Vpp on the word line Wi only when a specific voltage is applied to the dedicated line.

  An example of this control circuit is shown in FIG. The gate of the transistor that controls the high voltage Vpp is connected to a dedicated line. For this reason, the Vpp line can be conducted only when a gate control signal is applied to the dedicated line. By adopting such a configuration, application of the voltage Vpp to the word line Wi can be controlled.

  That is, when performing a data erasing operation and a writing operation, it is necessary to apply the voltage Vpp to the word line Wi as described above. In the data recording medium of the present invention, the transistor 112 is inserted between the connection terminal 111 for inputting Vpp and the word line Wi, and the conduction state of the transistor is controlled by the input of the control terminal 113, whereby a predetermined value is obtained. The memory cell array is write protected.

  The source and drain of the transistor 112 are inserted between the connection terminal 111 for inputting Vpp and each word line Wi, and the gate electrode is connected to the terminal 113 of the control line.

  The terminal 113 is electrically isolated from the external connection terminal of the data recording medium illustrated in FIGS. 1 and 2, for example, so as to be isolated inside the module, thereby being connected to the word line Wi. The data stored in the memory cell array is read-only and cannot be rewritten. Management information such as individual identification information can be written while applying a voltage that turns on the transistor 112 to the terminal 113 before modularization at the time of manufacturing a semiconductor element, for example. Therefore, by storing management information such as identification information in a protected memory cell array, it is possible to improve usability in a system that requires security of the data recording medium and security of the data recording medium.

  By adopting the configuration as shown in FIG. 18, it can be set as a read-only special area in which an arbitrary number capable of individual identification of the entire unit of one page is written at the maximum.

(Embodiment 4)
FIG. 19 is a diagram schematically showing an example of the configuration of a semiconductor element constituting the data recording medium of the present invention.

  In this semiconductor element, connection terminals are provided in the peripheral portion of the integrated circuit 110 including the memory cell array, and access to the semiconductor element from an external circuit is performed via these connection terminals 111 and 114. In many cases, Vpp is normally directly applied from a high voltage generation circuit inside the memory chip. Here, for example, the connection terminal 111 is a terminal for inputting Vpp, and the connection terminal 114 is, for example, CLE, ALE. , WE, WP, / CE, / RE, R / B, GND, I / O, etc. are input terminals (see FIG. 7).

  In the data recording medium of the present invention, by adopting a configuration that prohibits access to a part of these connection terminals from an external circuit, the first memory cell capable of reading and writing and the second memory cell capable of only reading can be used. The memory cell is realized.

  That is, as described above, in the data recording medium of the present invention, a control circuit such as the transistor 112 is inserted between the connection terminal 111 for inputting Vpp and the word line Wi, and the conduction state of this transistor is controlled by the control terminal. By performing control according to input 113, write protection is applied to a predetermined memory cell (second memory cell). In order to prohibit access from the external circuit to the control terminal 113, the present invention is modularized in a state where the control terminal and the external connection terminal of the data recording medium are electrically arranged independently. 20 and 21 are diagrams schematically showing an example of the configuration of the data recording medium of the present invention. FIG. 20 shows a DIP type data recording medium, and FIG. 21 shows a type of data recording medium in which the external connection terminal 22 exemplified in FIG. 5 is integrated with a memory module. Here, in either case, the semiconductor element 25 is mounted by bonding mounting using the bonding wire 28, but it may be mounted in a face-down type by flip-chip connection using conductive bumps. Reference numeral 22c denotes a lead frame.

  When the memory element 25 is packaged with the insulating mold resin 27, the connection electrodes 111 and 114 described above are connected to the external connection terminals 22 and 22b of the package shown in FIGS. Contributes to exchanges with However, at least one control terminal 113 connected to a dedicated line for controlling Vpp application to the previous word line Wi is formed as a special terminal not connected to the external connection terminals 22 and 22b. The special control terminal is a dedicated pad that can be accessed only in a chip inspection process in which the semiconductor element 25 is in a wafer state or a normal die sort test process. In a state where access to the control terminal 113 is possible, the voltage Vpp can be applied to the word line Wi connected to the second memory cell. Therefore, for example, management information such as an individual identification number of a semiconductor element can be written. Thereafter, if the control terminal 113 is sealed in the module, the voltage Vpp cannot be applied to the word line Wi connected to the second memory cell unless the module is broken. After the semiconductor element 25 is packaged as illustrated in FIGS. 20 and 21, there is no external connection terminal 22, 22 b connected to the control terminal 113, so a specific region of the packaged semiconductor element is read out. It can be secured as a dedicated management information storage area.

  Note that the second memory cell 122 may be dedicated for internal access within the semiconductor element 25. Further, it may be a region dedicated to internal access and read-only in the semiconductor element 25. Further, it may be an area where only erasure control is impossible (writing can be performed only once).

  For example, a terminal for applying the write voltage to the word line Wi of the second memory cell and a terminal for applying the erase voltage are provided separately. Alternatively, a semiconductor element is formed except for a terminal for applying an erase voltage to the second memory cell.

  In the semiconductor device manufacturing process, “0” is written in all the memory cells at the wafer die sorter stage. Then, the erase voltage cannot be applied to the second memory cell. In this method, for example, at least one or more control terminals connected exclusively to the control line are provided, and “0” is written in the memory cell in the wafer state using the control terminals, and then the memory chip is sealed in the package. In this case, the control terminal can be implemented by the same method as described above so as not to connect the external connection terminals 22 and 22b. Further, as described above, it may be performed by inserting a control circuit such as a transistor.

  At this time, the semiconductor element is in a state where data can be written to the second memory cell only once. At this stage, the manufacturer of the semiconductor element may write management information such as identification information of the semiconductor element in the second memory cell. Further, the terminal for applying the write voltage to the word line of the second memory cell and the external connection terminal 22 of the data recording medium are connected so that the user and the vendor cannot erase the data as necessary (and are therefore read-only). Management information may be stored.

  Such an OTP region in which data can be written only once may be provided in addition to the aforementioned read-only and non-writable memory cells. Such an area is suitable for use in confidentiality, security management, copy prevention, and the like for users other than semiconductor device manufacturers.

(Embodiment 5)
According to the data recording medium of the present invention that can read management information such as identification information of a semiconductor element and store it in a dedicated memory cell, the security of, for example, an electronic commerce system, an electronic banking system, an electronic money system, etc. is improved. be able to. The data recording medium of the present invention can also be used in a file data distribution system that distributes file data such as music and video through various networks such as the Internet. For example, unauthorized copying of digital data stored in the memory element can be prevented. For example, such a system may be provided with means for accessing the semiconductor element 25 via the external connection terminals 22 and 22b of the data recording medium of the present invention. For example, the host device of the data recording medium of the present invention such as a PC, PDA, mobile phone, digital camera, portable music device or the like is based on the management information stored in the second memory cell of the data recording medium of the present invention. The data to be written to the first memory cell of the data recording medium is encrypted. As the file data, not only text data but also music data, image data, video data, etc. can be mentioned. In such a case, the music data may be distributed and distributed in a compressed state using a compression algorithm such as AAC, TwinVQ, AC-3, or MP-3. The image data may be distributed and distributed after being compressed by a compression algorithm such as JPEG or MPEG2.

  In any case, when data is stored from the host device to the data recording medium, the data is encrypted and coded based on the management information stored in the second memory cell and then stored in the first memory cell. Even if the digital data stored in the first memory cell is copied bit-to-bit to another semiconductor element or the like, the management information for decoding is different, resulting in meaningless data.

  In this way, by combining the data recording device, data reading device, and information processing device of the present invention with the data recording medium of the present invention (for example, smart cards, memory cards (including IC cards such as SmartMedia (registered trademark)), etc. It is possible to correspond to an electronic commerce system, an electronic banking system, an electronic money system, various distribution systems, and the like. In such a case, for example, the identification data encrypted in the memory card can be used for authentication and combined with the payment by the smart card, so that the security of the system can be further improved.

  As the identification data, for example, image data such as a fingerprint, a facial photograph, a voiceprint, an iris, voice data, or a combination thereof may be used. These identification data are preferably encrypted as a digital signature for authenticating an individual. For example, the identification data may be encrypted by a CPU of an interface and loaded into a memory card. Further, for example, encryption by the external interface may be performed based on management information such as identification information stored in the second memory cell in the memory card.

  As an example of such a system, an example in which music distribution and billing are performed using two IC cards, a smart card and a memory card, will be described. That is, music is distributed using various networks, and the distributed music is taken into the memory card, and charging and settlement are performed by the smart card. In particular, since data such as music, images, and videos are suitable for serial access, a data recording medium including an external connection terminal and a serial access type memory element can be preferably used.

  Music data is preferably distributed in a compressed state based on various compression algorithms such as AAC, AC-3, and MP-3, for example, from the viewpoint of preventing traffic congestion and improving communication speed. Further, if the memory card is stored in a compressed state, the capacity of the memory card can be saved. Furthermore, the music data held in the memory card may be encrypted. Further, the music data itself to be distributed may be encrypted. Furthermore, it is also possible to capture the encrypted music data to be distributed and store it in the data recording medium as it is.

  If such a music distribution system is used, for example, music can be distributed to users through various networks such as the Internet, and charging processing can be performed.

  Although an example of a music data distribution system has been described here as an example of file data, it may be applied to other distribution systems such as text data, image data, and video data (moving image data such as MPEG and MPEG2). It may be.

(Embodiment 6)
FIG. 22 is a diagram schematically showing an example of the configuration of the data recording / reading apparatus 30 of the present invention. FIG. 23 shows the data recording / reading apparatus 30 of the present invention illustrated in FIG. 22 from the opening side of the slot. FIG. FIG. 24 is a diagram schematically showing a perspective view of the data recording / reading apparatus 30 illustrated in FIG. 22 from the side. In this example, a device capable of performing both data recording and data reading will be described. However, the present invention can also be applied to a dedicated device for either data recording or data reading. Furthermore, in this example, an apparatus corresponding to two recording media (smart card and memory card) will be described, but the present invention can be described in exactly the same manner to an apparatus corresponding to one of the data recording media.

  This data recording / reading device 30 has a smart card (first data recording medium) 11 having a first external connection terminal 12 on a first surface and a second external connection terminal 22 on a first surface. , A device for inserting and holding a memory card 21 smaller than the first data recording medium 11 (second data recording medium, for example, SmartMedia). A first holding means 33 having a connection electrode 32 formed so as to come into contact with the external connection terminal 12 when the card 11 is inserted, and a side surface on which the connection electrode 32 of the first holding means 33 is formed, Stacked so that the region where the connection electrode 32 is formed is exposed, the slot 34 into which the memory card 21 is inserted, and the memory card 21 is inserted into the slot And a second holding means 36 having a forming connection electrodes 35 so as to contact with the external connection terminal 22 when it is. The first holding means 33 and the second holding means 36 are combined so as to hold the smart card 11 in the lower slot 31 and the memory card 21 in the upper slot 34. The first holding means 33 and the second holding means 36 are only required to be able to hold a data recording medium such as the inserted smart card 11 and memory card 21, and are not necessarily limited to a shape that covers the entire card. There is nothing. For example, it may be formed so that the data recording medium is held in an exposed form, such as a shape that covers about the data recording medium.

  FIG. 25 is a diagram for explaining an example of the mutual positional relationship when the smart card 11 and the memory card 21 are inserted into the slot 31 and the slot 34, respectively. In this way, the smart card 11 and the memory card 21 can be inserted into the slot so that the external connection terminal 12 and the external connection terminal 22 do not overlap each other by overlapping the opening side of the slot. At this time, the data recording / reading apparatus of the present invention is configured to contact the first external connection terminal 12 and the second external connection terminal 22 from the same side. In addition, the connection to the external connection terminal 32 can be performed in a region 40 of the first holding means 33 that does not overlap the second holding means 36. Further, an interface circuit including a controller for driving the smart card 11 and the memory card 12 may be formed in this area 40.

  The connection electrode 32 connected to the external connection terminal 12 of the smart card 11 and the connection electrode 35 connected to the external connection terminal 22 of the memory card 21 may be configured according to the shape of the external connection terminals 12 and 22.

  FIG. 26 is a diagram schematically showing an example of connection electrodes 32 and 35 in contact with external connection terminals. For example, as shown in FIG. 26, for example, a contact pin 37 having a spring mechanism may be provided according to the external connection terminal pattern. The wiring for connecting the connection electrodes 32 and 35 to the interface circuit, for example, may be formed in the slot or may be connected from the outside of the slot.

  FIG. 28 is a diagram schematically showing an example of the configuration of the data recording apparatus of the present invention. The data recording apparatus of the present invention is a data recording apparatus for recording digital data on a data recording medium having a semiconductor element having identification information, and means for holding a data recording medium 120 such as a memory card (for example, SmartMedia) or a smart card. A means for obtaining identification information from the second memory cell 122 of the semiconductor element 25, a nonvolatile memory element 123 for storing the first encryption key K1, a first encryption key K1, and the obtained identification information A. Means for generating the second encryption key K2 based on the data, means for encoding the data D1 to be stored in the first memory cell based on the second encryption key K2, and the encoded data D2 of the semiconductor element 25. Means for storing in the first memory cell 121 (see FIG. 28). In this example, the identification information A is acquired from the data recording medium 120, the first encryption key K1 is acquired from the nonvolatile memory element 123, and the second encryption key K2 based on the identification information A and the first encryption key K1 is obtained. The CPU 55a performs generation and encoding of the data D1 based on the second encryption key K2 into the data D2.

  FIG. 29 is a diagram schematically showing an example of the configuration of the data reading device of the present invention. The data reading apparatus according to the present invention is a data reading apparatus for reading data from a data recording medium having a semiconductor element having identification information. The data reading apparatus includes a means for holding the data recording medium 120, and a second memory 122 cell of the semiconductor element 25. Means for acquiring identification information A, means for holding first encryption key K1, and means for generating second encryption key K2 based on first encryption key K1 and acquired identification information A And means for reading the data from the semiconductor element, and means for decoding the read data with the second encryption key K2 (see FIG. 29). In this example, the identification information A is acquired from the data recording medium 120, the first encryption key K1 is acquired from the nonvolatile memory element 123, and the second encryption key K2 based on the identification information A and the first encryption key K1 is obtained. Generation and decoding of the data D2 into the data D1 based on the second encryption key K2 are performed by the CPU 55a. In the reading device, for example, data decoded by a D / A converter or the like may be converted into analog data and then output.

  As described above, the data recording medium 120 of the present invention has the first memory cell 121 that can read, write, and erase data, and the management data storage area that cannot perform writing and erasing. A second memory cell 122. In this data recording medium 120, the control terminal 113 is already embedded in the module electrically independently from the external connection terminal 22, and Vpp cannot be applied to the second memory cell 122.

  A data write operation will be described. The digital data supplied and to be stored in the first memory cell 121 is referred to as data D1. The CPU 55a of the data recording device 130a reads management information such as the identification information A (serial number or the like) of the semiconductor element stored in the second area 122 of the data recording medium 120, for example. Also, the encryption key K1 stored in the nonvolatile memory 123 in the interface circuit 55 is read. Then, the identification information A is encoded with the encryption key K1 to generate the encryption key K2.

  Then, the data D 1 is encoded by the encryption key K 2 to be data D 2, and this data D 2 is stored in the second memory cell 122.

  When reading data, the CPU 55a of the data reading device 130b reads management information such as identification information A (serial number, etc.) of the semiconductor element stored in the second area 122 of the data recording medium 120. Further, the encryption key K1 stored in the nonvolatile memory 123 in the interface circuit 55 is read, and the identification information A is encoded by the encryption key K1 to generate the encryption key K2.

  Then, the data D2 obtained from the second memory cell 122 of the data recording medium 120 is decoded by the encryption key K2 to be data D1, and this data D1 is output to the outside. At this time, the digital data D1 is preferably converted into analog data by a D / A converter and then output to prevent unauthorized copying of data. In the example described here, the identification information A corresponds to a public key, and the first encryption key K1 corresponds to a secret key. Even when the data D2 is copied from the data recording medium 120 having the semiconductor element 25 having the unique identification information A to the data recording medium having the other unique identification information B, the data reading apparatus decodes D2. Therefore, the illegally copied data does not make sense. The first encryption key K1 shown in FIGS. 28 and 29 is used as individual identification information for identifying the means for holding the first encryption key K1, that is, the data recording device 130a and the data reading device 130b. Information of D2 is exchanged in a one-to-one relationship with the holding means. In this case, if the system is inconvenient, the first encryption key K1 may be supplied from the outside.

  At this time, from the viewpoint of security, it is desirable that the secret key K1 has individual identification information. For example, a private key owned by a person recorded on a smart card can be used as the first encryption key K1.

  By the way, as an example of an individual private key recorded on this smart card, when data such as music data is distributed over a network or the like and an individual receives predetermined data, the predetermined data is simultaneously with payment. The one received with is considered. As a result, a safer and more secure system is constructed so that data other than those who have acquired the proprietary data can be used only by legitimate means, for example, a person who has paid for the data value.

  The encoding and decoding schemes described here are examples, and other schemes can be used. In the present invention, by storing unique identification information for each semiconductor element 25 or each data recording medium 120 in the read-only second memory cell 122, it is possible to improve data security and prevent unauthorized copying.

  As shown in FIG. 27, the interface circuit 55 may include at least one CPU (or DSP) 55a. Thereby, for example, the CPU 55a can encrypt the data D to be stored in the first memory cell of the data recording medium and decrypt the data read from the first memory cell. Further, since the IC built in the smart card 11 also includes a CPU, for example, the CPU of the smart card 11 holds the first encryption key K1, and the CPU of the interface circuit 55 processes the second encryption key K2. You may do it. Further, as data held in the second memory cell of the memory card 21, management information such as identification information A, and photo information such as a digital signature for authentication, information such as a fingerprint and a voice print are held / read out. In this case, the data stored in the memory card 21 can be secured by encrypting / decrypting the data by the CPU 55a of the interface circuit 55 or the CPU of the smart card 11.

  The CPU 55a can execute more complex encryption / decryption processing in a shorter time when the processing capability is higher. The longer the bit length of the RSA key value, the greater the load on the CPU that processes it. Therefore, it takes too much time for such a complicated process to be performed by, for example, a smart card CPU unless a means such as a dedicated coprocessor is provided. For this reason, in the present invention, such “heavy” processing is performed by the CPU in the interface circuit 55. For example, a relatively high-performance CPU such as 16 bits or 32 bits may be used as needed. it can.

  On the other hand, in the case of data that does not need to be encrypted or decrypted, the interface circuit 55 may be designed to access the host side via a through path. For this purpose, for example, a header indicating whether or not the data is encrypted may be added to the data held in the memory card 21. Such a header addition can also be executed by the CPU of the smart card 11.

  By adopting such a configuration, the data recording / reading apparatus of the present invention can prevent illegal copying of digital data. Further, by storing authentication information or the like in the data recording medium of the present invention, it is possible to improve security in handling electronic payment and digital money. In particular, data such as digital signatures and medical records having a large amount of information of about 1 to 16 MB that cannot be handled by so-called smart cards can be stored safely, and can be safely transmitted to the PC side or the network side.

The figure which shows schematically the example (smart card) of the data recording medium of this invention. The figure which shows schematically the example (memory card | curd) of the data recording medium of this invention. The figure which shows the structure of a smart card typically. The figure which shows the example of the pattern of the external connection terminal of a smart card. The figure which shows the structure of a memory card typically. The figure which shows schematically the structure of the package which mounts a memory chip and was provided with the external connection terminal. The figure which shows the specification and pin layout of 16 Mb NAND type EEPROM. The figure which shows the structure of a memory chip typically. 2A and 2B are a plan view of an NAND structure memory cell and an example of an equivalent circuit diagram. The figure for demonstrating the erase operation of 1 bit of memory cells. The figure for demonstrating the write-in operation | movement of 1 bit of memory cells. The figure which shows typically the internal structure of a 16M bit memory cell array. The figure for demonstrating serial reading operation | movement. The flowchart for demonstrating the example of write-in operation. 9 is a flowchart for explaining an example of an erasing operation. The figure which shows typically the example of a structure of the memory cell of NAND type flash memory. The figure which shows schematically the example of a structure of the data recording medium of this invention. The figure which shows schematically the example of a structure of the data recording medium of this invention. The figure which shows schematically the example (smart card) of the data recording medium of this invention. The figure which shows schematically the example of a structure of the data recording medium of this invention. The figure which shows schematically the example of a structure of the data recording medium of this invention. The figure which shows roughly an example of a structure of the data recording / reading apparatus of this invention. The figure which looked at the data recording and reading apparatus of this invention from the opening part side of the slot. The figure which shows typically a mode that the data recording / reading apparatus of this invention was seen through from the side. The figure for demonstrating the example of a mutual positional relationship when a smart card and a memory card are each inserted in a slot. The figure which shows schematically the example of the connection electrode which contacts an external connection terminal. The figure for demonstrating another example of a structure of the data recording / reading apparatus of this invention. The figure which shows typically the example of a structure of the data recording device of this invention. The figure which shows typically the example of a structure of the data reading apparatus of this invention.

Explanation of symbols

11: Smart card 12: External connection terminal 13: MPU chip 14: CPU
15 ... ROM (program memory)
16… .EEPROM
21 ......... Memory card 22 ......... External connection terminal 22b ... External connection terminal 23 ......... Package 24 ......... Base card 25 ......... Memory chip 26 ......... Resin substrate 27 ......... Mold resin 28 ... ...... Wire bonding 30 ... Data recording / reading device 31, 34 ... Slots 32 and 35 ... Connection electrode 33 ... First holding means 36 ... Second holding means 37 ... Contact Pin 40... Region 50 of first holding means not facing second holding means... Casing 51... Connector (data recording / reading device side)
52 ... Connector (on the main unit side)
53 .... Central processing unit (CPU)
54 .... Substrate 55 .... Interface circuit 55a .... CPU (interface)
56 ......... Bus 59 ......... Connection wiring 61 ......... Memory 62 ......... Counter 63 ......... Sensor 65 ......... I / F (PC side)
66 .... I / F (data recording media side)
101 ......... Contact hole 102 ......... Source line 103 ......... Semiconductor substrate (N-type)
104 ... P well 105 ... Source region 106 ... Drain region 111 ... Connection terminal 112 ... Transistor 113 ... Control terminal 114 ... Connection terminal 120 ... Data recording medium 121 ... First memory cell array 122 Second memory cell array 123 Non-volatile memory 130a Data recording device 130b Data reading device

Claims (2)

In a data recording apparatus for recording data on a data storage medium including a semiconductor memory element having identification information,
Means for holding the data storage medium;
Means for obtaining the identification information from the semiconductor memory device;
Means for holding the first code;
Means for generating a second code based on the first code and the acquired identification information;
Means for encoding the data based on the second code;
Means for writing the encoded data to the semiconductor memory device;
A data recording apparatus comprising: In a data reading device for reading data from a data storage medium having a semiconductor memory element having identification information,
Means for holding the semiconductor medium;
Means for obtaining the identification information from the semiconductor memory device;
Means for holding the first code;
Means for generating a second code based on the first code and the acquired identification information;
Means for reading the data from the semiconductor memory device;
Means for decoding the read data with the second code;
A data reading device comprising:

Images