JP2006227742A - Reset circuit for microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To distinguish whether a reset signal inputted to a reset input terminal is caused by abnormality on a microcomputer side or by the other cause. <P>SOLUTION: A delay reset signal based on time of power-on from a delay circuit 12, a low voltage detection reset signal from a low voltage detection part 14 detecting low voltage of a power source, and a WDT abnormality detection reset signal from a WDT abnormality detection circuit part 16 monitoring a P-RUN signal are inputted to the reset input terminal R of the microcomputer 10. A storage circuit part 20 receives a storage clear signal from the low voltage detection part, and outputs a WDT reset signal that is a Hi level to a WDT reset signal input terminal W when the reset signal is inputted to the reset input terminal R while not detecting the low voltage. The microcomputer 10 can identify whether the reset signal to the rest input terminal R is caused by the low voltage or by the WDT abnormality by WDT reset signal reference. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reset circuit for resetting a microcomputer when the microcomputer cannot ensure normal operation.

A microcomputer having a CPU (central processing unit) as a main element is provided with a reset circuit for resetting and restarting when the normal operation cannot be ensured.
For example, when the voltage of the power source that supplies power to the microcomputer becomes a predetermined low voltage that cannot ensure the normal operation of the microcomputer, a low voltage detection reset signal from the low voltage detection unit is input to the microcomputer. To reset. When the WDT (watchdog timer) abnormality detection circuit section monitors the P-RUN signal from the CPU and the P-RUN signal is interrupted, it is assumed that the CPU is out of control and the WDT abnormality detection reset signal is sent to the microcomputer. To reset.

In addition, when the power to the microcomputer is turned on, a delay reset signal is also input to the microcomputer from the delay circuit in order to suppress the start-up of the microcomputer until the voltage reaches a predetermined value.
In the conventional reset circuit, all the reset signals described above are input to a common reset input terminal of the microcomputer.
Japanese Utility Model Publication No. 6-24898

By the way, it is desirable to change the treatment after reset when the reset signal is input to the microcomputer depending on the type of the reset signal.
For example, in the case of a low-voltage detection reset signal, the power supply voltage is only low and there is no abnormality on the microcomputer side. Therefore, after the reset is released, the microcomputer can continue normal operation again. On the other hand, in the case of the WDT abnormality detection reset signal, it is necessary to shift to a failure mode such as the operation stop or failure notification as a failure of the microcomputer.

  However, since the microcomputer has only one reset signal input terminal and the conventional reset circuit simply inputs each reset signal to the common reset input terminal, whether the low-voltage detection reset signal is WDT. The microcomputer cannot determine whether it is an abnormality detection reset signal or even a delayed reset signal, and there is a problem that the action after reset release must be fixed to continue operation or stop operation. It was.

  Therefore, in view of the above-described conventional problems, the present invention provides a microcomputer reset circuit that can determine whether the reset signal input to the reset input terminal is due to an abnormality on the microcomputer side or due to another cause. The purpose is to provide.

  Therefore, the present invention provides a reset circuit that includes a first reset signal input terminal in a microcomputer and resets the microcomputer when a reset signal based on the internal and external states of the microcomputer is input to the first reset signal input terminal. The microcomputer further includes a second reset signal input terminal for inputting a reference signal based on the generation state of the reset signal, and the reset signal input to the first reset signal input terminal is based on the internal state of the microcomputer. Or whether it is based on external conditions.

  By referring to the reference signal input to the second reset signal input terminal, it is possible to identify whether the reset signal input to the first reset signal input terminal is based on an internal state or an external state. Therefore, in the microcomputer, it is possible to select an appropriate measure to continue normal operation or stop operation after reset release.

Hereinafter, embodiments of the present invention will be described in detail.
FIG. 1 is a block diagram showing the configuration of the embodiment.
A delay circuit 12, a low voltage detection unit 14, and a WDT abnormality detection circuit unit 16 are connected to the power supply B for the microcomputer 10 in parallel with the microcomputer 10, respectively.
The microcomputer 10 is provided with a reset signal input terminal R, a P-RUN signal output terminal P, and a WDT reset signal input terminal W.
The outputs of the delay circuit 12, the low voltage detection unit 14, and the WDT abnormality detection circuit unit 16 are connected to the reset signal input terminal R of the microcomputer 10 via the AND circuit 18.
The P-RUN signal is input from the P-RUN signal output terminal P to the WDT abnormality detection circuit unit 16.
A memory circuit unit 20 is connected to the WDT reset signal input terminal W of the microcomputer 10. The output side of the AND circuit 18 is also connected to the memory circuit unit 20.

The delay circuit 12 outputs a delay reset signal until the power supply voltage reaches a voltage necessary for the microcomputer 10 to operate when the power is turned on.
The low voltage detection unit 14 outputs a low voltage detection reset signal when the power supply voltage becomes equal to or lower than a predetermined low voltage VB at which the operation of the microcomputer 10 becomes unstable.
The WDT abnormality detection circuit unit 16 outputs a WDT abnormality detection reset signal when the P-RUN signal input from the microcomputer 10 is interrupted (when WDT is abnormal).
The low voltage detection unit 14 further outputs the same memory clear signal as the low voltage detection reset signal to the storage circuit unit 20.
The storage circuit unit 20 selectively stores and clears reset signals from the delay circuit 12, the low voltage detection unit 14, and the WDT abnormality detection circuit unit 16 that have passed through the AND circuit 18 based on the storage clear signal. The memory circuit unit 20 outputs a WDT reset signal to the WDT reset signal input terminal W of the microcomputer 10.

The timing chart of FIG. 2 shows a specific example of each signal described above.
The delayed reset signal indicates the Low level until a predetermined time elapses (delay) after the power supply voltage reaches the voltage VA, and then becomes the Hi level. The power supply voltage usually becomes higher than the voltage VB as a delay time elapses after reaching the voltage VA.
The low voltage detection reset signal and the storage clear signal are at a high level when the power supply voltage is higher than the voltage VB, and at a low level when the voltage is lower than the voltage VB.
The WDT abnormality detection reset signal indicates a low level for a predetermined time from when the P-RUN signal stops, and then becomes a high level.
The delayed reset signal, the low voltage detection reset signal, and the WDT abnormality detection reset signal are given priority to the low level through the AND circuit 18, and when any of them becomes the low level, the reset signal input terminal R of the microcomputer 10 has a reset signal as a reset signal. Low level is input.

  The memory circuit unit 20 sets the WDT reset signal to the Low level while the memory clear signal from the low voltage detection unit 14 is at the Low level, and from the AND circuit 18 to the Low level while the memory clear signal is at the Hi level. When (reset signal) is input, a Hi-level WDT reset signal is output to the WDT reset signal input terminal W of the microcomputer 10, and this state is maintained.

A time t1 in FIG. 2 indicates a state in which the delay reset signal changes from Low to Hi level after power-on and the start-up is started in a normal voltage state.
Since the low voltage detection reset signal is also at the Hi level, the P-RUN signal is normal, and the WDT abnormality detection reset signal is at the Hi level, the reset signal input from the AND circuit 18 to the reset signal input terminal R of the microcomputer 10 is at the Hi level. is there.
Although the memory clear signal is also at the Hi level, the WDT reset signal from the memory circuit unit 20 is at the Low level because the reset signal is not at the Low level.

Between time t2 and t3, since the power supply voltage has become low, the low voltage detection reset signal changes to low level, and the reset signal input from the AND circuit 18 to the reset signal input terminal R of the microcomputer 10 is low level. It becomes.
At this time, since the memory clear signal is also at the low level, the WDT reset signal remains at the low level.

At time t4, the power supply voltage is normal, but the P-RUN signal from the microcomputer 10 is interrupted, so that the WDT abnormality detection reset signal changes from Hi to Low level. As a result, the reset signal input to the reset signal input terminal R of the microcomputer 10 becomes a low level.
Since the power supply voltage is not a low voltage, the memory circuit unit 20 outputs the Hi level WDT reset signal because the Low level reset signal is input while the memory clear signal is at the Hi level.
Thereafter, the WDT abnormality detection reset signal returns to the Hi level after a predetermined time has elapsed, but the Hi level WDT reset signal continues.

At time t5, when the Hi-level WDT reset signal continues, the P-RUN signal recovers, and then the power supply voltage becomes low. The low-voltage detection reset signal changes to Low level. The memory clear signal also goes low.
As a result, the reset signal input to the reset signal input terminal R of the microcomputer 10 changes to Low level, and the WDT reset signal changes from Hi to Low level.
From the above changes in the signals, the WDT reset signal becomes the Low level when the reset signal is based on the low voltage detection, and the WDT reset signal becomes the Hi level only when the WDT abnormality is detected.

In the reset circuit of the microcomputer configured as described above, the reset signal is input to the reset signal input terminal R, the microcomputer is reset, and the reset signal is input by referring to the state of the WDT reset signal after releasing the reset. It is possible to identify whether the reset signal input to the terminal R is due to only WDT abnormality or low voltage.
Therefore, the microcomputer 10 can take an appropriate action after reset release based on the identification result of the cause.
FIG. 3 shows a processing flow at the time of reset signal input in the microcomputer 10.
When the reset signal is input to the reset signal input terminal R and the microcomputer 10 is reset, first after the reset is released, in step 101, the input state of the WDT reset signal input terminal W is read. In step 102, the WDT reset signal is It is checked whether the level is Hi level or Low level.

When the WDT reset signal input to the WDT reset signal input terminal W is at the low level, it is assumed that the low voltage is included, the process proceeds to step 103 and restarts, and the process for the current reset signal input is terminated. Thereby, the microcomputer 10 continues normal operation.
On the other hand, if the WDT reset signal is at the Hi level in the check in step 102, it is determined that the WDT is abnormal, and the process proceeds to step 105 to stop the operation of the microcomputer 10 or shift to the fail mode. Reset the power and exit.

  If the P-RUN signal from the microcomputer 10 is interrupted at the same time as the power supply voltage becomes low, and the low voltage detection reset signal and the WDT abnormality detection reset signal are simultaneously set to the low level, the memory clear signal is also set to the low level. Therefore, the memory circuit unit 20 sets the WDT reset signal to the low level. Therefore, the microcomputer 10 proceeds from step 102 to step 103 and executes normal reset processing. If the P-RUN signal is not issued even after the reset process is restarted and the low voltage state is resolved, the WDT abnormality detection reset signal becomes the low level, and the process proceeds from step 102 to step 105 this time. Therefore, when there is a WDT abnormality, an abnormal process such as operation stop is finally performed.

  The present embodiment is configured as described above. The microcomputer 10 includes the reset signal input terminal R, and a reset signal based on the internal and external states of the microcomputer is input to the reset signal input terminal R to reset the microcomputer. In the reset circuit, the microcomputer 10 further includes a WDT reset signal input terminal W for inputting a WDT reset signal as a reference signal based on the generation state of the reset signal, and the reset signal input to the reset signal input terminal R is the microcomputer. Since it is possible to discriminate whether it is based on the internal state or the external state, it is possible to select an appropriate treatment to continue normal operation or stop operation after reset is released.

More specifically, the reset signal based on the state outside the microcomputer is a low voltage detection reset signal from the low voltage detection unit 14 that detects the low voltage of the power supply B, and the reset signal based on the state inside the microcomputer is P A WDT abnormality detection reset signal from the WDT abnormality detection circuit unit 16 that monitors the RUN signal. The WDT reset signal is output from the storage circuit unit 20 based on the storage clear signal output from the low voltage detection unit 14 corresponding to the low voltage detection reset signal, and the power source is not at a low voltage. Changes when there is a reset signal. Thereby, the microcomputer 10 can identify whether the reset signal is due to a low voltage or a failure of the microcomputer itself.
In other words, the microcomputer restarts after reset release if the reset signal is based on an external condition such as a low voltage, and resets if the reset signal is based on the internal condition due to WDT abnormality. After canceling, the operation stops or moves to fail mode.

In the embodiment, each reset signal output from the delay circuit 12, the low voltage detection unit 14, and the WDT abnormality detection circuit unit 16 indicates a state to be reset at a low level, and the WDT reset signal from the storage circuit unit 20. Indicates the Hi level when the WDT abnormality detection reset signal is generated, but the setting of the signal level is not limited to this, and it may be reversed as long as it can be identified.
The storage clear signal output from the low voltage detection unit 14 to the storage circuit unit 20 may use the low voltage detection reset signal itself.
Further, the predetermined voltage VA of the delay circuit 12 is set slightly lower than the predetermined low voltage VB of the low voltage detector 14, but may be the same value.

It is a block diagram which shows the structure of embodiment. It is a timing chart which shows the signal state in an embodiment. It is a flowchart which shows the flow of a process in a microcomputer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Microcomputer 12 Delay circuit 14 Low voltage detection part 16 WDT abnormality detection circuit part 18 AND circuit 20 Memory circuit part B Power supply P P-RUN signal output terminal R Reset signal input terminal W WDT Reset signal input terminal

Claims (4)

In a reset circuit that includes a first reset signal input terminal in a microcomputer, and a reset signal based on internal and external states of the microcomputer is input to the first reset signal input terminal to reset the microcomputer.
The microcomputer further comprises a second reset signal input terminal for inputting a reference signal based on the cause of occurrence of the reset signal,
The microcomputer can identify whether the reset signal input to the first reset signal input terminal is based on an internal state or an external state by referring to the reference signal. A microcomputer reset circuit. The microcomputer has a low voltage detection unit for detecting a low voltage of the power supply, a WDT abnormality detection circuit unit for monitoring the P-RUN signal, and a memory to which the reset signal input to the first reset signal input terminal is input. A circuit part is attached,
The reset signal based on the state outside the microcomputer is a low voltage detection reset signal from the low voltage detection unit,
The reset signal based on the state inside the microcomputer is a WDT abnormality detection reset signal from the WDT abnormality detection circuit unit,
The low voltage detection unit further outputs a storage clear signal corresponding to a low voltage detection reset signal to the storage circuit unit,
2. The microcomputer reset circuit according to claim 1, wherein the memory circuit unit outputs the reference signal based on the memory clear signal and a reset signal input to a first reset signal input terminal. . The reference signal changes when there is a reset signal input to the first reset signal input terminal when the power supply is not at a low voltage,
3. The microcomputer reset circuit according to claim 2, wherein the microcomputer receives the reference signal and determines that the reset signal input to the first reset signal input terminal is caused by WDT abnormality.   When the reset signal is based on an external state, the microcomputer restarts after the reset is released, and when the reset signal is based on an internal state, the microcomputer stops operating after the reset is released. 4. The microcomputer reset circuit according to claim 1, wherein the microcomputer is shifted to a fail mode.

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