JP2006224436A - Data transfer control means - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To update a compression rate of data for inter-CPU communication corresponding to the data transfer amount to a printer engine, in a dual CPU printer controller that separately has the function of performing a PDL interpretation processing by receiving print data from a host computer and the function of performing color conversion of the data acquired by the PDL interpretation processing to transmit the converted data to a printer engine. <P>SOLUTION: The data transfer control means has in a BusBridge register groups for storing the data amount to be transferred to the printer engine, and is also provided with a means for performing data compression corresponding to the data amount to be transferred to the printer engine by updating the compression rate of the data for inter-CPU communication corresponding to the state of the register groups. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a dual CPU printer controller in which a function of receiving print data from a host computer and performing PDL decoding processing and a function of performing color conversion on the data subjected to PDL decoding processing and transferring the data to a printer engine are separated. The present invention relates to data transfer control means for changing the data compression rate of inter-CPU communication.

With the recent improvement in image quality of printer engines, the processing speed required for printer controllers is required. As a solution to this problem, a general method is to improve the processing speed of digital data by parallel processing using a multiprocessor. However, since it takes a development period and costs, it is difficult to adopt it for peripheral devices such as printers. In view of this, a dual CPU printer controller has been proposed in which two CPUs are mounted, the processing in the printer controller is performed in stages, and data in each stage is transferred to enable parallel processing by a plurality of CPUs. (For example, refer to Patent Document 1 below.)
JP 2000-198240 A

  The function of receiving print data from the host computer and performing PDL decoding processing and the function of converting the data subjected to PDL decoding processing to color conversion and transferring to the printer engine are performed on the output-side bus in the dual CPU printer controller having the function separated. There is a conflict between data transfer to the engine and data transfer between CPUs. At that time, it is necessary to guarantee the data transfer band to the engine side, and at the same time, it is necessary to transfer the data necessary for printing the next page to the CPU. Therefore, efficient data communication between the two is required. SUMMARY An advantage of some aspects of the invention is that it provides a data transfer control unit that can change the compression ratio of data for inter-CPU communication according to the amount of data transferred to a printer engine.

  In order to achieve the above object, an invention relating to the present application has the following configuration (1).

  (1) In a dual CPU printer controller in which the function of receiving print data from a host computer and performing PDL decoding processing and the function of performing color conversion of the data subjected to PDL decoding processing and transferring the data to the printer engine are separated, the printer Based on the result of the measured bus bandwidth, having means for measuring the bus bandwidth when transferring the print data amount to the engine, data compression means for inter-CPU communication, and means for controlling the compression rate of data for inter-CPU communication And a data transfer control means for changing a data compression rate of communication between CPUs.

  In the dual CPU printer controller having the above-described configuration, the function of receiving print data from the host computer and performing PDL decoding processing and the function of performing color conversion on the data subjected to PDL decoding processing and transferring the data to the printer engine are separated. According to the data transfer amount to the printer engine, the data compression rate of communication between CPUs can be changed, and efficient data transfer can be performed.

  According to the present invention, a dual CPU printer controller in which a function of receiving print data from a host computer and performing PDL decoding processing and a function of performing color conversion on the data subjected to PDL decoding processing and transferring the data to the printer engine are separated. Thus, efficient data transfer can be performed.

  Embodiments according to the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing an embodiment of the present system.

  The printer controller 101 is a printer controller of the present invention. The printer controller 101 is mounted on the printer 102 and receives print data from the host computer 103. The print data is usually described in data in a format called a printer description language (PDL) that can be analyzed by the printer 102. Regarding the connection between the printer 102 and the host computer 103, a LAN such as Ethernet (registered trademark) is used in an office environment or the like. As means for independently connecting the information processing apparatus and the printer, there are a parallel interface such as IEEE1284 and a serial interface such as RS232C, USB, and IEEE1394. In the present invention, the means for connecting the printer 102 and the host computer 103 is not limited. As for the host computer 103, for example, a personal computer equipped with Windows (registered trademark) 2000, which is an OS manufactured by Microsoft Corporation, is considered. In the present invention, any apparatus that can generate PDL data that can be analyzed by the printer controller 101 and that can be connected to the printer 101 can be applied to, for example, a digital camera or a PDA.

  The Input I / F 207 is an interface for storing received data in the Memory # 0 201 and transmitting data on the Memory # 0 201 in data transmission / reception with the host computer 104. When the received data is a print job, the CPU # 0 202 manages the job in units of pages and determines a CPU that performs processing in units of pages, or raster data that can be transferred to the printer engine. This is an arithmetic processing unit having image processing means for conversion and means for transferring received data to the CPU # 1 203. The CPU # 1 203 transfers the raster data generated by the CPU # 0 202 to the printer engine in order of pages and transfers raster data to the engine 104 via the engine I / F 211. An arithmetic processing unit having means. Memory # 0 201 and Memory # 1 204 are storage media for storing PDL data and raster data. BusBridge 205 is a medium means for transferring PDL data from CPU # 0 202 to CPU # 1 203, and is an engine. A page register group 206 indicating the amount of data to be transferred to 104 and a data compression mechanism are installed. The engine 104 is a device that prints on paper based on the transferred raster data.

  FIG. 2 shows details of the page register group mounted on the BusBridge 205. The page size register 300 stores the amount of page data after processing by the CPU # 1, that is, the amount of data to be transferred to the engine. This value is calculated by CPU # 1 from the state of Memory # 1 and stored in the page size register 300. The compression rate flag register 301 is a compression rate flag register, and is designed so that a corresponding bit flag is set according to the value stored in the page size register 300. The data compression mechanism in CPU # 0 or BudBridge determines the data compression rate from the state of the compression rate flag register 301.

  FIG. 3 shows a processing flow for carrying out the present invention. Hereinafter, each step will be described.

  1) S401: The CPU # 0 checks whether there is a print job. If there is a print job, the process proceeds to S402.

  2) S402: CPU # 0 checks the compression rate flag register of the page register group mounted on BusBridge. If the value is “0”, it is not necessary to compress data between CPUs, and the process proceeds to S408. If it is not “0”, the process proceeds to S403.

  3) S403: As a method for compressing data for inter-CPU communication, if data compression is performed using the data compression mechanism installed in BusBridge, the process proceeds to S404, and if CPU # 0 performs data compression, the process proceeds to S406. .

  4) S404: Data is transferred from CPU # 0 to BusBridge. Proceed to S405.

  5) S405: Data compression is performed at a compression rate corresponding to the flag bit of the compression rate flag register of the page register group mounted on BusBridge. At that time, data compression is performed using a compression mechanism mounted on BusBridge. The process proceeds to S408.

  6) S406: Data compression is performed at a compression rate corresponding to the flag bit of the compression rate flag register of the page register group mounted on BusBridge. At that time, CPU # 0 performs data compression. The process proceeds to S407.

  7) S407: Data is transferred from CPU # 0 to BusBridge. The process proceeds to S408.

  8) S408: Data is transferred to CPU # 1. The process proceeds to S409.

  9) S409: When CPU # 1 receives the print job from CPU # 0, it proceeds to S410.

  10) S410: CPU # 1 performs color conversion processing. The process proceeds to S411.

  11) S411: As a result of performing the color conversion process in S410, the amount of data to be transferred to the engine is determined. CPU # 1 calculates from the state of SDRAM # 1, and sets the value to the page size register of the page register group mounted on BusBridge. The process proceeds to S412.

  12) S412: The data subjected to the color conversion process in S410 is output to the engine. The process proceeds to S409.

  As described above, according to the present embodiment, the function of receiving the print data from the host computer and performing the PDL decoding process, and the function of performing color conversion on the data subjected to the PDL decoding process and transferring the data to the printer engine are provided. In the separated dual CPU printer controller, the data compression rate of the inter-CPU communication can be changed according to the data amount of data transferred to the printer engine.

Embodiment of a system including data transfer control means in a dual CPU printer controller of the present invention The figure which shows the example of the flag register group of a present Example The flowchart figure which shows the example of the data transfer control means in the CPU printer controller of a present Example.

Explanation of symbols

101 Printer Controller 102 Printer 103 Host Computer 104 Engine 201 Memory # 0
202 CPU # 0
203 CPU # 1
204 Memory # 1
205 BusBridge
206 Page register group 207 Data compression mechanism 208 Input I / F
209 Rom # 0
210 Rom # 1
211 Engine I / F
300 Page data size register 301 Compression rate flag register

Claims (4)

  Printing on the printer engine using a dual CPU printer controller that separates the function of receiving print data from the host computer and performing PDL decoding processing, and the function of color-converting and transferring the PDL decoding data to the printer engine It has means for measuring the bus bandwidth when transferring the amount of data, data compression means for communication between CPUs, and means for controlling the compression rate of data for communication between CPUs, and between CPUs based on the result of the measured bus bandwidth A data transfer control means for changing a data compression rate of communication.   2. The data transfer control means according to claim 1, wherein data compression of inter-CPU communication data is performed by a CPU that performs input processing and PDL decoding processing.   2. The data transfer control means according to claim 1, wherein data compression of data for inter-CPU communication is performed by an inter-CPU data transfer bridge.   2. The data transfer control means according to claim 1, wherein the data compression rate of inter-CPU communication is performed by an inter-CPU data transfer bridge.

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