JP2006222194A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit which requires no mask for interconnections and can reduce the time and cost of manufacturing for the limited production of diversified products. <P>SOLUTION: The integrated circuit comprises a cell region 3 consisting of a plurality of cells 2 formed on a substrate 1 and an interconnection region 4 formed on the cell region 3. A terminal 7 of each cell 2 of the cell region 3 is connected to a wiring pattern 8 of the interconnection region 4. The wiring pattern 8 is formed in the interconnection region 4 by using an ink containing a conductive material. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an integrated circuit suitable for a gate array type semiconductor integrated circuit.

As shown in FIG. 8, an example of a conventional gate array includes a cell region 82 in which cells 81 are formed in a lower layer on the surface of a substrate (silicon substrate), and a cell formed in an upper layer on the surface of the substrate. A wiring area for wiring between 81, an input / output buffer area 83 in which an input / output buffer is arranged, and a plurality of input / output pads 84 for connection to the outside are provided.
On the other hand, conventionally, in a semiconductor device configured by mounting a plurality of chips on one main substrate, the plurality of chips are connected by wiring having a line width of about 10 μm without performing metal sputtering or etching. The thing is known (refer patent document 1). The wiring is formed by applying an ink containing a conductive material on a semiconductor substrate and a chip adapter using an ink jet printer.

Incidentally, in the conventional gate array as shown in FIG. 8, cells are formed in advance on the lower layer of the surface of the substrate, and the wiring inside the cell and the wiring between the cells are arranged on the substrate according to the desired circuit. In the upper layer on the surface, the metal is used. For this reason, in the conventional gate array, a mask of a metal layer corresponding to the desired circuit is required for each desired circuit.
As described above, the conventional gate array has a property that a cell is wired in a wiring area in accordance with a desired circuit for each circuit. On the other hand, in the wiring, if an ink containing a conductive material is used like the wiring between a plurality of chips of the semiconductor device described in Patent Document 1, a mask is not required and a small variety of products are produced. In some cases, time and cost can be reduced.
Japanese Patent Laid-Open No. 2004-22907

  The present invention has been made under the background as described above, and its object is to eliminate the need for a mask for wiring in a semiconductor integrated circuit such as a gate array and to produce a small variety of products. Another object of the present invention is to provide an integrated circuit capable of reducing time and cost.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
In other words, the first invention is a gate array type integrated circuit comprising a cell region comprising a plurality of cells provided on a substrate and a wiring region formed on the cell region, wherein the cell The terminal of each cell in the region is configured to be connectable to the wiring pattern in the wiring region, and the wiring pattern in the wiring region is formed using ink containing a conductive material in the wiring region.

  According to a second aspect of the present invention, a cell region including a plurality of cells provided on a substrate, an input / output buffer region including a plurality of buffers provided on the substrate, and a wiring region formed on the cell region are provided. A gate array type integrated circuit comprising input / output pads, wherein terminals of each cell in the cell region are configured to be connectable to a wiring pattern in the wiring region, and each buffer in the input / output buffer region. The terminal of the wiring region is configured to be connectable to the input / output pad, the wiring pattern of the wiring region is formed using ink containing a conductive material in the wiring region, and the input / output pad is connected to the input / output pad. An ink containing a conductive material is formed on the output buffer region.

  A third invention is a gate array type integrated circuit comprising a cell region composed of a plurality of cells provided on the entire surface of a substrate and a wiring region formed on the cell region, wherein the cell A terminal of each cell in the region is configured to be connectable to a wiring pattern in the wiring region, and the wiring pattern in the wiring region is formed using an ink containing a conductive material in the wiring region, and the cell region A predetermined part of the plurality of cells is configured as an input / output buffer, and an input / output pad is formed in the wiring region above the cell region using an ink containing a conductive material, Since the regions are arranged in a regular arrangement on the entire surface of the substrate, chips of any size and shape can be formed from the same substrate.

  According to a fourth invention, in the first, second, or third invention, the wiring region includes a plurality of wiring layers, and a wiring pattern of each wiring layer is coated with ink containing a conductive material by an ink jet technique. The insulating layer between the wiring layers is formed by applying an ink containing an insulating material by an ink jet technique, and the conductive portion that conducts between the wiring layers is conductive by the ink jet technique. It is formed by applying an ink containing a conductive material.

A fifth invention is an integrated circuit in which a plurality of integrated circuits according to any one of claims 1 to 4 are formed on the same substrate, and the plurality of integrated circuits are Wiring is performed on the substrate, and the wiring is formed by applying ink containing a conductive material on the substrate.
According to a sixth aspect of the present invention, there is provided a first general-purpose circuit or a unique integrated circuit formed on a substrate, and the first integrated circuit formed on the substrate. The wiring between the first integrated circuit and the second integrated circuit is formed by applying an ink containing a conductive material on the substrate.

A seventh invention is an integrated circuit in which a desired circuit is formed on a substrate, and a passive element necessary for the desired circuit is formed at a desired position on the substrate using an ink jet technique. I did it.
According to the present invention having such a configuration, a wiring mask is not required in a semiconductor integrated circuit such as a gate array, and time and cost can be reduced when manufacturing a small variety of products.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a plan view showing the configuration of the first embodiment of the integrated circuit of the present invention, FIG. 2 is a sectional view of the cell region and wiring region thereof, and FIG. 3 is a sectional view of the vicinity of the input / output pad.
As shown in FIGS. 1 and 2, the first embodiment includes a cell region 3 in which a plurality of cells 2 are arranged in an array form below the surface of a substrate 1 such as a semiconductor substrate, and a substrate. An input / output buffer region 6 in which a plurality of buffer circuits are formed below the surface of 1, a wiring region 4 formed to perform wiring between the cells 2 on the upper surface of the substrate 1, and the outside It is a gate array type integrated circuit having a plurality of input / output pads 5 for connection.

Each cell 2 in the cell region 3 is formed of a plurality of MOS transistors or the like as shown in FIG. 2, and the plurality of MOS transistors are formed in advance on the substrate 1 using a conventional technique. Further, on each cell 2, as shown in FIG. 2, terminals 7 such as input / output terminals of each cell 2 are previously formed of metal by a lithography technique.
In the first embodiment, wiring between the cells 2 is performed in the wiring region 4 in accordance with a desired circuit. This wiring (connection) is performed by applying ink containing a conductive material using a so-called inkjet technique. Realized.

That is, the wiring region 4 is composed of a plurality of wiring layers as shown in FIG. 2, and the wiring pattern 8 of each wiring layer uses ink containing a conductive material, for example, alternately discharging and drying the ink. It was formed by repeating. Here, an ink jet printer or the like is used for discharging the ink.
Further, the insulating film (insulating layer) between the wiring layers was formed by alternately repeating the discharge and drying of the insulating ink. Further, the conductive portion 9 that conducts between the wiring layers was formed by alternately repeating discharge and drying of ink containing a conductive material.

As shown in FIG. 3, a buffer circuit 10 made of a transistor is formed in the input / output buffer region 6. In the buffer circuit 10, a terminal 11 is previously formed of metal by a lithography technique.
As shown in FIG. 3, an input / output pad 5 connected to the terminal 11 is provided on the buffer circuit 5. As with the wiring pattern 8, the input / output pad 5 was formed by alternately discharging and drying ink containing a conductive material.

Further, the connection between the input / output pad 5 and the terminal 11 of the input / output buffer circuit 10 is performed by alternately repeating ejection and drying of ink containing a conductive material. Further, the insulating film 14 shown in FIG. 3 was formed by alternately repeating the discharge and drying of the insulating ink.
As described above, according to the first embodiment, the wiring between the cells 2 is realized by using the ink containing the conductive material according to the desired circuit, so that a wiring mask is not necessary. In addition, time and cost can be reduced when making a small variety of products.

  In the first embodiment, since the input / output pad 5 is realized in the input / output buffer region 6 using ink containing a conductive material, the conventional input / output pad region is not required, and the wafer is removed. Can be effectively used (see FIG. 8).

(Second Embodiment)
FIG. 4 is a plan view showing the configuration of the second embodiment of the integrated circuit of the present invention.
This second embodiment is a gate array type integrated circuit, and as shown in FIG. 4, a plurality of cells 2a are laid out in an array on the entire lower surface of a substrate (wafer) 1. A cell region 3a, a wiring region formed for wiring between the cells 2a above the surface of the substrate 1, and a plurality of input / output pads 5a provided around and in the cell region 3a. It has. In the prior art gate array, the layout of the cell area and the input / output buffer area is different, so it is necessary to prepare a chip as shown in FIG. 8 corresponding to the scale of the integrated circuit. Therefore, the types of substrates (wafers) necessary for realizing different types of chips have been manufactured.

The cell region 3a is configured in the same manner as the cell region 3 shown in FIG. 2, and each cell 2a in the cell region 3a is configured in the same manner as each cell 2 in the cell region 3 shown in FIG.
Further, the wiring area was configured in the same manner as the wiring area 4 shown in FIG. That is, the wiring area is composed of a plurality of wiring layers like the wiring area 4 shown in FIG. 2, and the wiring pattern of each wiring layer uses ink containing a conductive material, for example, discharging and drying the ink. It was formed by repeating alternately.

Further, the insulating film (insulating layer) between the wiring layers was formed by alternately repeating the discharge and drying of the insulating ink. Furthermore, the conductive portion that conducts between the wiring layers was formed by alternately repeating ejection and drying of ink containing a conductive material.
Of the cells 2a in the cell region 3a, the cell 2a below the input / output pad 5a is formed as an input / output buffer circuit. In addition, the input / output pad 5a is formed by alternately discharging and drying ink containing a conductive material, like the input / output pad 5 shown in FIG. Further, the wiring between the input / output pad 5a and the input / output buffer circuit is also performed by alternately repeating the ejection and drying of ink containing a conductive material.

  As described above, in the second embodiment, the wiring between the cells 2a is realized by using ink containing a conductive material according to a desired circuit, so that a wiring mask is not necessary. In addition, time and cost can be reduced when making a small variety of products. In addition, since the cell regions under the wiring layer are regularly arranged on the entire surface of the substrate (wafer), if one kind of substrate (wafer) is prepared, various kinds of integrated circuit products of arbitrary sizes and shapes can be obtained. Can be made. Thereby, the cost for manufacturing the substrate (wafer) and the cost and time for manufacturing various kinds of integrated circuits can be reduced.

  In the second embodiment, of the cells 2a in the cell region 3a, the cell 2a below the input / output pad 5a is formed as an input / output buffer circuit, and the input / output pad is formed on the input / output buffer circuit. Is realized using an ink containing a conductive material. For this reason, since the input / output pads can be provided at arbitrary positions, chips of any size and shape can be created.

(Third embodiment)
FIG. 5 is a plan view showing the configuration of the third embodiment of the integrated circuit of the present invention.
In the third embodiment, as shown in FIG. 5, a plurality of integrated circuits 12 related to each other are formed on the same substrate 1, and wiring (connection) 13 between the plurality of integrated circuits 12 is On the board | substrate 1, it was made to apply | coat the ink containing the electroconductive material using the inkjet technique.
That is, the wiring 13 is formed on the substrate 1 by using ink containing a conductive material, for example, by alternately repeating discharge and drying of the ink.

Here, as the related integrated circuit 12, the gate array type integrated circuit of the first embodiment shown in FIG. 1 or the second embodiment shown in FIG. 4 is preferable.
Further, as a combination of the integrated circuits 12 which are related to each other, there are cases where a plurality of CPUs and a plurality of memory chips corresponding thereto are used. Wiring into one chip.

In such a third embodiment, first, a large number of circuits each including a plurality of mutually related integrated circuits 12 as a unit are formed on a wafer (substrate). Next, wiring 13 between the related integrated circuits 12 is performed on the wafer using ink containing a conductive material. After that, the wafer is diced by using the circuit where the wiring is completed as one unit to form one chip.
According to the third embodiment having such a configuration, a plurality of related integrated circuits can be formed on a wafer to easily form a unit circuit, thereby reducing design costs and chip mounting costs. It becomes possible.

Note that the third embodiment can be applied as follows. That is, when a large-scale integrated circuit is configured by combining chips on a wafer, only a chip that operates normally in a probe test in a wafer state is selected and wiring is performed using ink containing a conductive material. Like that.
In this way, in the semiconductor process, the yield generally decreases as the chip area increases, but the influence can be reduced and the yield can be improved.

(Fourth embodiment)
FIG. 6 is a plan view showing the configuration of the fourth embodiment of the integrated circuit of the present invention.
In the fourth embodiment, as shown in FIG. 6, a general-purpose integrated circuit such as a CPU 15 and a memory 16 and an analog circuit such as an A / D conversion circuit (ADC) 17 are formed on the same substrate 1. Thus, an integrated circuit having a unique layout and an integrated circuit including the gate array 18 are provided.
Integrated circuits such as the CPU 15, the memory 16, and the A / D conversion circuit 17 are configured by lithography techniques as in the past. Further, the gate array 18 is configured in the first embodiment shown in FIG. 1 or the third embodiment shown in FIG.

Further, the wiring 19 between these integrated circuits is formed on the substrate 1 by applying ink containing a conductive material using an ink jet technique. That is, the wiring 19 is formed on the substrate 1 by using an ink containing a conductive material, for example, by alternately discharging and drying the ink.
According to the fourth embodiment having such a configuration, the effects of the first embodiment or the second embodiment can be realized, and wiring between the integrated circuits can be easily performed.

(Fifth embodiment)
FIG. 7 is a plan view showing the configuration of the fifth embodiment of the integrated circuit of the present invention.
In the fifth embodiment, as shown in FIG. 7, a desired circuit 20 is integrated on the same substrate 1. Then, passive elements necessary for the circuit 20 are formed at desired positions on the substrate 1 by using a so-called inkjet technique.
A capacitor 21 is shown in FIG. 7 as an example of a passive element. The capacitor 21 includes an electrode 22 and an electrode 23, and an insulator 24 is sandwiched therebetween. The electrodes 22 and 23 are formed by using an ink containing a conductive material, for example, by alternately discharging and drying the ink. The insulator 24 is formed by alternately repeating the discharge and drying of the insulating ink. Further, the wiring between the electrodes 22 and 23 and the circuit 20 is performed by alternately repeating discharge and drying of ink containing a conductive material.

According to the fifth embodiment having such a configuration, there is no need to externally attach a passive element, and the mounting area of the passive element can be reduced.
Further, according to the fifth embodiment, if a decoupling capacitor is formed as a passive element, it can be mounted from the integrated circuit in the shortest time, so that the noise reduction effect is great.
Furthermore, according to the fifth embodiment, radiation noise from the chip can be shielded by forming a capacitor on the entire top surface of the chip.

It is a top view which shows the structure of 1st Embodiment of this invention. It is sectional drawing of the cell area | region and wiring area | region of 1st Embodiment. It is sectional drawing of the vicinity of the input / output pad of 1st Embodiment. It is a top view which shows the structure of 2nd Embodiment of this invention. It is a top view which shows the structure of 3rd Embodiment of this invention. It is a top view which shows the structure of 4th Embodiment of this invention. It is a top view which shows the structure of 5th Embodiment of this invention. It is a top view which shows the structure of the conventional gate array.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Substrate, 2, 2a ... Cell, 3, 3a ... Cell area, 4, 4a ... Wiring area, 5 ... I / O pad, 6 ... I / O buffer area, 8 ... Wiring pattern, 9 ... Conducting part

Claims (7)

A gate array type integrated circuit comprising a cell region composed of a plurality of cells provided on a substrate and a wiring region formed on the cell region,
The terminal of each cell in the cell region is configured to be connectable with the wiring pattern in the wiring region,
The integrated circuit according to claim 1, wherein the wiring pattern of the wiring region is formed using ink containing a conductive material in the wiring region. A cell region comprising a plurality of cells provided on the substrate; an input / output buffer region comprising a plurality of buffers provided on the substrate; a wiring region formed on the cell region; and an input / output pad; A gate array type integrated circuit comprising:
A terminal of each cell in the cell region is configured to be connectable with a wiring pattern in the wiring region, and a terminal of each buffer in the input / output buffer region is configured to be connectable to the input / output pad,
The wiring pattern of the wiring region is formed using an ink containing a conductive material in the wiring region, and the input / output pad uses an ink containing a conductive material on the input / output buffer region. An integrated circuit characterized by being formed. A gate array type integrated circuit comprising a cell region comprising a plurality of cells provided on the entire surface of a substrate, and a wiring region formed on the cell region,
The terminal of each cell in the cell region is configured to be connectable with the wiring pattern in the wiring region,
The wiring pattern of the wiring region is formed using an ink containing a conductive material in the wiring region,
A predetermined part of the plurality of cells in the cell region is configured as an input / output buffer, and an input / output pad is formed in the wiring region above the cell region using ink containing a conductive material. ,
Since the cell regions are arranged in a regular array on the entire surface of the substrate, chips having an arbitrary size and shape can be formed from the same substrate.   The wiring region is composed of a plurality of wiring layers, and the wiring pattern of each wiring layer is formed by applying ink containing a conductive material by ink jet technology, and the insulating film between the wiring layers is insulated by ink jet technology. The conductive portion that conducts conduction between the wiring layers is formed by applying ink containing a conductive material by ink-jet technology. The integrated circuit according to claim 1, 2 or 3. An integrated circuit in which a plurality of integrated circuits according to any one of claims 1 to 4 are formed on the same substrate,
Wiring the plurality of integrated circuits on the substrate;
The integrated circuit according to claim 1, wherein the wiring is formed by applying an ink containing a conductive material on the substrate. A first integrated circuit having a general purpose or layout specific formed on a substrate;
A second integrated circuit according to any one of claims 1 to 4 formed on the substrate;
The wiring between the first integrated circuit and the second integrated circuit is formed by applying an ink containing a conductive material on the substrate. An integrated circuit in which a desired circuit is formed on a substrate,
2. An integrated circuit, wherein a passive element necessary for the desired circuit is formed at a desired position on the substrate by using an ink jet technique.

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