JP2006217454A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for preventing signal shrinkage on the negative side with respect to the semiconductor integrated circuit which uses a negative power source generated by a charge pump circuit and has a video output circuit capable of outputting a signal with a positive/negative voltage. <P>SOLUTION: In the semiconductor integrated circuit including the charge pump circuit for generating a negative power source voltage, an input part for biasing an average level of video signals by 0V, and the video signal output circuit, an output of an average level detection circuit for detecting an average value of video signal outputs and an output of a lower limit level detection circuit for detecting a lower limit level of video signal outputs are determined, and a 0V bias circuit is selected at the time of input of a standard video signal, and a clamp bias circuit is selected at the time of input of a high-luminance video signal, whereby distortion on the negative side of an output signal is prevented even at the time of input of the high-luminance video signal to output a normal video signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit that uses a negative power source generated by a charge pump circuit and has a video signal output circuit capable of outputting a signal positively or negatively and prevents negative signal shrinkage. .

  2. Description of the Related Art Conventionally, semiconductor integrated circuits that output analog signals of video signals include semiconductor integrated circuits that have positive and negative power supplies and drive a load with 0V average. Among the semiconductor integrated circuits, Patent Document 1 proposes an integrated circuit that incorporates a circuit that generates a negative power supply from a single positive power supply voltage and can output a signal positively or negatively. Furthermore, in recent years, the number of video output has been increased by adapting to the input of television S terminal, D terminal, etc., and the power supply voltage has been reduced to 2.7 V or less due to the portable products.

  In addition, there has been a proposal regarding the restriction of an input signal in a semiconductor integrated circuit device including an input circuit unit that receives an external input signal, and a clip circuit and a clamp circuit that prevent the input signal from falling below the substrate potential of the semiconductor integrated circuit. Japanese Patent Laid-Open No. 2004-133867 proposes an integrated circuit having a signal input at the input unit.

  A conventional semiconductor integrated circuit that incorporates a negative power supply generation circuit and can output positive and negative signals will be described below.

  FIG. 5 shows a conventional semiconductor integrated circuit.

  In FIG. 5, reference numeral 1 denotes a resistor, 2 denotes an output amplifier, 3 denotes a negative power supply generation charge pump circuit, and 10 denotes a semiconductor integrated circuit including a resistor 1, an output amplifier 2, and a negative power supply generation charge pump circuit 3. 21 is an input signal source, 22 is an input capacity, 23 is a flying capacity, 24 is a charge capacity, 25 is a load, and 26 is a negative power source impedance.

  The following operation is described for the semiconductor integrated circuit configured as described above.

  The input signal DC-cut by the input capacitor 22 is biased at an average level of 0 V by the resistor 1 connected between the input terminal and GND. The output amplifier 2 uses VSS generated by the negative power supply generation charge pump circuit 3 as a negative power supply, amplifies the signal biased to 0V by the resistor 1 on the basis of 0V, and drives the load 25.

  FIG. 6A shows an example of signal waveforms at the input / output pins when a standard video signal is input. Here, the output amplifier 2 is an amplifier capable of outputting up to VSS + Vsat on the negative side by collector-collector connection, and the gain is 6 dB. The input signal is biased by 0V, and the output signal also has an average level of 0V and outputs twice the amplitude of the input signal.

As an example, when Vsat = 0.3V, VSS = −2.5V, negative power supply impedance 20Ω, and current I flowing into VSS is 10 mA, VSS + Vsat = −2.5 + 20 × 10e−3 + 0.3V = −2.0V Become. Since the output SYNC voltage of the 0V average white 130% video signal is about -2V, white 130% is a limit value at which normal output is possible when the negative power supply fluctuation due to the signal current is ignored.
Japanese Patent Laid-Open No. 7-106963 Japanese Patent Laid-Open No. 5-299959

  However, in the above configuration, when a higher-luminance video signal is input and the gain multiple of the SYNC voltage of the input signal is lower than VSS + Vsat, the output signal causes SYNC contraction. FIG. 6B shows an example of the waveform of the input / output pins when a video signal having a higher luminance than that in FIG. 6A is input. The input signal is biased by 0V and the amplitude of the input signal is doubled by the output amplifier, but the SYNC portion of the output signal is shrunk due to the saturation of the output NPN transistor of the output amplifier. This phenomenon of SYNC shrinkage may cause the video signal to be out of synchronization on the television side, which is a problem.

  Also, due to recent trends, there is an increase in current consumption I due to multiple output amplifier operation due to lower power supply voltage and multi-channel video output, and non-ideal negative power supply impedance increases due to differences in mounting patterns In some cases, it may be impossible to obtain a sufficiently low voltage value for a video signal for which VSS is assumed. At that time, prevention of SYNC shrinkage becomes a major issue in semiconductor integrated circuits that output video signals.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described conventional problems and to provide a semiconductor integrated circuit that prevents a SYNC contraction in an output amplifier 2 and outputs a normal signal.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes a charge pump circuit that generates a negative power supply voltage, an input unit that biases the average level of the video signal at 0V, and the average level of the video signal that is output on the basis of 0V. In a semiconductor integrated circuit having a video signal output circuit, an average level detection circuit for detecting the average value of the video signal output, a 0 V bias circuit for outputting the detection result, an average level determination circuit for comparing and determining the average level, and Lower limit level detection circuit that detects the lower limit level of video signal output, clamp bias circuit that outputs the detection result, lower limit level determination circuit that compares and determines the lower limit level, average level determination result and lower limit level determination result When a standard video signal is input, a 0V bias circuit is selected. When a high luminance video signal is input, a clamp bias circuit is selected. By configuring the level control switch that provides optimal bias circuit to force the circuit, high luminance when a video signal input also prevent distortion of the negative-side output signal, and outputs the normal video signal.

  The semiconductor integrated circuit according to the present invention has the above-described configuration and reduces the SYNC contraction of the output even when a high-luminance video signal is input or when a sufficiently low voltage is not generated with respect to an input signal assumed to be VSS. Can be prevented.

  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

  In FIG. 1, 1 is a resistor, 2 is an output amplifier, 3 is a negative power generation charge pump circuit, 11 is an average level detection circuit, 12 is a 0V bias output circuit, 13 is a lower limit level detection circuit, 14 is a clamp bias output circuit, 15 is a level control circuit, 16 is a level control switch, 17 is a charge capacity, 10 is a resistor 1, an output amplifier 2, a negative power generation charge pump circuit 3, an average signal level detection circuit 11, a 0V bias output circuit 12, and a lower limit signal level. The semiconductor integrated circuit includes a detection circuit 13, a clamp bias output circuit 14, a level control circuit 15, a level control switch 16, and a charging capacitor 17. 21 is an input signal source, 22 is an input capacity, 23 is a flying capacity, 24 is a charge capacity, and 25 is a load.

  The operation of the semiconductor integrated circuit 10 configured as described above will be described below.

  When a video signal is input, the resistor 1 connected between the input terminal and GND biases the average level of the signal at 0 V, and the output amplifier 2 (gain is 6 dB) amplifies the amplitude twice. The signal amplified by the output amplifier 2 is detected by the average level detection circuit 11 and the lower limit level detection circuit 13. The average level of the signal is output from the output of the average level detection circuit 11, and the lower limit level of the signal is output from the lower limit level detection circuit 13. The average level and the lower limit level of the signal are determined by the level control circuit 15, and either the 0V bias circuit 12 or the clamp bias circuit 14 is selected by the level control switch 16. When the standard video signal is input, even if the average level of the output signal is 0V, the lower limit level is equal to or higher than VSS + Vsat. Therefore, the level control switch 16 selects the 0V bias circuit by the level control circuit 15, and the average of the output signal The level is also 0V. When a high brightness video signal is input, if the average level of the output signal is 0V, the lower limit level is less than VSS + Vsat and the SYNC part is shrunk, so the level control switch 16 is set so that the lower limit level of the signal is greater than VSS + Vsat. When the clamp bias circuit is selected, the lower limit level of the output signal becomes VSS + Vsat or higher, and a normal signal is output. However, at this time, the average level of the output signal is higher than 0V.

  FIG. 2A shows an example of signal waveforms at the input / output pins when a standard video signal is input. The video input signal is biased at 0 V and then detected by the average level detection circuit 11 and the lower limit level detection circuit 13. The average level and the lower limit level are determined by the level control circuit 15, and even if the average level of the output signal is set to 0V, the lower limit level is equal to or higher than VSS + Vsat. Therefore, the 0V bias circuit is selected by the level control switch 16. The output signal also has an average level of 0V and outputs twice the amplitude of the input signal.

  FIG. 2B shows an example of signal waveforms at the input / output pins when a high-luminance video signal is input. The average level and the lower limit level of the output video signal are determined by the level control circuit 15. If the average level of the output signal is set to 0V, the lower limit level becomes VSS + Vsat or less and the SYNC part shrinks, so the lower limit level of the output signal is more than VSS + Vsat. Therefore, the level shift switch 16 selects the clamp bias circuit 14. The output bias of the clamp bias circuit 14 is set so that the lower limit level of the output signal is equal to or higher than VSS + Vsat, and outputs twice the amplitude of the input signal without shrinking the SYNC. At this time, the average level of the signal at the input / output pin is higher than 0V.

  As described above, according to the present embodiment, a high-brightness video signal in which SYNC is contracted in the conventional circuit example can be output without SYNC contraction.

  FIG. 3 shows a circuit diagram for specifically realizing the configurations of the average level detection circuit 11, the lower limit level detection circuit 13, and the level control circuit 15. FIG. 4 shows voltage waveforms at respective points in FIG. Hereinafter, description will be given with reference to the drawings.

  The average level voltage value of the video signal is detected by the average level detection circuit 11 composed of a low-pass filter after the signal amplified by the output amplifier 2 is output (point 101). The average level of the signal is compared with Vb (for example, set to -0.1V) by the average level determination circuit 31. When the average level of the signal is higher than Vb, Lo is obtained. When the average level of the signal is lower than Vb, Hi is obtained. Is output (point 102). The lower limit level voltage value of the video signal is detected by the lower limit level detection circuit 13, and the lower limit voltage of the signal is held by the charge / discharge capacitance 32 (point 103). The lower limit level of the signal is compared with VSS + Va (for example, Va: set to 0.5V) by the lower limit level determination circuit 33. When the lower limit level of the signal is higher than VSS + Va, Lo is set. When the lower limit level of the signal is lower than VSS + Va, Hi is set. Is output (point 104). When the average level determination output (point 102) is Lo and the lower limit level determination output (point 104) is Lo by the level control circuit 15, the level control switch 16 selects the 0V bias circuit 12. When Hi is output at the lower limit level determination output (point 104), the level control switch 16 switches from the 0V bias circuit 12 to the clamp bias circuit 14. When Hi is output at the average level determination output (point 102), the level control switch 16 switches from the clamp bias circuit 14 to the 0V bias circuit 12. When the level control switch 16 selects the 0V bias circuit 12, the output signal is output so that the average level is 0V, and is driven by the load 25. When the level control switch 16 selects the clamp bias circuit 14, the output signal is output so that the lower limit level is equal to or higher than VSS + Vsat, and the load 25 is driven (point 105).

  As described above, according to the present embodiment, when the standard video signal is input, the 0 V bias circuit 12 operates, and when the high luminance video signal is input, the clamp bias circuit 14 operates. If the output bias (VSS + Va) of the clamp bias circuit 14 is set so that the SYNC voltage of the output signal becomes equal to or higher than VSS + Vsat when the clamp bias is activated, the signal dynamic range that can be operated with 0V bias without considering SYNC compression is widened. . In addition, since the clamp voltage can be set from the VSS voltage value, there is no need to consider fluctuations in the power supply voltage and variations in the negative power supply. Further, since the output signal is detected and the output signal level is adjusted, the input / output DC offset can be compensated, and the versatility is expanded.

  As described above, the present invention is useful for a semiconductor integrated circuit using a negative power source generated by a charge pump circuit and having a video signal output circuit capable of positive / negative output.

Configuration diagram of a semiconductor integrated circuit in an embodiment of the present invention The figure which shows the signal waveform of the input-output pin in embodiment of this invention Configuration diagram of a specific semiconductor integrated circuit for realizing an embodiment of the present invention The figure which shows the voltage waveform of each point in embodiment of this invention Configuration diagram of a semiconductor integrated circuit in an embodiment of a conventional example The figure which shows the signal waveform of the input / output pin in embodiment of a prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Resistance 2 Output amplifier 3 Negative power source generation charge pump circuit 10 Semiconductor integrated circuit 11 Average level detection circuit 12 0V bias circuit 13 Lower limit level detection circuit 14 Clamp bias circuit 15 Level control circuit 16 Level control switch 17 Charging capacity 21 Input signal source 22 Input capacity 23 Flying capacity 24 Charging capacity 25 Load 26 Negative power supply impedance 31 Average level determination circuit 32 Charge / discharge capacity 33 Lower limit level determination circuit 101 Average level detection point 102 Average level determination output 103 Lower limit level detection point 104 Lower limit level determination output 105 level Control judgment output

Claims (1)

In a semiconductor integrated circuit having a charge pump circuit for generating a negative power supply voltage, an input unit for biasing the average level of the video signal at 0V, and a video signal output circuit for outputting the average level of the video signal on the basis of 0V. An average level detection circuit for detecting an average value, a 0 V bias circuit for outputting the detection result, an average level determination circuit for comparing and determining the average level,
A lower limit level detection circuit for detecting the lower limit level of the video signal output, a clamp bias circuit for outputting the detection result, a lower limit level determination circuit for comparing and determining the lower limit level,
Level control that provides the optimum bias circuit for the video signal output circuit by selecting the 0V bias circuit when the standard video signal is input and the clamp bias circuit when the high-brightness video signal is input based on the average level determination result and the lower limit level determination result A semiconductor integrated circuit characterized by comprising a switch to prevent a negative distortion of an output signal even when a high-luminance video signal is input and to output a normal video signal.

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