JP2006217106A - Class d amplifier - Google Patents
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Abstract
Description
本発明は、PWM方式等の矩形波に基づきオーディオ信号を出力するD級増幅器に係り、特に、起動時、停止時及びスタンバイ状態からの復帰時に、出力のAC結合コンデンサに流れる突入電流によって発生するポップノイズを防止する対策を施したD級増幅器に関するものである。 The present invention relates to a class D amplifier that outputs an audio signal based on a rectangular wave such as a PWM method, and is generated by an inrush current flowing through an output AC coupling capacitor, particularly at startup, stop, and return from a standby state. The present invention relates to a class D amplifier that has taken measures to prevent pop noise.
増幅器では電源投入時等の過渡状態において出力信号に急激な変動が起こる。特に、オーディオアンプでは、この急激な変動はポップノイズと言われる不快なノイズとなって現れる。そこで、一般的には増幅器の出力とスピーカとの間にミュート回路を設け、増幅器が定常状態になるまでの期間、スピーカを遮断もしくは接地している。 In an amplifier, a sudden change occurs in the output signal in a transient state such as when the power is turned on. Particularly in an audio amplifier, this sudden fluctuation appears as an unpleasant noise called pop noise. Therefore, in general, a mute circuit is provided between the output of the amplifier and the speaker, and the speaker is cut off or grounded until the amplifier reaches a steady state.
また、図4の従来例1に示すように、ハイサイドドライブ用、ローサイドドライブ用のトランジスタM1,M2の電源側に直列にミュートトランジスタM9を接続し、電源VDDの投入後、キャパシタC5と抵抗R3からなる時定数回路により、このミュートトランジスタM9のオン抵抗を徐々に下げていくことで、ポップノイズを低減させる方式もあった(例えば、特許文献1参照)。図4において、SPはスピーカ、C1はAC結合コンデンサ、L1はローパスフィルタ用インダクタ、C2はローパスフィルタ用コンデンサ、1は音声信号をPWM変調して出力するPWM変調回路である。なお、出力トランジスタM1,M2の接地側に同様にミュートトランジスタを接続して、電源投入時にそのオン抵抗を徐々にさげてポップノイズを低減させる方式もあった。 Further, as shown in Conventional Example 1 in FIG. 4, a mute transistor M9 is connected in series to the power supply side of the high-side drive and low-side drive transistors M1 and M2, and after the power supply VDD is turned on, the capacitor C5 and the resistor R3 are connected. There is also a method of reducing pop noise by gradually reducing the on-resistance of the mute transistor M9 by a time constant circuit consisting of (see, for example, Patent Document 1). In FIG. 4, SP is a speaker, C1 is an AC coupling capacitor, L1 is a low-pass filter inductor, C2 is a low-pass filter capacitor, and 1 is a PWM modulation circuit for PWM-modulating an audio signal and outputting it. There is also a method in which a mute transistor is similarly connected to the ground side of the output transistors M1 and M2 to reduce pop noise by gradually reducing the on-resistance when the power is turned on.
さらに、図5の従来例2に示すように、電源投入時には、制御回路2によりスイッチSW1をオフ、SW2をオンにして、AC結合コンデンサC1を出力基準電圧回路3で発生した電圧によりバッファアンプ4で充電し、安定動作領域まで充電が完了した後、制御回路2によりスイッチSW1をオン、SW2をオフにして、PWMアンプ5に切り替え、ポップノイズを低減させる方式もあった(例えば、特許文献2参照)。
Further, as shown in Conventional Example 2 of FIG. 5, when the power is turned on, the switch SW1 is turned off and the switch SW2 is turned on by the control circuit 2, and the AC coupling capacitor C1 is supplied to the
しかし、図4で説明したような、ハイサイドドライブ用、ローサイドドライブ用のトランジスタM1,M2の電源側もしくは接地側に直列にミュートトランジスタM9を接続し、電源投入後、このミュートトランジスタM9のオン抵抗を徐々に下げていく方式では、このミュートトランジスタM9に電力損失を生じるため、効率を上げるためにはそのミュートトランジスタM9のオン抵抗をトランジスタM1,M2のオン抵抗よりも充分低くする必要があり、ミュートトランジスタM9が非常に大きなものになり、集積化してもチップサイズが増大しコストアップになる。さらに、電源を急激に立ち上げた場合、瞬間的にミュートトランジスタM9のゲート電位が下がり、タイミングによってはポップノイズを抑えきることが出来ない。 However, the mute transistor M9 is connected in series to the power supply side or the ground side of the high-side drive and low-side drive transistors M1 and M2 as described with reference to FIG. In the method of gradually lowering the power, loss occurs in the mute transistor M9. Therefore, in order to increase the efficiency, it is necessary to make the on-resistance of the mute transistor M9 sufficiently lower than the on-resistances of the transistors M1 and M2. The mute transistor M9 becomes very large, and even if integrated, the chip size increases and the cost increases. Further, when the power supply is suddenly turned on, the gate potential of the mute transistor M9 instantaneously drops, and pop noise cannot be suppressed depending on the timing.
また、図5で説明したような、バッファアンプ4とPWMアンプ5を切り替える方式では、バッファアンプ4の出力電圧の中点とPWMアンプ5の出力電圧の中点を一致させる必要があり、誤差分がポップノイズとなる。よって、製造上のバラツキ等によりバッファアンプ4にオフセット電圧が生じた場合、ポップノイズを抑えきれない問題が発生する。
Further, in the method of switching between the
本発明は上記問題点を解消し、製造上のバラツキ等に影響されること無く、低コストで高効率でありながらポップノイズ防止を図ったD級増幅器を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a class D amplifier that solves the above-described problems and is low-cost and high-efficiency while preventing pop noise without being affected by manufacturing variations.
上記課題を解決するために、請求項1にかかる発明は、入力PWM信号に応じてハイサイドドライブ用トランジスタおよびローサイドドライブ用トランジスタが交互にスイッチング動作をし、該スイッチングによる信号でAC結合用コンデンサを介してスピーカ又はヘッドフォンを駆動するD級増幅器において、前記ハイサイドドライブ用トランジスタのゲートを駆動する第1の駆動回路と、前記ローサイドドライブ用トランジスタのゲートを駆動する第2の駆動回路と、起動時又は復帰時に、前記第1および第2駆動回路の動作を時定数を持って立ち上げる制御手段とを設けたことを特徴とする。
In order to solve the above-mentioned problem, in the invention according to
請求項2にかかる発明は、請求項1に記載のD級増幅器において、前記制御手段として、前記第1の駆動回路と電源又は接地間に接続した第1の制御トランジスタと、起動時又は復帰時に該第1の制御トランジスタを時定数をもって導通させる第1の時定数回路と、該第2の駆動回路と電源又は接地間に接続した第2の制御トランジスタと、起動時又は復帰時に該第2の制御トランジスタを時定数をもって導通させる第2の時定数回路とを具備させたことを特徴とする。 According to a second aspect of the present invention, in the class D amplifier according to the first aspect, as the control means, a first control transistor connected between the first drive circuit and a power source or a ground, and at the time of starting or returning A first time constant circuit for conducting the first control transistor with a time constant; a second control transistor connected between the second drive circuit and a power supply or ground; and And a second time constant circuit for conducting the control transistor with a time constant.
本発明によれば、ハイサイドドライブ用、ローサイドドライブ用のトランジスタに直列に挿入される素子がないため、通常動作時には効率が低下することが無く、集積化してもチップサイズには大きく影響しないため、低コストで実現できる。また、出力ラインには電源起動直後から安定動作時までアンプを切り替えることがないため、製造バラツキ等により発生するオフセット等による、切り替え時の基準電圧変動によるポップノイズの発生も無いという利点がある。このため、かすかなポップノイズでも耳に不快に感じるような、携帯機器等のヘッドフォンに使用する場合においても、非常に有効である。 According to the present invention, since there is no element inserted in series with the transistors for high side drive and low side drive, the efficiency does not decrease during normal operation, and even if integrated, the chip size is not greatly affected. Can be realized at low cost. In addition, since the amplifier does not switch in the output line immediately after the power is turned on until the stable operation, there is an advantage that there is no occurrence of pop noise due to reference voltage fluctuation at the time of switching due to an offset generated due to manufacturing variation or the like. For this reason, it is very effective even when used for headphones such as portable devices, where even a faint pop noise feels uncomfortable to the ear.
図1は本発明の実施例のD級増幅器の構成を示す回路図である。SPは負荷となるスピーカまたはヘッドフォン、C1はAC結合用コンデンサ、L1はインダクタ、C2はコンデンサである。インダクタL1とコンデンサC2はローパスフィルタを構成する。M1はハイサイドドライブ用PMOSトランジスタ、M2はローサイドドライブ用NMOSトランジスタである。INV1はトランジスタM1のゲートを駆動するインバータ(第1の駆動回路)、INV2はトランジスタM2のゲートを駆動するインバータ(第2の駆動回路)である。M3はインバータINV1と接地間に接続されたNMOSトランジスタ(第1の制御トランジスタ)、M4はインバータINV2と電源VDD間に接続されたPMOSトランジスタ(第2の制御トランジスタ)である。M5はミュート動作時及び通常動作時にオン状態となるPMOSトランジスタ、M6はミュート動作時及び通常動作時にオン状態となるNMOSトランジスタである。R1,R2は抵抗、C3,C4はコンデンサであり、抵抗R1とコンデンサC3は第1のCR時定数回路を、抵抗R2とコンデンサC4は第2のCR時定数回路を構成する。M7はリセット期間にコンデンサC3の電荷を放電するためのNMOSトランジスタ、M8はリセット期間にコンデンサC4の電荷を放電するためのPMOSトランジスタである。INV3〜INV6はインバータ、ENはイネーブル端子、RESETはリセット端子、SIGは入力信号端子である。 FIG. 1 is a circuit diagram showing a configuration of a class D amplifier according to an embodiment of the present invention. SP is a speaker or headphone as a load, C1 is an AC coupling capacitor, L1 is an inductor, and C2 is a capacitor. The inductor L1 and the capacitor C2 constitute a low pass filter. M1 is a high-side drive PMOS transistor, and M2 is a low-side drive NMOS transistor. INV1 is an inverter (first drive circuit) that drives the gate of the transistor M1, and INV2 is an inverter (second drive circuit) that drives the gate of the transistor M2. M3 is an NMOS transistor (first control transistor) connected between the inverter INV1 and the ground, and M4 is a PMOS transistor (second control transistor) connected between the inverter INV2 and the power supply VDD. M5 is a PMOS transistor that is turned on during mute operation and normal operation, and M6 is an NMOS transistor that is turned on during mute operation and normal operation. R1 and R2 are resistors, and C3 and C4 are capacitors. The resistor R1 and the capacitor C3 constitute a first CR time constant circuit, and the resistor R2 and the capacitor C4 constitute a second CR time constant circuit. M7 is an NMOS transistor for discharging the charge of the capacitor C3 during the reset period, and M8 is a PMOS transistor for discharging the charge of the capacitor C4 during the reset period. INV3 to INV6 are inverters, EN is an enable terminal, RESET is a reset terminal, and SIG is an input signal terminal.
D級アンプの動作は、一般的には、音声周波数帯域の10倍以上のスイッチング周波数でハイサイドドライブ用トランジスタM1とローサイドドライブ用トランジスタM2を交互にスイッチング動作させる。スピーカSPの出力が無音状態では、AC結合用コンデンサC1の正極側の電圧は平均値でVDD/2となる。 In general, the operation of the class D amplifier is such that the high-side drive transistor M1 and the low-side drive transistor M2 are alternately switched at a switching frequency of 10 times or more of the audio frequency band. When the output of the speaker SP is silent, the voltage on the positive side of the AC coupling capacitor C1 is an average value of VDD / 2.
しかし、電源投入時及びスタンバイ状態からの復帰等のタイミング時に、動作を開始する瞬間には、矩形波のステップ応答の電圧が出力され、インダクタL1およびコンデンサC2で構成するローパスフィルタを通った後でも、AC結合用コンデンサC1の正極側には急激な電荷の変動が生じる。これがポップノイズとなり、特にヘッドフォンを使用する携帯型オーディオ再生機器においては、非常に不快な音となる。 However, at the moment when the operation is started at the time of turning on the power and returning from the standby state, the voltage of the step response of the rectangular wave is output and even after passing through the low-pass filter constituted by the inductor L1 and the capacitor C2. Then, a sudden charge fluctuation occurs on the positive electrode side of the AC coupling capacitor C1. This becomes pop noise, and particularly in a portable audio playback device using headphones, it becomes a very unpleasant sound.
そこで、本実施例では、ハイサイドドライブ用トランジスタM1のゲートを駆動するインバータINV1の接地側にトランジスタM3を接続し、動作開始時に、抵抗R1とコンデンサC3の時定数により、トランジスタM3のゲート電圧Vg3を徐々に上昇させることで、ハイサイドドライブ用トランジスタM1のゲートに加わる矩形波の波高値を徐々に上昇させ、ハイサイドドライブ用トランジスタM1のオン抵抗値Rm1を徐々に減少させる。 Therefore, in this embodiment, the transistor M3 is connected to the ground side of the inverter INV1 that drives the gate of the high-side drive transistor M1, and the gate voltage Vg3 of the transistor M3 is determined by the time constant of the resistor R1 and the capacitor C3 at the start of operation. Is gradually increased, the peak value of the rectangular wave applied to the gate of the high-side drive transistor M1 is gradually increased, and the on-resistance value Rm1 of the high-side drive transistor M1 is gradually decreased.
さらに詳しく説明すると、電源投入後、電源電圧VDDが安定するまでの期間は、RESET端子のレベルをHレベルとし、EN端子をLレベルにすることで、トランジスタM5がオフ、M7がオンとなり、トランジスタM7によりコンデンサC3の電荷は放電され、トランジスタM3はオフ状態となり、ハイサイドドライブ用トランジスタM1もオフ状態となる。 More specifically, after the power is turned on, during a period until the power supply voltage VDD is stabilized, the level of the RESET terminal is set to the H level and the EN terminal is set to the L level, whereby the transistor M5 is turned off and M7 is turned on. The electric charge of the capacitor C3 is discharged by M7, the transistor M3 is turned off, and the high side drive transistor M1 is also turned off.
この後、EN端子をHレベルにし、RESET端子をLレベルにすることで、トランジスタM5がオン、M7がオフとなり、抵抗R1を通って電荷がコンデンサC3に徐々に充電される。コンデンサC3の電圧が上昇するとトランジスタM3のゲート電位Vg3が上昇し、ハイサイドドライブ用トランジスタM1のゲートに印加される矩形波の波高値が徐々に上昇し、矩形波がHレベルの時のハイサイドドライブ用トランジスタM1のオン抵抗Rm1が徐々に減少する。 Thereafter, by setting the EN terminal to the H level and the RESET terminal to the L level, the transistor M5 is turned on, M7 is turned off, and the capacitor C3 is gradually charged through the resistor R1. When the voltage of the capacitor C3 rises, the gate potential Vg3 of the transistor M3 rises, the peak value of the rectangular wave applied to the gate of the high-side drive transistor M1 gradually rises, and the high side when the rectangular wave is at the H level The on-resistance Rm1 of the driving transistor M1 gradually decreases.
このため、AC結合用コンデンサC1は緩やかに波高値が上昇するパルスにより充電されるため、充電電圧Vaも緩やかに変化し、スピーカSPに加わる電圧Vbには急激な変化は現れないので、スピーカSPに印加される電圧変化は可聴域以下の周波数成分(f=1/tpop)となり、ポップノイズも発生しない。なお、ローサイドドライブ用トランジスタM2の動作に関しても、前述のハイサイドドライブ用トランジスタM1の動作と同様であるので、説明は省略する。 For this reason, the AC coupling capacitor C1 is charged by a pulse with a gradually increasing peak value, so that the charging voltage Va also changes gradually, and no sudden change appears in the voltage Vb applied to the speaker SP. The voltage change applied to is a frequency component (f = 1 / tpop) below the audible range, and no pop noise is generated. Note that the operation of the low-side drive transistor M2 is the same as that of the above-described high-side drive transistor M1, and a description thereof will be omitted.
以上の動作波形を図3に示した。図3において、Vg3はトランジスタM3のゲート電圧、Vg4はトランジスタM4のゲート電圧、Vg1はトランジスタM1のゲート電圧、Vg2はトランジスタM2のゲート電圧、Rm1はトランジスタM1のオン抵抗、Rm2はトランジスタM2のオン抵抗、VaはコンデンサC2の電圧、VbはスピーカSPに印加する電圧である。 The above operation waveforms are shown in FIG. In FIG. 3, Vg3 is the gate voltage of the transistor M3, Vg4 is the gate voltage of the transistor M4, Vg1 is the gate voltage of the transistor M1, Vg2 is the gate voltage of the transistor M2, Rm1 is the on-resistance of the transistor M1, and Rm2 is the on-state of the transistor M2. Resistance, Va is a voltage of the capacitor C2, and Vb is a voltage applied to the speaker SP.
なお、この動作は電源投入時だけでなく、長時間の待機時にAC結合用コンデンサC1の電荷がリークし、VDD/2から減少してしまっていても、待機状態からの復帰時に上記一連の動作を行えるため、復帰時のポップノイズも発生しないという利点もある。さらに、この回路をIC化した場合、コンデンサC3,C4の電流値を非常に小さい値にでき、これに伴いコンデンサC3,C4の容量も小さく出来るため、携帯機器等でも実装面積を増やすことなく、低コストで実現が可能である。さらに、図1における抵抗R1,R2は図2に示すように、電流源I1,I2に置き換えても同様に動作する。この場合は、コンデンサC3,C4が定電流充電されるので、ゲート電圧Vg3,Vg4が一定勾配で変化する。さらに、以上ではインバータINV1には接地との間に、インバータINV2には電源との間にそれぞれMOSトランジスタを接続したが、それらインバータINV1、INV2には電源又は接地のいずれか一方との間にトランジスタを接続し、起動時又は復帰時にそのトランジスタが時定数をもってオンするようにすればよい。 This operation is performed not only when the power is turned on, but also when the AC coupling capacitor C1 leaks during standby for a long time and decreases from VDD / 2. Therefore, there is an advantage that pop noise does not occur when returning. Furthermore, when this circuit is integrated into an IC, the current value of the capacitors C3 and C4 can be made very small, and the capacity of the capacitors C3 and C4 can be reduced accordingly. It can be realized at low cost. Further, the resistors R1 and R2 in FIG. 1 operate similarly even if they are replaced with current sources I1 and I2 as shown in FIG. In this case, since the capacitors C3 and C4 are charged with a constant current, the gate voltages Vg3 and Vg4 change with a constant gradient. Further, in the above description, MOS transistors are connected between the inverter INV1 and the ground, and the inverter INV2 is connected to the power source. However, the inverters INV1 and INV2 are connected to either the power source or the ground. So that the transistor is turned on with a time constant at start-up or return.
Claims (2)
前記ハイサイドドライブ用トランジスタのゲートを駆動する第1の駆動回路と、前記ローサイドドライブ用トランジスタのゲートを駆動する第2の駆動回路と、起動時又は復帰時に、前記第1および第2駆動回路の動作を時定数を持って立ち上げる制御手段とを設けたことを特徴とするD級増幅器。 In a class D amplifier in which a high-side drive transistor and a low-side drive transistor alternately perform switching operations according to an input PWM signal, and a speaker or a headphone is driven via an AC coupling capacitor by a signal by the switching.
A first drive circuit for driving the gate of the high-side drive transistor, a second drive circuit for driving the gate of the low-side drive transistor, and at the time of start-up or return, the first and second drive circuits A class D amplifier comprising a control means for starting up the operation with a time constant.
前記第1の駆動回路と電源又は接地間に接続した第1の制御トランジスタと、起動時又は復帰時に該第1の制御トランジスタを時定数をもって導通させる第1の時定数回路と、該第2の駆動回路と電源又は接地間に接続した第2の制御トランジスタと、起動時又は復帰時に該第2の制御トランジスタを時定数をもって導通させる第2の時定数回路とを具備することを特徴とするD級増幅器。 The class D amplifier according to claim 1, wherein the control means includes:
A first control transistor connected between the first drive circuit and a power source or the ground; a first time constant circuit for conducting the first control transistor with a time constant at start-up or return; and A second control transistor connected between the driving circuit and the power source or the ground; and a second time constant circuit for conducting the second control transistor with a time constant at the time of start-up or return. Class amplifier.
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JP2005025874A JP4654047B2 (en) | 2005-02-02 | 2005-02-02 | Class D amplifier |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7764119B2 (en) | 2007-03-01 | 2010-07-27 | Fujitsu Semiconductor Limited | Voltage control circuit |
US8044719B2 (en) | 2009-03-11 | 2011-10-25 | Yamaha Corporation | Class D amplifier circuit |
JP2013121023A (en) * | 2011-12-06 | 2013-06-17 | Onkyo Corp | Switching amplifier |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5687717U (en) * | 1979-12-06 | 1981-07-14 | ||
JP2001223538A (en) * | 2000-02-14 | 2001-08-17 | Rohm Co Ltd | Mute circuit and digital audio amplifier circuit |
WO2004019483A2 (en) * | 2002-08-23 | 2004-03-04 | Tripath Technology, Inc. | Providing dc isolation in switching amplifiers |
-
2005
- 2005-02-02 JP JP2005025874A patent/JP4654047B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5687717U (en) * | 1979-12-06 | 1981-07-14 | ||
JP2001223538A (en) * | 2000-02-14 | 2001-08-17 | Rohm Co Ltd | Mute circuit and digital audio amplifier circuit |
WO2004019483A2 (en) * | 2002-08-23 | 2004-03-04 | Tripath Technology, Inc. | Providing dc isolation in switching amplifiers |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7764119B2 (en) | 2007-03-01 | 2010-07-27 | Fujitsu Semiconductor Limited | Voltage control circuit |
KR100983854B1 (en) * | 2007-03-01 | 2010-09-28 | 후지쯔 세미컨덕터 가부시키가이샤 | Voltage control circuit |
US8044719B2 (en) | 2009-03-11 | 2011-10-25 | Yamaha Corporation | Class D amplifier circuit |
JP2013121023A (en) * | 2011-12-06 | 2013-06-17 | Onkyo Corp | Switching amplifier |
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